Lines Matching +full:1 +full:c600000
21 #define SPEAR1310_CLCD_SYNT_CLK_MASK 1
43 #define SPEAR1310_GPT_APB_VAL 1
44 #define SPEAR1310_GPT_CLK_MASK 1
50 #define SPEAR1310_UART_CLK_OSC24_VAL 1
56 #define SPEAR1310_AUX_CLK_SYNT_VAL 1
59 #define SPEAR1310_C3_CLK_MASK 1
60 #define SPEAR1310_C3_CLK_SHIFT 1
65 #define SPEAR1310_GMAC_PHY_CLK_MASK 1
68 #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1
83 #define SPEAR1310_I2S_REF_SEL_MASK 1
132 #define SPEAR1310_SYSROM_CLK_ENB 1
144 #define SPEAR1310_DDR_CORE_CLK_ENB 1
165 #define SPEAR1310_PCLK_CLK_ENB 1
172 #define SPEAR1310_TDM_CLK_MASK 1
175 #define SPEAR1310_I2C_CLK_MASK 1
183 #define SPEAR1310_GPT64_CLK_MASK 1
185 #define SPEAR1310_RAS_UART_CLK_MASK 1
191 #define SPEAR1310_PCI_CLK_MASK 1
224 #define SPEAR1310_MII0_CLK_ENB 1
238 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
246 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
256 {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
257 {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
265 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
266 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
311 {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
313 {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
320 {.xscale = 1, .yscale = 3, .eq = 0},
325 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
331 {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */
332 {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
339 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
458 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1, in spear1310_clk_init()
462 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1, in spear1310_clk_init()
466 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1, in spear1310_clk_init()
470 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1, in spear1310_clk_init()
475 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1, in spear1310_clk_init()
483 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1, in spear1310_clk_init()
484 1); in spear1310_clk_init()
489 CLK_SET_RATE_PARENT, 1, 2); in spear1310_clk_init()
492 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, in spear1310_clk_init()
496 clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1, in spear1310_clk_init()
500 clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1, in spear1310_clk_init()
504 clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1, in spear1310_clk_init()
906 clk_register_clkdev(clk, NULL, "c_can_platform.1"); in spear1310_clk_init()
921 clk_register_clkdev(clk, NULL, "5c600000.eth"); in spear1310_clk_init()
934 clk_register_clkdev(clk, "stmmacphy.1", NULL); in spear1310_clk_init()
1118 clk_register_clkdev(clk, NULL, "tdm_hdlc.1"); in spear1310_clk_init()