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/linux/Documentation/devicetree/bindings/cache/
H A Dsifive,ccache0.yaml25 - sifive,fu540-c000-ccache
26 - sifive,fu740-c000-ccache
37 - sifive,fu540-c000-ccache
38 - sifive,fu740-c000-ccache
49 - const: sifive,fu540-c000-ccache
54 - const: sifive,fu540-c000-ccache
80 maxItems: 1
85 maxItems: 1
99 - sifive,fu740-c000-ccache
139 - sifive,fu740-c000-ccache
[all …]
/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
38 #interrupt-cells = <1>;
43 cpu1: cpu@1 {
48 d-tlb-sets = <1>;
54 i-tlb-sets = <1>;
57 reg = <1>;
65 #interrupt-cells = <1>;
75 d-tlb-sets = <1>;
81 i-tlb-sets = <1>;
[all …]
H A Dfu740-c000.dtsi11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
39 #interrupt-cells = <1>;
44 cpu1: cpu@1 {
49 d-tlb-sets = <1>;
55 i-tlb-sets = <1>;
66 #interrupt-cells = <1>;
76 d-tlb-sets = <1>;
82 i-tlb-sets = <1>;
93 #interrupt-cells = <1>;
[all …]
H A Dhifive-unleashed-a00.dts4 #include "fu540-c000.dtsi"
14 compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000",
59 pwms = <&pwm0 1 7812500 0>;
/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm-sifive.yaml30 - sifive,fu540-c000-pwm
31 - sifive,fu740-c000-pwm
35 compatible strings are "sifive,fu540-c000-pwm" and
36 "sifive,fu740-c000-pwm" for the SiFive PWM v0 as integrated onto the
42 maxItems: 1
45 maxItems: 1
53 Each PWM instance in FU540-C000 has 4 comparators. One interrupt per comparator.
66 compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
/linux/Documentation/devicetree/bindings/gpio/
H A Dsifive,gpio.yaml16 - sifive,fu540-c000-gpio
17 - sifive,fu740-c000-gpio
22 maxItems: 1
27 minItems: 1
36 maxItems: 1
45 minimum: 1
50 minItems: 1
69 - sifive,fu540-c000-gpio
70 - sifive,fu740-c000-gpio
81 compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
/linux/Documentation/devicetree/bindings/spi/
H A Dspi-sifive.yaml21 - sifive,fu540-c000-spi
22 - sifive,fu740-c000-spi
28 "sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v0
37 minItems: 1
43 maxItems: 1
46 maxItems: 1
62 enum: [0, 1, 2, 3, 4, 5, 6, 7, 8]
76 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
81 #address-cells = <1>;
/linux/arch/arm64/boot/dts/qcom/
H A Dsa8540p-pmics.dtsi14 #address-cells = <1>;
25 pmm8540a_gpios: gpio@c000 {
39 #address-cells = <1>;
45 #address-cells = <1>;
46 #size-cells = <1>;
51 pmm8540c_gpios: gpio@c000 {
65 #address-cells = <1>;
68 pmm8540e_gpios: gpio@c000 {
82 #address-cells = <1>;
85 pmm8540g_gpios: gpio@c000 {
H A Dsc8180x-pmics.dtsi72 #address-cells = <1>;
101 #address-cells = <1>;
103 #io-channel-cells = <1>;
108 qcom,pre-scaling = <1 1>;
112 channel@1 {
114 qcom,pre-scaling = <1 1>;
120 qcom,pre-scaling = <1 1>;
129 #thermal-sensor-cells = <1>;
130 #address-cells = <1>;
142 pmc8180_1_gpios: gpio@c000 {
[all …]
/linux/Documentation/devicetree/bindings/i2c/
H A Dopencores,i2c-ocores.yaml21 - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC
22 - sifive,fu540-c000-i2c # Opencore based IP block FU540-C000 SoC
29 maxItems: 1
32 maxItems: 1
35 maxItems: 1
55 enum: [1, 2, 4]
93 #address-cells = <1>;
99 reg-io-width = <1>; /* 8 bit read/write */
105 #address-cells = <1>;
112 reg-io-width = <1>; /* 8 bit read/write */
/linux/arch/powerpc/boot/dts/fsl/
H A Dt4240si-post.dtsi52 #size-cells = <1>;
66 #interrupt-cells = <1>;
75 0000 0 0 1 &mpic 40 1 0 0
76 0000 0 0 2 &mpic 1 1 0 0
77 0000 0 0 3 &mpic 2 1 0 0
78 0000 0 0 4 &mpic 3 1 0 0
92 #interrupt-cells = <1>;
101 0000 0 0 1 &mpic 41 1 0 0
102 0000 0 0 2 &mpic 5 1 0 0
103 0000 0 0 3 &mpic 6 1 0 0
[all …]
H A Db4860si-post.dtsi44 interrupts = <16 2 1 20>;
53 cell-index = <1>;
116 bman-portal@3c000 {
136 bman-portal@4c000 {
156 bman-portal@5c000 {
175 qportal15: qman-portal@3c000 {
199 qportal19: qman-portal@4c000 {
223 qportal23: qman-portal@5c000 {
241 interrupts = <16 2 1 9>;
261 /include/ "qoriq-fman3-0-1g-4.dtsi"
[all …]
H A Dt2081si-post.dtsi52 #size-cells = <1>;
68 #interrupt-cells = <1>;
76 0000 0 0 1 &mpic 40 1 0 0
77 0000 0 0 2 &mpic 1 1 0 0
78 0000 0 0 3 &mpic 2 1 0 0
79 0000 0 0 4 &mpic 3 1 0 0
95 #interrupt-cells = <1>;
103 0000 0 0 1 &mpic 41 1 0 0
104 0000 0 0 2 &mpic 5 1 0 0
105 0000 0 0 3 &mpic 6 1 0 0
[all …]
H A Db4si-post.dtsi52 #size-cells = <1>;
67 #interrupt-cells = <1>;
76 0000 0 0 1 &mpic 40 1 0 0
77 0000 0 0 2 &mpic 1 1 0 0
78 0000 0 0 3 &mpic 2 1 0 0
79 0000 0 0 4 &mpic 3 1 0 0
85 #address-cells = <1>;
86 #size-cells = <1>;
166 bman-portal@c000 {
186 bman-portal@1c000 {
[all …]
H A Dqoriq-bman1-portals.dtsi36 #address-cells = <1>;
37 #size-cells = <1>;
55 bman-portal@c000 {
75 bman-portal@1c000 {
H A Dqoriq-qman1-portals.dtsi36 #address-cells = <1>;
37 #size-cells = <1>;
50 cell-index = <1>;
58 qportal3: qman-portal@c000 {
83 qportal7: qman-portal@1c000 {
/linux/Documentation/devicetree/bindings/serial/
H A Dsifive-serial.yaml21 - sifive,fu540-c000-uart
22 - sifive,fu740-c000-uart
38 maxItems: 1
41 maxItems: 1
44 maxItems: 1
58 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
/linux/Documentation/devicetree/bindings/clock/sifive/
H A Dfu540-prci.yaml26 const: sifive,fu540-c000-prci
29 maxItems: 1
42 const: 1
55 compatible = "sifive,fu540-c000-prci";
58 #clock-cells = <1>;
H A Dfu740-prci.yaml27 const: sifive,fu740-c000-prci
30 maxItems: 1
43 const: 1
46 const: 1
59 compatible = "sifive,fu740-c000-prci";
62 #clock-cells = <1>;
63 #reset-cells = <1>;
/linux/arch/arm/boot/dts/rockchip/
H A Drk3xxx.dtsi12 #address-cells = <1>;
13 #size-cells = <1>;
73 scu@1013c000 {
112 reg-io-width = <1>;
123 reg-io-width = <1>;
214 dmas = <&dmac2 1>;
236 emmc: mmc@1021c000 {
282 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
283 #dma-cells = <1>;
290 dmac1_ns: dma-controller@2001c000 {
[all …]
/linux/drivers/dma/sf-pdma/
H A Dsf-pdma.h13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
44 #define PDMA_RUN_MASK GENMASK(1, 1)
55 #define MAX_RETRY 1
/linux/arch/arm/boot/dts/qcom/
H A Dpm8226.dtsi41 #address-cells = <1>;
58 interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
71 <0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>,
74 <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>,
75 <0x0 0x14 1 IRQ_TYPE_EDGE_BOTH>;
103 #address-cells = <1>;
105 #io-channel-cells = <1>;
109 qcom,pre-scaling = <1 3>;
155 pm8226_gpios: gpio@c000 {
166 pm8226_1: pm8226@1 {
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dti-omap-hsmmc.txt22 - ti,hwmods: Must be "mmc<n>", n is controller instance starting 1.
50 1:1 with the DMA specifiers listed in dmas.
58 mmc1: mmc@4809c000 {
70 mmc1: mmc@4809c000 {
111 1. select matching 'compatible' section, see example below.
124 pinctrl-1 = <&mmc1_idle>;
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-colibri-eval-v3.dts13 rtc0 = "/i2c@7000c000/rtc@68";
64 i2c@7000c000 {
107 no-1-8-v;
152 gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
194 regulator-name = "VCC_USB[1-4]";
H A Dtegra30-apalis-eval.dts13 rtc0 = "/i2c@7000c000/rtc@68";
27 pci@1,0 {
90 i2c@7000c000 {
135 no-1-8-v;
144 no-1-8-v;
158 /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
193 gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
241 gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;

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