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/linux/drivers/clk/spear/
H A Dspear1340_clock.c21 #define SPEAR1340_HCLK_SRC_SEL_MASK 1
28 #define SPEAR1340_CLCD_SYNT_CLK_MASK 1
48 #define SPEAR1340_SPDIF_CLK_MASK 1
53 #define SPEAR1340_GPT_CLK_MASK 1
61 #define SPEAR1340_C3_CLK_MASK 1
62 #define SPEAR1340_C3_CLK_SHIFT 1
65 #define SPEAR1340_GMAC_PHY_CLK_MASK 1
83 #define SPEAR1340_I2S_REF_SEL_MASK 1
128 #define SPEAR1340_SYSROM_CLK_ENB 1
139 #define SPEAR1340_DDR_CORE_CLK_ENB 1
[all …]
H A Dspear1310_clock.c21 #define SPEAR1310_CLCD_SYNT_CLK_MASK 1
43 #define SPEAR1310_GPT_APB_VAL 1
44 #define SPEAR1310_GPT_CLK_MASK 1
50 #define SPEAR1310_UART_CLK_OSC24_VAL 1
56 #define SPEAR1310_AUX_CLK_SYNT_VAL 1
59 #define SPEAR1310_C3_CLK_MASK 1
60 #define SPEAR1310_C3_CLK_SHIFT 1
65 #define SPEAR1310_GMAC_PHY_CLK_MASK 1
68 #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1
83 #define SPEAR1310_I2S_REF_SEL_MASK 1
[all …]
/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
43 # 2 chars 1 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
64 # 7 chars 1 lines
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_consts.h85 .blks_per_clk = 1,
104 .blks_per_clk = 1,
120 .tx_mode = { .def = 1, },
121 .rx_mode = { .def = 1, },
122 .blks_per_clk = 1,
141 .def = 1,
146 .def = 1,
150 .def = 1,
154 .def = 1,
155 .rs = 1
[all …]
/linux/drivers/clk/mvebu/
H A Dmv98dx3236.c25 * 0 = 400 MHz 400 MHz 800 MHz
26 * 2 = 667 MHz 667 MHz 2000 MHz
27 * 3 = 800 MHz 800 MHz 1600 MHz
34 * 1 = 667 MHz 667 MHz 2000 MHz
35 * 2 = 400 MHz 400 MHz 400 MHz
36 * 3 = 800 MHz 800 MHz 800 MHz
37 * 5 = 800 MHz 400 MHz 800 MHz
46 /* Tclk = 200MHz, no SaR dependency */ in mv98dx3236_get_tclk_freq()
98 {0, 1}, {3, 1}, {1, 1}, {1, 1},
99 {0, 1}, {1, 1}, {0, 1}, {0, 1},
[all …]
H A Darmada-375.c29 * 6 = 400 MHz 400 MHz 200 MHz
30 * 15 = 600 MHz 600 MHz 300 MHz
31 * 21 = 800 MHz 534 MHz 400 MHz
32 * 25 = 1000 MHz 500 MHz 500 MHz
36 * 0 = 166 MHz
37 * 1 = 200 MHz
93 {0, 1}, {0, 1}, {0, 1}, {0, 1},
94 {0, 1}, {0, 1}, {1, 2}, {0, 1},
95 {0, 1}, {0, 1}, {0, 1}, {0, 1},
96 {0, 1}, {0, 1}, {0, 1}, {1, 2},
[all …]
H A Ddove.c26 * 5 = 1000 MHz
27 * 6 = 933 MHz
28 * 7 = 933 MHz
29 * 8 = 800 MHz
30 * 9 = 800 MHz
31 * 10 = 800 MHz
32 * 11 = 1067 MHz
33 * 12 = 667 MHz
34 * 13 = 533 MHz
35 * 14 = 400 MHz
[all …]
/linux/arch/x86/kernel/
H A Dtsc_msr.c22 * The frequency numbers in the SDM are e.g. 83.3 MHz, which does not contain a
24 * use a 25 MHz crystal and Cherry Trail uses a 19.2 MHz crystal, the crystal
25 * is the source clk for a root PLL which outputs 1600 and 100 MHz. It is
31 * clock of 100 MHz plus a quotient which gets us as close to the frequency
33 * For the 83.3 MHz example from above this would give us 100 MHz * 5 / 6 =
34 * 83 and 1/3 MHz, which matches exactly what has been measured on actual hw.
80 * 000: 100 * 5 / 6 = 83.3333 MHz
81 * 001: 100 * 1 / 1 = 100.0000 MHz
82 * 010: 100 * 4 / 3 = 133.3333 MHz
83 * 011: 100 * 7 / 6 = 116.6667 MHz
[all …]
/linux/arch/arm/mach-omap2/
H A Dopp2xxx.h20 * 2430 (iva2.1, NOdsp, mdm)
45 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
48 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
68 /* 2430 Ratio's, 2430-Ratio Config 1 */
103 #define RB_CLKSEL_L3 (1 << 0)
104 #define RB_CLKSEL_L4 (1 << 5)
105 #define RB_CLKSEL_USB (1 << 25)
109 #define RB_CLKSEL_MPU (1 << 0)
111 #define RB_CLKSEL_DSP (1 << 0)
112 #define RB_CLKSEL_DSP_IF (1 << 5)
[all …]
/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_mipi_dsi.c31 #define MHZ(v) ((u32)((v) * 1000000U)) macro
102 { MHZ(80), 0x00 }, { MHZ(90), 0x10 }, { MHZ(100), 0x20 },
103 { MHZ(110), 0x30 }, { MHZ(120), 0x01 }, { MHZ(130), 0x11 },
104 { MHZ(140), 0x21 }, { MHZ(150), 0x31 }, { MHZ(160), 0x02 },
105 { MHZ(170), 0x12 }, { MHZ(180), 0x22 }, { MHZ(190), 0x32 },
106 { MHZ(205), 0x03 }, { MHZ(220), 0x13 }, { MHZ(235), 0x23 },
107 { MHZ(250), 0x33 }, { MHZ(275), 0x04 }, { MHZ(300), 0x14 },
108 { MHZ(325), 0x25 }, { MHZ(350), 0x35 }, { MHZ(400), 0x05 },
109 { MHZ(450), 0x16 }, { MHZ(500), 0x26 }, { MHZ(550), 0x37 },
110 { MHZ(600), 0x07 }, { MHZ(650), 0x18 }, { MHZ(700), 0x28 },
[all …]
/linux/arch/mips/txx9/rbtx4927/
H A Dsetup.c75 writeb(1, rbtx4927_pcireset_addr); in tx4927_pci_setup()
93 writeb(1, rbtx4927_pcireset_addr); in tx4927_pci_setup()
122 writeb(1, rbtx4927_pcireset_addr); in tx4937_pci_setup()
140 writeb(1, rbtx4927_pcireset_addr); in tx4937_pci_setup()
164 gpio_direction_output(15, 1); in rbtx4927_gpio_init()
190 writeb(1, rbtx4927_softresetlock_addr); in toshiba_rbtx4927_restart()
193 while (!(readb(rbtx4927_softresetlock_addr) & 1)) in toshiba_rbtx4927_restart()
197 writeb(1, rbtx4927_softreset_addr); in toshiba_rbtx4927_restart()
231 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. in rbtx4927_clock_init()
234 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1). in rbtx4927_clock_init()
[all …]
/linux/drivers/media/tuners/
H A Dtuner-types.c65 { 16 * 140.25 /*MHz*/, 0x8e, 0x02, },
66 { 16 * 463.25 /*MHz*/, 0x8e, 0x04, },
81 { 16 * 140.25 /*MHz*/, 0x8e, 0xa0, },
82 { 16 * 463.25 /*MHz*/, 0x8e, 0x90, },
97 { 16 * 157.25 /*MHz*/, 0x8e, 0xa0, },
98 { 16 * 451.25 /*MHz*/, 0x8e, 0x90, },
107 .cb_first_if_lower_freq = 1,
114 { 16 * 168.25 /*MHz*/, 0x8e, 0xa7, },
115 { 16 * 447.25 /*MHz*/, 0x8e, 0x97, },
124 .cb_first_if_lower_freq = 1,
[all …]
H A Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
35 14 1f ?
41 1a d0 set frequency: 125 kHz scale, n*125 kHz
42 1b 00 ?
43 1c 89 ?
44 1d 00 ?
45 1e 00 ? looks like operation register; write cmd here, read result from 1f-26
[all …]
/linux/drivers/media/usb/dvb-usb-v2/
H A Daf9035.h56 u8 dual_mode:1;
57 u8 no_read:1;
75 { 0x67, 0x63, 1 },
81 16384000, /* 16.38 MHz */
82 20480000, /* 20.48 MHz */
83 36000000, /* 36.00 MHz */
84 30000000, /* 30.00 MHz */
85 26000000, /* 26.00 MHz */
86 28000000, /* 28.00 MHz */
87 32000000, /* 32.00 MHz */
[all …]
/linux/Documentation/userspace-api/media/dvb/
H A Dfe-bandwidth-t.rst10 :header-rows: 1
14 - .. row 1
30 - .. _BANDWIDTH-1-712-MHZ:
34 - 1.712 MHz
38 - .. _BANDWIDTH-5-MHZ:
42 - 5 MHz
46 - .. _BANDWIDTH-6-MHZ:
50 - 6 MHz
54 - .. _BANDWIDTH-7-MHZ:
58 - 7 MHz
[all …]
/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
13 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
25 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6)
28 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
32 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_vangogh.h45 uint16_t Freq; // in MHz
50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
62 #define WM_RETRAINING 1
124 //Freq in MHz
156 #define THROTTLER_STATUS_BIT_FPPT 1
168 uint16_t GfxclkFrequency; //[MHz]
169 uint16_t SocclkFrequency; //[MHz]
170 uint16_t VclkFrequency; //[MHz]
171 uint16_t DclkFrequency; //[MHz]
[all …]
H A Dsmu11_driver_if_sienna_cichlid.h53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
54 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
55 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
57 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
58 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
61 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
62 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
[all …]
/linux/Documentation/devicetree/bindings/cpu/
H A Dcpu-capacity.txt6 1 - Introduction
38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
61 Example 1 (ARM 64-bit, 6-cpu system, two clusters):
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
[all …]
/linux/net/mac80211/tests/
H A Dtpe.c34 .desc = "identical 20 MHz",
38 .n = 1,
42 .desc = "identical 40 MHz",
50 .desc = "identical 80+80 MHz",
60 .desc = "identical 320 MHz",
68 .desc = "lower 160 MHz of 320 MHz",
76 .desc = "upper 160 MHz of 320 MHz",
84 .desc = "upper 160 MHz of 320 MHz, go to 40",
92 .desc = "secondary 80 above primary in 80+80 MHz",
102 .desc = "secondary 80 below primary in 80+80 MHz",
[all …]
/linux/drivers/clk/samsung/
H A Dclk-exynos3250.c92 #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
93 #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
94 #define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
95 #define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
96 #define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
97 #define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
98 #define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
99 #define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
100 #define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
101 #define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
[all …]
/linux/tools/testing/selftests/intel_pstate/
H A Drun.sh6 # state to the minimum supported frequency, in decrements of 100MHz. The
10 # or the requested frequency in MHz, the Actual frequency, as read from
22 #/tmp/result.3100:1:cpu MHz : 2899.980
23 #/tmp/result.3100:2:cpu MHz : 2900.000
28 # for consistency and modified to remove the extra MHz values. The result.X
29 # files can be re-evaluated by setting EVALUATE_ONLY to 1 below.
52 max_cpus=$(($(nproc)-1))
56 file_ext=$1
65 grep MHz /proc/cpuinfo | sort -u > /tmp/result.freqs
66 num_freqs=$(wc -l /tmp/result.freqs | awk ' { print $1 } ')
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dphy_shim.h27 #define RADAR_TYPE_ETSI_1 1 /* ETSI 1 Radar type */
49 #define ANTSEL_2x4 1 /* 2x4 boardlevel selection available */
54 #define ANT_RX_DIV_FORCE_1 1 /* Use antenna 1 */
55 #define ANT_RX_DIV_START_1 2 /* Choose starting with 1 */
62 #define WL_ANT_IDX_1 0 /* antenna index 1 */
63 #define WL_ANT_IDX_2 1 /* antenna index 2 */
67 #define BRCMS_N_PREAMBLE_GF 1
80 /* Index for first 20MHz OFDM SISO rate */
82 /* Index for first 20MHz OFDM CDD rate */
84 /* Index for first 40MHz OFDM SISO rate */
[all …]
/linux/drivers/media/i2c/cx25840/
H A Dcx25840-core.c71 MODULE_PARM_DESC(debug, "Debugging messages [0=Off (default) 1=On]");
81 buffer[1] = addr & 0xff; in cx25840_write()
91 buffer[1] = addr & 0xff; in cx25840_write4()
102 u8 tx_buf[2], rx_buf[1]; in cx25840_read()
106 tx_buf[1] = addr & 0xff; in cx25840_read()
113 msgs[1].addr = client->addr; in cx25840_read()
114 msgs[1].flags = I2C_M_RD; in cx25840_read()
115 msgs[1].len = 1; in cx25840_read()
116 msgs[1].buf = (char *)rx_buf; in cx25840_read()
131 tx_buf[1] = addr & 0xff; in cx25840_read4()
[all …]
/linux/drivers/media/i2c/et8ek8/
H A Det8ek8_mode.c19 /* (without the +1)
20 * SPCK = 80 MHz
21 * CCP2 = 640 MHz
22 * VCO = 640 MHz
93 /* Switch of Preset-White-balance (0d:disable / 1d:enable) */
95 /* Switch of blemish correction (0d:disable / 1d:enable) */
97 /* Switch of auto noise correction (0d:disable / 1d:enable) */
120 /* (without the +1)
121 * SPCK = 80 MHz
122 * CCP2 = 560 MHz
[all …]

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