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/freebsd/share/man/man4/
H A Diwlwifi.412 .\" 1. Redistributions of source code must retain the above copyright
139 .\" seen[$2]=1; printf ".It\n%s\n", $2; }' iwlwifi_pci_ids_name.txt
174 Killer (R) Wireless-AC 1550 Wireless Network Adapter (9260NGW) 160MHz
180 Killer(R) Wireless-AC 1550s Wireless Network Adapter (9560D2W) 160MHz
182 Killer(R) Wireless-AC 1550i Wireless Network Adapter (9560NGW) 160MHz
184 Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)
186 Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)
188 Intel(R) Wireless-AC 9260-1
190 Intel(R) Wi-Fi 6 AX200 160MHz
192 Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)
[all …]
H A Dahc.410 .\" 1. Redistributions of source code must retain the above copyright
93 .It "aic7770" Ta "10" Ta "VL" Ta "10MHz" Ta "16Bit" Ta "4" Ta "1"
94 .It "aic7850" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "8Bit" Ta "3" Ta ""
95 .It "aic7860" Ta "10" Ta "PCI/32" Ta "20MHz" Ta "8Bit" Ta "3" Ta ""
96 .It "aic7870" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "16Bit" Ta "16" Ta ""
97 .It "aic7880" Ta "10" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta ""
98 .It "aic7890" Ta "20" Ta "PCI/32" Ta "40MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
99 .It "aic7891" Ta "20" Ta "PCI/64" Ta "40MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
100 .It "aic7892" Ta "20" Ta "PCI/64" Ta "80MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
101 .It "aic7895" Ta "15" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5"
[all …]
H A Dsym.437 .\" 1. Redistributions of source code must retain the above copyright
110 As a result, it guarantees that no more than 1 interrupt
143 a value of 1, the driver will also probe against HVD for 825a, 875, 876 and
204 .Bl -column sym53c1510d "80MHz" "Width" "SRAM" "PCI64"
206 .It "sym53c810 10MHz 8Bit N N Y"
207 .It "sym53c810a 10MHz 8Bit N N Y"
208 .It "sym53c815 10MHz 8Bit N N Y"
209 .It "sym53c825 10MHz 16Bit N N Y"
210 .It "sym53c825a 10MHz 16Bit 4KB N Y"
211 .It "sym53c860 20MHz 8Bit N N Y"
[all …]
/freebsd/contrib/tcpdump/
H A Dprint-802_11.c7 * modification, are permitted provided that: (1) source code distributions
53 #define IEEE802_11_KID_LEN 1
195 u_char ssid[33]; /* 32 + 1 for null */
205 uint8_t text[254]; /* 1-253 + 1 for null */
238 #define E_RATES 1
430 * 0 for 20 MHz, 1 for 40 MHz;
432 * 0 for a long guard interval, 1 for a short guard interval.
434 static const float ieee80211_float_htrates[MAX_MCS_INDEX+1][2][2] = {
436 { /* 20 Mhz */ { 6.5f, /* SGI */ 7.2f, },
437 /* 40 Mhz */ { 13.5f, /* SGI */ 15.0f, },
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dcpu-capacity.txt6 1 - Introduction
38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
61 Example 1 (ARM 64-bit, 6-cpu system, two clusters):
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A Dcpu-capacity.txt6 1 - Introduction
38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
61 Example 1 (ARM 64-bit, 6-cpu system, two clusters):
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
[all …]
/freebsd/contrib/wpa/src/common/
H A Dieee802_11_common.c35 return -1; in ieee802_11_parse_vendor_specific()
44 case 1: in ieee802_11_parse_vendor_specific()
45 /* Microsoft OUI (00:50:F2) with OUI Type 1: in ieee802_11_parse_vendor_specific()
57 return -1; in ieee802_11_parse_vendor_specific()
80 return -1; in ieee802_11_parse_vendor_specific()
93 return -1; in ieee802_11_parse_vendor_specific()
148 return -1; in ieee802_11_parse_vendor_specific()
165 return -1; in ieee802_11_parse_vendor_specific()
172 return -1; in ieee802_11_parse_vendor_specific()
186 return -1; in ieee802_11_parse_vendor_specific()
[all …]
H A Dhw_features_common.c130 return 1; /* HT40 not used */ in allowed_ht40_channel_pair()
138 "HT40: control channel: %d (%d MHz), secondary channel: %d (%d MHz)", in allowed_ht40_channel_pair()
141 /* Verify that HT40 secondary channel is an allowed 20 MHz in allowed_ht40_channel_pair()
158 return 1; in allowed_ht40_channel_pair()
165 ok = 1; in allowed_ht40_channel_pair()
175 return 1; in allowed_ht40_channel_pair()
186 if (ieee802_11_parse_elems((u8 *) (bss + 1), bss->ie_len, &elems, 0) != in get_pri_sec_chan()
244 match = 1; in check_40mhz_5g()
263 return 1; in check_40mhz_5g()
276 if (ieee802_11_parse_elems((u8 *) (bss + 1), bss->ie_len, &elems, 0) == in check_20mhz_bss()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Domap-usb-host.txt16 from 1 to 3. If the port mode is not specified, that port is treated
33 ULPI bypass control bit. e.g. OMAP3 silicon <= ES2.1
40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
46 * "utmi_p1_gfclk" - Port 1 UTMI clock mux.
48 * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dsamsung,exynos850-clock.yaml20 two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
49 minItems: 1
53 minItems: 1
57 const: 1
60 maxItems: 1
73 - description: External reference clock (26 MHz)
89 - description: External reference clock (26 MHz)
107 - description: External reference clock (26 MHz)
125 - description: External reference clock (26 MHz)
143 - description: External reference clock (26 MHz)
[all …]
H A Dsamsung,exynosautov9-clock.yaml20 two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
47 minItems: 1
51 minItems: 1
55 const: 1
58 maxItems: 1
71 - description: External reference clock (26 MHz)
87 - description: External reference clock (26 MHz)
105 - description: External reference clock (26 MHz)
123 - description: External reference clock (26 MHz)
141 - description: External reference clock (26 MHz)
[all …]
H A Dtesla,fsd-clock.yaml16 The root clock comes from external OSC clock (24 MHz).
33 minItems: 1
37 minItems: 1
41 const: 1
44 maxItems: 1
56 - description: External reference clock (24 MHz)
70 - description: External reference clock (24 MHz)
90 - description: External reference clock (24 MHz)
114 - description: External reference clock (24 MHz)
134 - description: External reference clock (24 MHz)
[all …]
H A Darmada3700-periph-clock.txt16 1 sata_host Sata Host
25 10 i2c_1 I2C 1
36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
37 1 gbe-core parent clock for Gigabit Ethernet core
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
43 7 gbe1-core Gigabit Ethernet core port 1
[all …]
H A Dmaxim,max9485.txt5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
8 - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
10 MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set
15 - clocks: Input clock, must provide 27.000 MHz
17 - #clock-cells: From common clock binding; shall be set to 1
34 xo-27mhz: xo-27mhz {
45 clocks = <&xo-27mhz>;
46 reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
48 #clock-cells = <1>;
[all...]
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Drs.h16 * bandwidths <= 80MHz
18 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
21 * for BPSK (MCS 0) with 1 spatial
30 IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK = BIT(1),
39 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
40 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
41 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
42 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
43 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
60 IWL_TLC_MNG_CHAIN_B_MSK = BIT(1),
[all …]
H A Dphy-ctxt.h12 #define PHY_BAND_24 (1)
20 /* and 320 MHz for EHT */
27 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
31 * 40Mhz |____|____|
32 * 80Mhz |____|____|____|____|
33 * 160Mhz |____|____|____|____|____|____|____|____|
34 * 320MHz |____|____|____|____|____|____|____|____|____|____|____|____|____|____|____|____|
76 #define PHY_RX_CHAIN_VALID_POS (1)
145 * @sbb_bandwidth: 0 disabled, 1 - 40Mhz ... 4 - 320MHz
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dintegratorcp.dts18 #address-cells = <1>;
39 clock-latency = <1000000>; /* 1 ms */
49 /* The codec chrystal operates at 24.576 MHz */
61 clock-mult = <1>;
65 /* This is a 25MHz chrystal on the base board */
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
115 auxosc: clock-controller@1c {
124 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
125 kmiclk: kmiclk@1M {
[all …]
/freebsd/contrib/wpa/wpa_supplicant/
H A Dop_classes.c59 * In 80 MHz, the bandwidth "spans" 12 channels (e.g., 36-48), in get_center_80mhz()
109 no_ir = 1; in verify_80mhz()
129 * In 160 MHz, the bandwidth "spans" 28 channels (e.g., 36-64), in get_center_160mhz()
179 no_ir = 1; in verify_160mhz()
199 * In 320 MHz, the bandwidth "spans" 60 channels (e.g., 65-125), in get_center_320mhz()
259 if (bw == BW40MINUS || (bw == BW40 && (((channel - 1) / 4) % 2))) { in verify_channel()
275 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel()
276 * result and use only the 80 MHz specific version. in verify_channel()
282 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel()
283 * result and use only the 160 MHz specific version. in verify_channel()
[all …]
/freebsd/contrib/wpa/src/ap/
H A Dieee802_11_ht.c99 if (hapd->iconf->secondary_channel == 1) in hostapd_eid_ht_operation()
102 if (hapd->iconf->secondary_channel == -1) in hostapd_eid_ht_operation()
115 - all STAs in the BSS are 20/40 MHz HT in 20/40 MHz BSS or
116 - all STAs in the BSS are 20 MHz HT in 20 MHz BSS
117 Set to 1 (HT non-member protection) if there may be non-HT STAs
120 however and at least one 20 MHz HT STA is associated
186 return 1; in is_40_allowed()
198 return 1; /* not within affected channel range */ in is_40_allowed()
200 wpa_printf(MSG_ERROR, "40 MHz affected channel range: [%d,%d] MHz", in is_40_allowed()
213 int is_ht40_allowed = 1; in hostapd_2040_coex_action()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos5433-tmu.dtsi22 atlas0_alert_1: atlas0-alert-1 {
56 /* Set maximum frequency as 1800MHz */
58 cooling-device = <&cpu4 1 2>, <&cpu5 1 2>,
59 <&cpu6 1 2>, <&cpu7 1 2>;
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
74 /* Set maximum frequency as 1500MHz */
80 /* Set maximum frequency as 1400MHz */
86 /* Set maximum frequencyas 1200MHz */
92 /* Set maximum frequency as 1000MHz */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm660.dtsi20 * 775MHz is only available on the highest speed bin
90 capacity-dmips-mhz = <1024>;
96 capacity-dmips-mhz = <1024>;
102 capacity-dmips-mhz = <1024>;
108 capacity-dmips-mhz = <1024>;
114 capacity-dmips-mhz = <640>;
120 capacity-dmips-mhz = <640>;
126 capacity-dmips-mhz = <640>;
132 capacity-dmips-mhz = <640>;
148 port@1 {
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dadi,adin.yaml42 A 25MHz reference and a free-running 125MHz.
44 the 125MHz clocks based on its internal state.
47 - 25mhz-reference
48 - 125mhz-free-running
52 description: Enable 25MHz reference clock output on CLK25_REF pin.
60 #address-cells = <1>;
74 #address-cells = <1>;
79 ethernet-phy@1 {
80 reg = <1>;
/freebsd/sys/contrib/dev/iwlwifi/mvm/
H A Drfi.c11 * DDR needs frequency in units of 16.666MHz, so provide FW with the
15 /* frequency 2667MHz */
20 /* frequency 2933MHz */
27 /* frequency 3200MHz */
32 /* frequency 3733MHz */
37 /* frequency 4000MHz */
42 /* frequency 4267MHz */
47 /* frequency 4400MHz */
52 /* frequency 5200MHz */
57 /* frequency 5600MHz */
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-gxm.dtsi46 capacity-dmips-mhz = <1024>;
49 cpu1: cpu@1 {
50 capacity-dmips-mhz = <1024>;
54 capacity-dmips-mhz = <1024>;
58 capacity-dmips-mhz = <1024>;
66 capacity-dmips-mhz = <1024>;
68 clocks = <&scpi_dvfs 1>;
77 capacity-dmips-mhz = <1024>;
79 clocks = <&scpi_dvfs 1>;
88 capacity-dmips-mhz = <1024>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3288-veyron-mickey.dts85 * After 1st level, throttle the CPU down to as low as 1.4 GHz
86 * and don't let the GPU go faster than 400 MHz.
97 cooling-device = <&gpu 1 1>;
106 * - 800 MHz (hot)
107 * - 800 MHz - 696 MHz (hotter)
108 * - 696 MHz - min (very hot)
111 * - 800 MHz appears to be a "sweet spot" for me. I can run
113 * - After 696 MHz we stop lowering voltage, so throttling
139 /* At very hot, don't let GPU go over 300 MHz */
180 /* After 1st level throttle the GPU down to as low as 400 MHz */
[all …]

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