/linux/Documentation/devicetree/bindings/phy/ |
H A D | apm-xgene-phy.txt | 1 * APM X-Gene 15Gbps Multi-purpose PHY nodes 3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each 9 - #phy-cells : Shall be 1 as it expects one argument for setting 11 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI). 23 data earlier than the nominal sampling point. 1 means 35 - apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of 48 0 = 1-2Gbps 49 1 = 2-4Gbps (1st tuple default) 50 2 = 4-8Gbps 51 3 = 8-15Gbps (2nd tuple default) [all …]
|
H A D | mediatek,hdmi-phy.yaml | 34 maxItems: 1 56 TX DRV bias current for < 1.65Gbps 64 TX DRV bias current for >= 1.65Gbps
|
/linux/drivers/scsi/mvsas/ |
H A D | mv_94xx.h | 72 /* ports 1-3 follow after this */ 79 /* ports 1-3 follow after this */ 84 /* ports 1-3 follow after this */ 91 /* phys 1-3 follow after this */ 94 /* phys 1-3 follow after this */ 117 VSR_PHY_MODE5 = 0x05 * 4, /* Phy Counter 1 */ 121 VSR_PHY_MODE9 = 0x09 * 4, /* Event Counter 1 */ 141 MVS_IRQ_COM_IN_I2O_IOP0 = (1 << 0), 142 MVS_IRQ_COM_IN_I2O_IOP1 = (1 << 1), 143 MVS_IRQ_COM_IN_I2O_IOP2 = (1 << 2), [all …]
|
/linux/drivers/gpu/drm/amd/display/dc/ |
H A D | dc_dp_types.h | 34 LANE_COUNT_ONE = 1, 50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane 51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane 52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane 53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane 54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane 55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane 56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane 57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane 58 LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane [all …]
|
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
H A D | smu11_driver_if_arcturus.h | 44 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1) 45 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1) 46 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1) 47 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1) 48 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1) 49 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 50 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1) 51 #define MAX_XGMI_LEVEL (NUM_XGMI_LEVELS - 1) 52 #define MAX_XGMI_PSTATE_LEVEL (NUM_XGMI_PSTATE_LEVELS - 1) 57 #define FEATURE_DPM_GFXCLK_BIT 1 [all …]
|
H A D | smu11_driver_if_sienna_cichlid.h | 53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1) 54 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1) 55 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1) 56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1) 57 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1) 58 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1) 59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1) 60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1) 61 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1) 62 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1) [all …]
|
/linux/drivers/net/ethernet/ezchip/ |
H A D | nps_enet.h | 19 #define NPS_ENET_ENABLE 1 57 #define TX_DONE_SHIFT 1 59 /* Gbps Eth MAC Configuration 0 register masks and shifts */ 63 #define CFG_0_TX_EN_SHIFT 1 93 /* Gbps Eth MAC Configuration 1 register masks and shifts */ 103 /* Gbps Eth MAC Configuration 2 register masks and shifts */ 119 /* Gbps Eth MAC Configuration 3 register masks and shifts */ 123 #define CFG_3_RX_CBFC_EN_SHIFT 1 151 #define PHASE_FIFO_CTL_INIT_SHIFT 1
|
/linux/drivers/gpu/drm/meson/ |
H A D | meson_dw_hdmi.c | 120 MESON_VENC_SOURCE_ENCI = 1, 291 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode() 295 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode() 299 /* 1.485Gbps */ in meson_hdmi_phy_setup_mode() 310 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode() 314 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode() 318 /* 1.485Gbps, and below */ in meson_hdmi_phy_setup_mode() 325 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode() 330 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode() 335 /* 1.485Gbps, and below */ in meson_hdmi_phy_setup_mode() [all …]
|
/linux/Documentation/devicetree/bindings/media/i2c/ |
H A D | maxim,max96717.yaml | 25 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the 27 MAX96717F only supports a fixed rate of 3Gbps in the forward direction. 50 maxItems: 1 68 minItems: 1 72 minItems: 1 78 port@1: 84 - port@1 107 #address-cells = <1>; 117 #address-cells = <1>; 123 data-lanes = <1 2 3 4>; [all …]
|
H A D | maxim,max96714.yaml | 23 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the 25 MAX96714F only supports a fixed rate of 3Gbps in the forward direction. 37 maxItems: 1 40 maxItems: 1 59 port@1: 71 minItems: 1 75 minItems: 1 79 maxItems: 1 85 - port@1 111 #address-cells = <1>; [all …]
|
H A D | sony,imx214.yaml | 7 title: Sony 1/3.06-Inch 13.13MP CMOS Digital Image Sensor 13 The Sony IMX214 is a 1/3.06-inch CMOS active pixel digital image sensor with 16 maximum throughput of 1.2Gbps/lane. 32 maxItems: 1 39 maxItems: 1 67 - const: 1 70 - const: 1 101 #address-cells = <1>; 104 camera-sensor@1a { 117 data-lanes = <1 2 3 4>;
|
/linux/fs/smb/client/ |
H A D | cifs_debug.c | 142 seq_printf(m, "\n\n\t\tChannel: %d DISABLED", i+1); in cifs_dump_channel() 151 i+1, server->conn_id, in cifs_dump_channel() 180 return "1Gbps"; in smb_speed_to_str() 182 return "2.5Gbps"; in smb_speed_to_str() 184 return "5Gbps"; in smb_speed_to_str() 186 return "10Gbps"; in smb_speed_to_str() 188 return "14Gbps"; in smb_speed_to_str() 190 return "20Gbps"; in smb_speed_to_str() 192 return "25Gbps"; in smb_speed_to_str() 194 return "40Gbps"; in smb_speed_to_str() [all …]
|
/linux/tools/testing/selftests/drivers/net/mlxsw/ |
H A D | qos_lib.sh | 5 local rate=$1; shift 6 local min=$1; shift 7 local what=$1; shift 14 return 1 19 local sw_in=$1; shift # Where the traffic ingresses the switch 20 local host_in=$1; shift # Where it ingresses another host 21 local counter=$1; shift # Counter to use for measurement 22 local what=$1; shift 29 # 1Gbps. That wouldn't saturate egress and MC would thus get through, 30 # seemingly winning bandwidth on account of UC. Demand at least 2Gbps [all …]
|
/linux/Documentation/networking/ |
H A D | dctcp.rst | 19 switches is 20 packets (30KB) at 1Gbps, and 65 packets (~100KB) at 10Gbps,
|
/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/ |
H A D | hclge_main.h | 26 #define HCLGE_VF_VPORT_START_NUM 1 88 #define HCLGE_RSS_TC_SIZE_0 1 151 #define HCLGE_CORE_RESET_BIT 1 166 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1 168 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1 178 (pci_resource_len((hdev)->pdev, HCLGE_MEM_BAR) >> 1) 188 #define HCLGE_SUPPORT_10G_BIT BIT(1) 247 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ 248 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ 249 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ [all …]
|
/linux/include/rdma/ |
H A D | opa_port_info.h | 15 #define OPA_PORT_PACKET_FORMAT_8B 1 /* Format 8B */ 21 #define OPA_PORT_LTP_CRC_MODE_14 1 /* 14-bit LTP CRC mode (optional) */ 28 #define OPA_LINKDOWN_REASON_RCV_ERROR_0 1 89 #define OPA_LINKINIT_REASON_LINKUP (1 << 4) 96 #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */ 97 #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */ 98 #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */ 105 #define OPA_CAP_MASK3_IsEthOnFabricSupported (1 << 13) 106 #define OPA_CAP_MASK3_IsSnoopSupported (1 << 7) 107 #define OPA_CAP_MASK3_IsAsyncSC2VLSupported (1 << 6) [all …]
|
/linux/drivers/gpu/drm/i915/display/ |
H A D | intel_cx0_phy.c | 31 #define INTEL_CX0_LANE1 BIT(1) 51 hweight8(lane_mask) != 1)) in lane_mask_to_lane() 66 * by display and lane 1 is owned by USB. in intel_cx0_get_owned_lane_mask() 376 intel_cx0_write(encoder, lane, PHY_C20_WR_DATA_L, data & 0xff, 1); in intel_c20_sram_write() 388 intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1); in intel_c20_sram_read() 470 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), in intel_cx0_phy_set_signal_levels() 476 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_TX(1), in intel_cx0_phy_set_signal_levels() 495 intel_cx0_rmw(encoder, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 1), in intel_cx0_phy_set_signal_levels() 511 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), in intel_cx0_phy_set_signal_levels() 529 .pll[1] = 0, [all …]
|
/linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
H A D | link_dp_capability.c | 133 return -1; in translate_dpcd_max_bpc() 139 case 0x80: // 1 lttpr repeater in dp_parse_lttpr_repeater_count() 140 return 1; in dp_parse_lttpr_repeater_count() 184 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation. in linkRateInKHzToLinkRateMultiplier() 187 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane in linkRateInKHzToLinkRateMultiplier() 190 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane in linkRateInKHzToLinkRateMultiplier() 193 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane in linkRateInKHzToLinkRateMultiplier() 196 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane in linkRateInKHzToLinkRateMultiplier() 199 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2)- 3.24 Gbps/Lane in linkRateInKHzToLinkRateMultiplier() 202 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane in linkRateInKHzToLinkRateMultiplier() [all …]
|
H A D | link_dp_dpia_bw.c | 71 #define BW_GRANULARITY_0 4 // 0.25 Gbps 72 #define BW_GRANULARITY_1 2 // 0.5 Gbps 73 #define BW_GRANULARITY_2 1 // 1 Gbps 89 case 1: in get_bw_granularity() 199 for (uint8_t i = 0; i < MAX_LINKS - 1; ++i) { in get_host_router_total_dp_tunnel_bw() 208 link_dpia_secondary = dc->links[i + 1]; in get_host_router_total_dp_tunnel_bw() 316 bw_support_dpia = (response >> 7) & 1; in link_dp_dpia_set_dptx_usb4_bw_alloc_support() 323 bw_support_cm = (response >> 7) & 1; in link_dp_dpia_set_dptx_usb4_bw_alloc_support() 390 * 1. Due to DP-Tx trying to allocate more than available i.e. it failed locally in dpia_handle_bw_alloc_response() 440 //1. Hot Plug in dpia_handle_usb4_bandwidth_allocation_for_link() [all …]
|
/linux/drivers/usb/host/ |
H A D | xhci-hub.c | 26 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */ 27 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */ 28 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */ 29 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */ 30 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */ 31 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */ 32 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */ 33 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */ 58 bos->bNumDeviceCaps = 1; in xhci_create_usb3x_bos_desc() 81 ssac = port_cap->psi_count + num_sym_ssa - 1; in xhci_create_usb3x_bos_desc() [all …]
|
/linux/Documentation/networking/device_drivers/ethernet/pensando/ |
H A D | ionic.rst | 25 $ lspci -d 1dd8: 26 b5:00.0 Ethernet controller: Device 1dd8:1002 27 b6:00.0 Ethernet controller: Device 1dd8:1002 36 ionic 0000:b5:00.0 enp181s0: Link up - 100 Gbps 39 ionic 0000:b6:00.0 enp182s0: Link up - 100 Gbps
|
/linux/Documentation/driver-api/ |
H A D | interconnect.rst | 131 echo 1 > get 133 # Set desired BW to 1GBps avg and 2GBps peak. 140 echo 1 > commit
|
/linux/arch/mips/cavium-octeon/executive/ |
H A D | cvmx-helper-board.c | 49 * port. A result of -1 means there isn't a MII capable PHY 61 * Returns MII PHY address and bus number or -1. 68 return -1; in cvmx_helper_board_get_mii_address() 73 /* Interface 0 is SPI4, interface 1 is RGMII */ in cvmx_helper_board_get_mii_address() 77 return -1; in cvmx_helper_board_get_mii_address() 85 * Port 0 is WAN connected to a PHY, Port 1 is GMII in cvmx_helper_board_get_mii_address() 90 else if (ipd_port == 1) in cvmx_helper_board_get_mii_address() 93 return -1; in cvmx_helper_board_get_mii_address() 101 return -1; in cvmx_helper_board_get_mii_address() 104 return -1; in cvmx_helper_board_get_mii_address() [all …]
|
/linux/Documentation/devicetree/bindings/ata/ |
H A D | apm-xgene.txt | 24 * "sata-phy" for the SATA 6.0Gbps PHY 34 #clock-cells = <1>; 39 phy2: phy@1f22a000 { 42 #phy-cells = <1>; 45 phy3: phy@1f23a000 { 48 #phy-cells = <1>; 51 sata2: sata@1a400000 { 65 sata3: sata@1a800000 {
|
/linux/drivers/platform/mellanox/ |
H A D | Kconfig | 90 L3 management switches. It has 48 x 1Gbps RJ45 + 4 x 100G QSFP28 91 ports in a compact 1RU form factor. The system also including a 92 serial port (RS-232 interface), an OOB port (1G/100M MDI interface) 96 System equipped with Nvidia®Spectrum-1 32x100GbE Ethernet switch.
|