Lines Matching +full:1 +full:gbps
34 #define INTEL_CX0_LANE1 BIT(1)
60 hweight8(lane_mask) != 1)) in lane_mask_to_lane()
75 * by display and lane 1 is owned by USB. in intel_cx0_get_owned_lane_mask()
384 intel_cx0_write(encoder, lane, PHY_C20_WR_DATA_L, data & 0xff, 1); in intel_c20_sram_write()
396 intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1); in intel_c20_sram_read()
478 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), in intel_cx0_phy_set_signal_levels()
484 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_TX(1), in intel_cx0_phy_set_signal_levels()
503 intel_cx0_rmw(encoder, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 1), in intel_cx0_phy_set_signal_levels()
519 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), in intel_cx0_phy_set_signal_levels()
537 .pll[1] = 0,
563 .pll[1] = 0,
589 .pll[1] = 0,
615 .pll[1] = 0,
641 .pll[1] = 0,
667 .pll[1] = 0,
693 .pll[1] = 0,
719 .pll[1] = 0,
745 .pll[1] = 0,
890 .clock = 1000000, /* 10 Gbps */
914 .clock = 1350000, /* 13.5 Gbps */
939 .clock = 2000000, /* 20 Gbps */
1116 .clock = 1350000, /* 13.5 Gbps */
1175 .pll[1] = 0,
1201 .pll[1] = 0,
1227 .pll[1] = 0,
1253 .pll[1] = 0,
1279 .pll[1] = 0,
1305 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1315 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00,
1325 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00,
1335 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00,
1345 .pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00,
1355 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1365 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1375 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00,
1385 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00,
1395 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1405 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00,
1415 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00,
1425 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1435 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00,
1445 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00,
1455 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00,
1465 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00,
1475 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00,
1485 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1495 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1505 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00,
1515 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00,
1525 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00,
1535 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00,
1545 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1555 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00,
1565 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00,
1575 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00,
1585 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1595 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1605 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00,
1615 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00,
1625 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00,
1635 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00,
1645 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1655 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1665 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1675 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00,
1685 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1695 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
2121 intel_cx0_rmw(encoder, lane, PHY_C10_VDR_CONTROL(1), in intel_c10pll_readout_hw_state()
2140 intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), in intel_c10_pll_program()
2157 intel_cx0_rmw(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1), in intel_c10_pll_program()
2167 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; in intel_c10pll_dump_hw_state()
2196 i, hw_state->pll[i], i + 1, hw_state->pll[i + 1], in intel_c10pll_dump_hw_state()
2266 mpll_div_multiplier = min_t(u8, div64_u64((vco_freq * 16 + (datarate >> 1)), in intel_c20_compute_hdmi_tmds_pll()
2280 pll_state->tx[1] = intel_c20_hdmi_tmds_tx_cgf_1(crtc_state); in intel_c20_compute_hdmi_tmds_pll()
2283 pll_state->cmn[1] = 0x0005; in intel_c20_compute_hdmi_tmds_pll()
2288 pll_state->mpllb[1] = (CAL_DAC_CODE(CAL_DAC_CODE_31) | in intel_c20_compute_hdmi_tmds_pll()
2393 tx_rate_mult = 1; in intel_c20pll_calc_port_clock()
2409 tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]); in intel_c20pll_calc_port_clock()
2419 ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div); in intel_c20pll_calc_port_clock()
2435 /* 1. Read current context selection */ in intel_c20pll_readout_hw_state()
2500 "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2501 hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); in intel_c20pll_dump_hw_state()
2503 "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2504 hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); in intel_c20pll_dump_hw_state()
2529 case 162000: /* 1.62 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2531 case 270000: /* 2.7 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2532 return 1; in intel_c20_get_dp_rate()
2533 case 540000: /* 5.4 Gbps DP 1.4 */ in intel_c20_get_dp_rate()
2535 case 810000: /* 8.1 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2537 case 216000: /* 2.16 Gbps eDP */ in intel_c20_get_dp_rate()
2539 case 243000: /* 2.43 Gbps eDP */ in intel_c20_get_dp_rate()
2541 case 324000: /* 3.24 Gbps eDP */ in intel_c20_get_dp_rate()
2543 case 432000: /* 4.32 Gbps eDP */ in intel_c20_get_dp_rate()
2545 case 1000000: /* 10 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2547 case 1350000: /* 13.5 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2549 case 2000000: /* 20 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2551 case 648000: /* 6.48 Gbps eDP*/ in intel_c20_get_dp_rate()
2553 case 675000: /* 6.75 Gbps eDP*/ in intel_c20_get_dp_rate()
2567 case 300000: /* 3 Gbps */ in intel_c20_get_hdmi_rate()
2568 case 600000: /* 6 Gbps */ in intel_c20_get_hdmi_rate()
2569 case 1200000: /* 12 Gbps */ in intel_c20_get_hdmi_rate()
2570 return 1; in intel_c20_get_hdmi_rate()
2571 case 800000: /* 8 Gbps */ in intel_c20_get_hdmi_rate()
2573 case 1000000: /* 10 Gbps */ in intel_c20_get_hdmi_rate()
2593 case 300000: /* 3 Gbps */ in is_hdmi_frl()
2594 case 600000: /* 6 Gbps */ in is_hdmi_frl()
2595 case 800000: /* 8 Gbps */ in is_hdmi_frl()
2596 case 1000000: /* 10 Gbps */ in is_hdmi_frl()
2597 case 1200000: /* 12 Gbps */ in is_hdmi_frl()
2618 return 1; in intel_get_c20_custom_width()
2632 /* 1. Read current context selection */ in intel_c20_pll_program()
2724 BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED); in intel_c20_pll_program()
2730 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; in intel_c10pll_calc_port_clock()
2749 tmpclk *= (hdmi_div ? 2 : 1); in intel_c10pll_calc_port_clock()
2894 ? XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1) in intel_cx0_phy_lane_reset()
2898 XELPDP_LANE_PHY_CURRENT_STATUS(1)) in intel_cx0_phy_lane_reset()
2955 PHY_C10_VDR_CONTROL(1), 0, in intel_cx0_program_phy_lane()
2964 if (dp_alt_mode && lane_count == 1) { in intel_cx0_program_phy_lane()
2965 disables &= ~REG_GENMASK8(1, 0); in intel_cx0_program_phy_lane()
2966 disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1); in intel_cx0_program_phy_lane()
2970 int tx = i % 2 + 1; in intel_cx0_program_phy_lane()
2984 PHY_C10_VDR_CONTROL(1), 0, in intel_cx0_program_phy_lane()
3024 * 1. Program PORT_CLOCK_CTL REGISTER to configure in __intel_cx0pll_enable()
3070 * LN<Lane for maxPCLK> to "1" to enable PLL. in __intel_cx0pll_enable()
3076 /* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */ in __intel_cx0pll_enable()
3172 * 1. Program PORT_CLOCK_CTL REGISTER to configure in intel_mtl_tbt_pll_enable()
3195 * 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL. in intel_mtl_tbt_pll_enable()
3200 /* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */ in intel_mtl_tbt_pll_enable()
3255 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 0, in intel_lnl_mac_transmit_lfps()
3259 int tx = i % 2 + 1; in intel_lnl_mac_transmit_lfps()
3293 /* 1. Change owned PHY lane power to Disable state. */ in intel_cx0pll_disable()
3354 * 1. Follow the Display Voltage Frequency Switching Sequence Before in intel_mtl_tbt_pll_disable()
3618 * 1. Follow the PLL Enable Sequence, using any valid frequency such as DP 1.62 GHz.