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/linux/include/soc/mscc/
H A Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
93 #define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18))
94 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18)
95 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
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H A Docelot_ana.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
15 #define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14))
16 #define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14)
17 #define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
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/linux/drivers/media/platform/ti/vpe/
H A Dvpe_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
51 #define VPE_INT0_LIST0_COMPLETE BIT(0)
52 #define VPE_INT0_LIST0_NOTIFY BIT(1)
53 #define VPE_INT0_LIST1_COMPLETE BIT(2)
54 #define VPE_INT0_LIST1_NOTIFY BIT(3)
55 #define VPE_INT0_LIST2_COMPLETE BIT(4)
56 #define VPE_INT0_LIST2_NOTIFY BIT(5)
57 #define VPE_INT0_LIST3_COMPLETE BIT(6)
58 #define VPE_INT0_LIST3_NOTIFY BIT(7)
59 #define VPE_INT0_LIST4_COMPLETE BIT(8)
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/linux/include/linux/
H A Dintel_pmt_features.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define PMT_CAP_TELEM BIT(0)
10 #define PMT_CAP_WATCHER BIT(1)
11 #define PMT_CAP_CRASHLOG BIT(2)
12 #define PMT_CAP_STREAMING BIT(3)
13 #define PMT_CAP_THRESHOLD BIT(4)
14 #define PMT_CAP_WINDOW BIT(5)
15 #define PMT_CAP_CONFIG BIT(6)
16 #define PMT_CAP_TRACING BIT(7)
17 #define PMT_CAP_INBAND BIT(8)
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/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
34 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
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/linux/drivers/gpu/drm/mcde/
H A Dmcde_dsi_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)
9 #define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE BIT(1)
10 #define DSI_MCTL_MAIN_DATA_CTL_VID_EN BIT(2)
11 #define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL BIT(3)
12 #define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL BIT(4)
13 #define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN BIT(5)
14 #define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN BIT(6)
15 #define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN BIT(7)
16 #define DSI_MCTL_MAIN_DATA_CTL_READ_EN BIT(8)
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/linux/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
6 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
171 #define QCA956X_MAC_CFG1_SOFT_RST BIT(31)
172 #define QCA956X_MAC_CFG1_RX_RST BIT(19)
173 #define QCA956X_MAC_CFG1_TX_RST BIT(18)
174 #define QCA956X_MAC_CFG1_LOOPBACK BIT(8)
175 #define QCA956X_MAC_CFG1_RX_EN BIT(2)
176 #define QCA956X_MAC_CFG1_TX_EN BIT(0)
179 #define QCA956X_MAC_CFG2_IF_1000 BIT(9)
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/linux/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/
H A Dsun8i_a83t_mipi_csi2_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2020-2022 Bootlin
14 #define SUN8I_A83T_MIPI_CSI2_CTRL_RESET_N BIT(31)
24 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_ECC_ERR_DBL BIT(28)
25 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_CKSM_ERR_VC3 BIT(27)
26 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_CKSM_ERR_VC2 BIT(26)
27 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_CKSM_ERR_VC1 BIT(25)
28 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_CKSM_ERR_VC0 BIT(24)
29 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_SEQ_ERR_DT3 BIT(23)
30 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_SEQ_ERR_DT2 BIT(22)
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/linux/drivers/platform/x86/intel/pmc/
H A Darl.c1 // SPDX-License-Identifier: GPL-2.0
63 {"AON2_OFF_STS", BIT(0)},
64 {"AON3_OFF_STS", BIT(1)},
65 {"AON4_OFF_STS", BIT(2)},
66 {"AON5_OFF_STS", BIT(3)},
67 {"AON1_OFF_STS", BIT(4)},
68 {"XTAL_LVM_OFF_STS", BIT(5)},
69 {"AON3_SPL_OFF_STS", BIT(9)},
70 {"DMI3FPW_0_PLL_OFF_STS", BIT(10)},
71 {"DMI3FPW_1_PLL_OFF_STS", BIT(11)},
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/linux/include/linux/amba/
H A Dpl080.h1 /* SPDX-License-Identifier: GPL-2.0-only */
38 #define PL080_CONFIG_M2_BE BIT(2)
39 #define PL080_CONFIG_M1_BE BIT(1)
40 #define PL080_CONFIG_ENABLE BIT(0)
72 #define PL080_LLI_LM_AHB2 BIT(0)
74 #define PL080_CONTROL_TC_IRQ_EN BIT(31)
77 #define PL080_CONTROL_PROT_CACHE BIT(30)
78 #define PL080_CONTROL_PROT_BUFF BIT(29)
79 #define PL080_CONTROL_PROT_SYS BIT(28)
80 #define PL080_CONTROL_DST_INCR BIT(27)
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/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_mipi_dsi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 /* Top-level registers */
24 #define MIPI_DSI_TOP_SW_RESET_DWC BIT(0)
25 #define MIPI_DSI_TOP_SW_RESET_INTR BIT(1)
26 #define MIPI_DSI_TOP_SW_RESET_DPI BIT(2)
27 #define MIPI_DSI_TOP_SW_RESET_TIMING BIT(3)
35 * [2] RW clock_freerun: Apply to auto-clock gate only. Default 0.
36 * 0=Default, use auto-clock gating to save power;
37 * 1=use free-run clock, disable auto-clock gating, for debug mode.
39 * have auto-clock gating. 1=Enable pixclk. Default 0.
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/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen4_ras.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #define ADF_GEN4_ERRSOU0_BIT BIT(0)
18 #define ADF_GEN4_ERRSOU1_HIAEUNCERRLOG_CPP0_BIT BIT(0)
19 #define ADF_GEN4_ERRSOU1_HICPPAGENTCMDPARERRLOG_BIT BIT(1)
20 #define ADF_GEN4_ERRSOU1_RIMEM_PARERR_STS_BIT BIT(2)
21 #define ADF_GEN4_ERRSOU1_TIMEM_PARERR_STS_BIT BIT(3)
22 #define ADF_GEN4_ERRSOU1_RIMISCSTS_BIT BIT(4)
51 * BIT(0) - BIT(3) - ri_iosf_pdata_rxq[0:3] parity error
52 * BIT(4) - ri_tlq_phdr parity error
53 * BIT(5) - ri_tlq_pdata parity error
[all …]
H A Dadf_gen4_pm.h1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
26 #define ADF_GEN4_PM_SOU BIT(18)
28 #define ADF_GEN4_PM_IDLE_INT_EN BIT(18)
29 #define ADF_GEN4_PM_THROTTLE_INT_EN BIT(19)
30 #define ADF_GEN4_PM_DRV_ACTIVE BIT(20)
31 #define ADF_GEN4_PM_INIT_STATE BIT(21)
35 #define ADF_GEN4_PM_THR_STS BIT(0)
36 #define ADF_GEN4_PM_IDLE_STS BIT(1)
37 #define ADF_GEN4_PM_FW_INT_STS BIT(2)
42 #define ADF_GEN4_PM_MSG_PENDING BIT(0)
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/linux/include/linux/mfd/syscon/
H A Dimx6q-iomuxc-gpr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
55 #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_MASK (0x3 << 18)
56 #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1_MUXED (0x0 << 18)
57 #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1 (0x1 << 18)
58 #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK (0x2 << 18)
59 #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_TX_BIT_CLK (0x3 << 18)
69 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK BIT(7)
71 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX BIT(7)
72 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK BIT(6)
74 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3 BIT(6)
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/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
46 #define MT_TX_FREE_PAIR BIT(31)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
56 #define MT_TXD1_TGID BIT(30)
58 #define MT_TXD1_AMSDU BIT(23)
60 #define MT_TXD1_HDR_PAD GENMASK(19, 18)
63 #define MT_TXD1_ETH_802_3 BIT(15)
64 #define MT_TXD1_VTA BIT(10)
67 #define MT_TXD2_FIX_RATE BIT(31)
68 #define MT_TXD2_FIXED_RATE BIT(30)
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/linux/drivers/net/phy/mscc/
H A Dmscc.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
28 #define MSCC_PHY_BYPASS_CONTROL 18
66 #define MII_VSC85XX_INT_MASK_MDINT BIT(15)
67 #define MII_VSC85XX_INT_MASK_LINK_CHG BIT(13)
68 #define MII_VSC85XX_INT_MASK_WOL BIT(6)
69 #define MII_VSC85XX_INT_MASK_EXT BIT(5)
89 #define MSCC_EXT_PAGE_CSR_CNTL_18 18
94 #define MSCC_PHY_CSR_CNTL_19_READ BIT(14)
95 #define MSCC_PHY_CSR_CNTL_19_CMD BIT(15)
101 #define PHY_MCB_S6G_WRITE BIT(31)
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H A Dmscc_macsec.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
17 #define CONTROL_IV0 BIT(5)
18 #define CONTROL_IV1 BIT(6)
19 #define CONTROL_IV2 BIT(7)
20 #define CONTROL_UPDATE_SEQ BIT(13)
21 #define CONTROL_IV_IN_SEQ BIT(14)
22 #define CONTROL_ENCRYPT_AUTH BIT(15)
23 #define CONTROL_KEY_IN_CTX BIT(16)
33 #define CONTROL_SEQ_MASK BIT(30)
34 #define CONTROL_CONTEXT_ID BIT(31)
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/linux/drivers/net/wireless/realtek/rtw89/
H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
9 #define B_AX_AUTOLOAD_SUS BIT(5)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(8)
18 #define B_AX_FEN_BB_GLB_RSTN BIT(1)
19 #define B_AX_FEN_BBRSTB BIT(0)
22 #define B_AX_SOP_ASWRM BIT(31)
23 #define B_AX_SOP_PWMM_DSWR BIT(29)
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/linux/drivers/mmc/host/
H A Drenesas_sdhi_internal_dmac.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-19 Renesas Electronics Corporation
6 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
7 * Copyright (C) 2018-19 Sang Engineering, Wolfram Sang
12 #include <linux/dma-mapping.h>
13 #include <linux/io-64-nonatomic-hi-lo.h>
39 #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "upstream" = for read commands */
40 #define DTRAN_MODE_BUS_WIDTH (BIT(5) | BIT(4))
41 #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address, 0 = Fixed */
44 #define DTRAN_CTRL_DM_START BIT(0)
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/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
27 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
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/linux/drivers/media/platform/ti/cal/
H A Dcal_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 * LDOs on the device are disabled if CSI-2 module is powered on
25 * Errata does not apply when CSI-2 module is powered off
30 * which is essentially CSI2 REG10 bit 6:
35 #define DRA72_CAL_PRE_ES2_LDO_DISABLE BIT(0)
103 #define CAL_HL_HWINFO_WCTX_MASK GENMASK(18, 13)
113 #define CAL_HL_SYSCONFIG_SOFTRESET_MASK BIT(0)
124 #define CAL_HL_IRQ_EOI_LINE_NUMBER_MASK BIT(0)
128 #define CAL_HL_IRQ_WDMA_END_MASK(m) BIT(m)
129 #define CAL_HL_IRQ_WDMA_START_MASK(m) BIT(m)
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/linux/arch/alpha/lib/
H A Dcsum_ipv6_magic.S1 /* SPDX-License-Identifier: GPL-2.0 */
26 extqh $18,1,$4 # e0 : byte swap len & proto while we wait
29 extbl $18,1,$5 # e0 :
31 extbl $18,2,$6 # e0 :
34 extbl $18,3,$18 # e0 :
55 or $4,$18,$18 # .. e1 :
62 or $18,$5,$18 # .. e1 : len complete
80 addq $20,$18,$20 # .. e1 :
81 cmpult $20,$18,$18 # e0 :
87 addq $18,$19,$18 # .. e1 :
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/linux/sound/soc/rockchip/
H A Drockchip_sai.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * ALSA SoC Audio Layer - Rockchip SAI Controller driver
12 #define SAI_XCR_START_SEL_MASK BIT(23)
13 #define SAI_XCR_START_SEL_CHAINED BIT(23)
15 #define SAI_XCR_EDGE_SHIFT_MASK BIT(22)
16 #define SAI_XCR_EDGE_SHIFT_1 BIT(22)
19 #define SAI_XCR_CSR(x) ((x - 1) << 20)
21 #define SAI_XCR_SJM_MASK BIT(19)
22 #define SAI_XCR_SJM_L BIT(19)
24 #define SAI_XCR_FBM_MASK BIT(18)
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/linux/arch/mips/include/asm/mach-ralink/
H A Drt3883.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
95 #define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
96 #define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8)
97 #define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7)
98 #define RT3883_SYSCFG1_PCI_66M_MODE BIT(6)
99 #define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2)
101 #define RT3883_CLKCFG1_PCIE_CLK_EN BIT(21)
102 #define RT3883_CLKCFG1_UPHY1_CLK_EN BIT(20)
103 #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
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/linux/arch/arm/mach-rpc/
H A Dirq.c1 // SPDX-License-Identifier: GPL-2.0
37 0,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
38 20,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
39 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
40 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
41 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
42 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
43 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
44 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
45 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
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