Lines Matching +full:18 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * ALSA SoC Audio Layer - Rockchip SAI Controller driver
12 #define SAI_XCR_START_SEL_MASK BIT(23)
13 #define SAI_XCR_START_SEL_CHAINED BIT(23)
15 #define SAI_XCR_EDGE_SHIFT_MASK BIT(22)
16 #define SAI_XCR_EDGE_SHIFT_1 BIT(22)
19 #define SAI_XCR_CSR(x) ((x - 1) << 20)
21 #define SAI_XCR_SJM_MASK BIT(19)
22 #define SAI_XCR_SJM_L BIT(19)
24 #define SAI_XCR_FBM_MASK BIT(18)
25 #define SAI_XCR_FBM_LSB BIT(18)
28 #define SAI_XCR_SNB(x) ((x - 1) << 11)
29 #define SAI_XCR_VDJ_MASK BIT(10)
30 #define SAI_XCR_VDJ_L BIT(10)
33 #define SAI_XCR_SBW(x) ((x - 1) << 5)
36 #define SAI_XCR_VDW(x) ((x - 1) << 0)
39 #define SAI_FSCR_EDGE_MASK BIT(24)
40 #define SAI_FSCR_EDGE_DUAL BIT(24)
43 #define SAI_FSCR_FPW(x) ((x - 1) << 12)
45 #define SAI_FSCR_FW(x) ((x - 1) << 0)
50 #define SAI_MCR_RX_MONO_SLOT_SEL(x) ((x - 1) << 2)
51 #define SAI_MCR_RX_MONO_MASK BIT(1)
52 #define SAI_MCR_RX_MONO_EN BIT(1)
54 #define SAI_MCR_TX_MONO_MASK BIT(0)
55 #define SAI_MCR_TX_MONO_EN BIT(0)
59 #define SAI_XFER_RX_IDLE BIT(8)
60 #define SAI_XFER_TX_IDLE BIT(7)
61 #define SAI_XFER_FS_IDLE BIT(6)
67 #define SAI_XFER_TX_AUTO_MASK BIT(6)
68 #define SAI_XFER_TX_AUTO_EN BIT(6)
70 #define SAI_XFER_RX_CNT_MASK BIT(5)
71 #define SAI_XFER_RX_CNT_EN BIT(5)
73 #define SAI_XFER_TX_CNT_MASK BIT(4)
74 #define SAI_XFER_TX_CNT_EN BIT(4)
76 #define SAI_XFER_RXS_MASK BIT(3)
77 #define SAI_XFER_RXS_EN BIT(3)
79 #define SAI_XFER_TXS_MASK BIT(2)
80 #define SAI_XFER_TXS_EN BIT(2)
82 #define SAI_XFER_FSS_MASK BIT(1)
83 #define SAI_XFER_FSS_EN BIT(1)
85 #define SAI_XFER_CLK_MASK BIT(0)
86 #define SAI_XFER_CLK_EN BIT(0)
90 #define SAI_CLR_FCR BIT(3) /* TODO: what is this? */
91 #define SAI_CLR_FSC BIT(2)
92 #define SAI_CLR_RXC BIT(1)
93 #define SAI_CLR_TXC BIT(0)
97 #define SAI_CKR_MDIV(x) ((x - 1) << 3)
98 #define SAI_CKR_MSS_MASK BIT(2)
99 #define SAI_CKR_MSS_SLAVE BIT(2)
101 #define SAI_CKR_CKP_MASK BIT(1)
102 #define SAI_CKR_CKP_INVERTED BIT(1)
104 #define SAI_CKR_FSP_MASK BIT(0)
105 #define SAI_CKR_FSP_INVERTED BIT(0)
109 #define SAI_DMACR_RDE_MASK BIT(24)
112 #define SAI_DMACR_RDL(x) ((x - 1) << 16)
114 #define SAI_DMACR_TDE_MASK BIT(8)
121 #define SAI_INTCR_FSLOSTC BIT(28)
122 #define SAI_INTCR_FSLOST_MASK BIT(27)
124 #define SAI_INTCR_FSERRC BIT(26)
125 #define SAI_INTCR_FSERR_MASK BIT(25)
127 #define SAI_INTCR_RXOIC BIT(18)
128 #define SAI_INTCR_RXOIE_MASK BIT(17)
130 #define SAI_INTCR_TXUIC BIT(2)
131 #define SAI_INTCR_TXUIE_MASK BIT(1)
136 #define SAI_INTSR_FSLOSTI_ACT BIT(19)
138 #define SAI_INTSR_FSERRI_ACT BIT(18)
140 #define SAI_INTSR_RXOI_ACT BIT(17)
142 #define SAI_INTSR_TXUI_ACT BIT(1)
155 * TX-ONLY: LEFT Direction Feature
156 * +------------------------------------------------+
158 * +------------------------------------------------+
163 * +------------------------------------------------+
165 * +------------------------------------------------+
171 #define SAI_FIFOLR_XFL3_SHIFT 18
172 #define SAI_FIFOLR_XFL3_MASK GENMASK(23, 18)
181 #define SAI_STATUS_RX_IDLE BIT(3)
182 #define SAI_STATUS_TX_IDLE BIT(2)
183 #define SAI_STATUS_FS_IDLE BIT(1)
195 * Support SAIn-Chained (e.g. SAI0-CLK-DATA + SAI3-DATA +...)
214 #define SAI_FS_TIMEOUT_EN_MASK BIT(0)