1f707079dSWolfram Sang // SPDX-License-Identifier: GPL-2.0 22a68ea78SSimon Horman /* 32a68ea78SSimon Horman * DMA support for Internal DMAC with SDHI SD/SDIO controller 42a68ea78SSimon Horman * 5f49bdcdeSWolfram Sang * Copyright (C) 2016-19 Renesas Electronics Corporation 62a68ea78SSimon Horman * Copyright (C) 2016-17 Horms Solutions, Simon Horman 7f49bdcdeSWolfram Sang * Copyright (C) 2018-19 Sang Engineering, Wolfram Sang 82a68ea78SSimon Horman */ 92a68ea78SSimon Horman 100cbc94daSWolfram Sang #include <linux/bitops.h> 112a68ea78SSimon Horman #include <linux/device.h> 122a68ea78SSimon Horman #include <linux/dma-mapping.h> 132a68ea78SSimon Horman #include <linux/io-64-nonatomic-hi-lo.h> 142a68ea78SSimon Horman #include <linux/mmc/host.h> 152a68ea78SSimon Horman #include <linux/mod_devicetable.h> 162a68ea78SSimon Horman #include <linux/module.h> 17c62da8a8SRob Herring #include <linux/of.h> 182a68ea78SSimon Horman #include <linux/pagemap.h> 19*70b46487SWolfram Sang #include <linux/platform_data/tmio.h> 204377aef8SWolfram Sang #include <linux/platform_device.h> 214377aef8SWolfram Sang #include <linux/pm_runtime.h> 222a68ea78SSimon Horman #include <linux/scatterlist.h> 23cd09780fSSimon Horman #include <linux/sys_soc.h> 242a68ea78SSimon Horman 252a68ea78SSimon Horman #include "renesas_sdhi.h" 262a68ea78SSimon Horman #include "tmio_mmc.h" 272a68ea78SSimon Horman 282a68ea78SSimon Horman #define DM_CM_DTRAN_MODE 0x820 292a68ea78SSimon Horman #define DM_CM_DTRAN_CTRL 0x828 302a68ea78SSimon Horman #define DM_CM_RST 0x830 312a68ea78SSimon Horman #define DM_CM_INFO1 0x840 322a68ea78SSimon Horman #define DM_CM_INFO1_MASK 0x848 332a68ea78SSimon Horman #define DM_CM_INFO2 0x850 342a68ea78SSimon Horman #define DM_CM_INFO2_MASK 0x858 352a68ea78SSimon Horman #define DM_DTRAN_ADDR 0x880 362a68ea78SSimon Horman 372a68ea78SSimon Horman /* DM_CM_DTRAN_MODE */ 382a68ea78SSimon Horman #define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */ 39c1ec8f86SSergei Shtylyov #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "upstream" = for read commands */ 40c1ec8f86SSergei Shtylyov #define DTRAN_MODE_BUS_WIDTH (BIT(5) | BIT(4)) 419706b472SChris Brandt #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address, 0 = Fixed */ 422a68ea78SSimon Horman 432a68ea78SSimon Horman /* DM_CM_DTRAN_CTRL */ 442a68ea78SSimon Horman #define DTRAN_CTRL_DM_START BIT(0) 452a68ea78SSimon Horman 462a68ea78SSimon Horman /* DM_CM_RST */ 472a68ea78SSimon Horman #define RST_DTRANRST1 BIT(9) 482a68ea78SSimon Horman #define RST_DTRANRST0 BIT(8) 499faf870eSSergei Shtylyov #define RST_RESERVED_BITS GENMASK_ULL(31, 0) 502a68ea78SSimon Horman 512a68ea78SSimon Horman /* DM_CM_INFO1 and DM_CM_INFO1_MASK */ 52d2332f88SSergei Shtylyov #define INFO1_MASK_CLEAR GENMASK_ULL(31, 0) 53ec9e80aeSWolfram Sang #define INFO1_DTRANEND1 BIT(20) 54ec9e80aeSWolfram Sang #define INFO1_DTRANEND1_OLD BIT(17) 552a68ea78SSimon Horman #define INFO1_DTRANEND0 BIT(16) 562a68ea78SSimon Horman 572a68ea78SSimon Horman /* DM_CM_INFO2 and DM_CM_INFO2_MASK */ 58d2332f88SSergei Shtylyov #define INFO2_MASK_CLEAR GENMASK_ULL(31, 0) 592a68ea78SSimon Horman #define INFO2_DTRANERR1 BIT(17) 602a68ea78SSimon Horman #define INFO2_DTRANERR0 BIT(16) 612a68ea78SSimon Horman 6269e7d76aSYoshihiro Shimoda enum renesas_sdhi_dma_cookie { 6369e7d76aSYoshihiro Shimoda COOKIE_UNMAPPED, 6469e7d76aSYoshihiro Shimoda COOKIE_PRE_MAPPED, 6569e7d76aSYoshihiro Shimoda COOKIE_MAPPED, 6669e7d76aSYoshihiro Shimoda }; 6769e7d76aSYoshihiro Shimoda 682a68ea78SSimon Horman /* 692a68ea78SSimon Horman * Specification of this driver: 702a68ea78SSimon Horman * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma 712a68ea78SSimon Horman * - Since this SDHI DMAC register set has 16 but 32-bit width, we 722a68ea78SSimon Horman * need a custom accessor. 732a68ea78SSimon Horman */ 742a68ea78SSimon Horman 750cbc94daSWolfram Sang static unsigned long global_flags; 760cbc94daSWolfram Sang /* 7707248afaSWolfram Sang * Workaround for avoiding to use RX DMAC by multiple channels. On R-Car M3-W 7807248afaSWolfram Sang * ES1.0, when multiple SDHI channels use RX DMAC simultaneously, sometimes 7907248afaSWolfram Sang * hundreds of data bytes are not stored into the system memory even if the 8007248afaSWolfram Sang * DMAC interrupt happened. So, this driver then uses one RX DMAC channel only. 810cbc94daSWolfram Sang */ 82bcfa7f15SWolfram Sang #define SDHI_INTERNAL_DMAC_RX_IN_USE 0 830cbc94daSWolfram Sang 842a68ea78SSimon Horman /* Definitions for sampling clocks */ 852a68ea78SSimon Horman static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = { 862a68ea78SSimon Horman { 872a68ea78SSimon Horman .clk_rate = 0, 882a68ea78SSimon Horman .tap = 0x00000300, 89c1a49782SWolfram Sang .tap_hs400_4tap = 0x00000100, 902a68ea78SSimon Horman }, 912a68ea78SSimon Horman }; 922a68ea78SSimon Horman 9371b7597cSYoshihiro Shimoda static const struct renesas_sdhi_of_data of_data_rza2 = { 949706b472SChris Brandt .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 959706b472SChris Brandt TMIO_MMC_HAVE_CBSY, 969706b472SChris Brandt .tmio_ocr_mask = MMC_VDD_32_33, 979706b472SChris Brandt .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 9887e985aeSWolfram Sang MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 999706b472SChris Brandt .bus_shift = 2, 1009706b472SChris Brandt .scc_offset = 0 - 0x1000, 1019706b472SChris Brandt .taps = rcar_gen3_scc_taps, 1029706b472SChris Brandt .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 1032a55c1eaSWolfram Sang /* DMAC can handle 32bit blk count but only 1 segment */ 1042a55c1eaSWolfram Sang .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 1059706b472SChris Brandt .max_segs = 1, 1069706b472SChris Brandt }; 1079706b472SChris Brandt 10871b7597cSYoshihiro Shimoda static const struct renesas_sdhi_of_data of_data_rcar_gen3 = { 1092ad1db05SMasahiro Yamada .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 1102ad1db05SMasahiro Yamada TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 1112a68ea78SSimon Horman .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 11287e985aeSWolfram Sang MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 113c7d9eccbSYoshihiro Shimoda .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, 1142a68ea78SSimon Horman .bus_shift = 2, 1152a68ea78SSimon Horman .scc_offset = 0x1000, 1162a68ea78SSimon Horman .taps = rcar_gen3_scc_taps, 1172a68ea78SSimon Horman .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 1182a55c1eaSWolfram Sang /* DMAC can handle 32bit blk count but only 1 segment */ 1192a55c1eaSWolfram Sang .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 1202a68ea78SSimon Horman .max_segs = 1, 121627151b4SWolfram Sang .sdhi_flags = SDHI_FLAG_NEED_CLKH_FALLBACK, 122627151b4SWolfram Sang }; 123627151b4SWolfram Sang 1246de9727aSWolfram Sang static const struct renesas_sdhi_of_data of_data_rcar_gen3_no_sdh_fallback = { 125627151b4SWolfram Sang .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 126627151b4SWolfram Sang TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 127627151b4SWolfram Sang .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 128627151b4SWolfram Sang MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 129627151b4SWolfram Sang .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, 130627151b4SWolfram Sang .bus_shift = 2, 131627151b4SWolfram Sang .scc_offset = 0x1000, 132627151b4SWolfram Sang .taps = rcar_gen3_scc_taps, 133627151b4SWolfram Sang .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 134627151b4SWolfram Sang /* DMAC can handle 32bit blk count but only 1 segment */ 135627151b4SWolfram Sang .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 136627151b4SWolfram Sang .max_segs = 1, 1372a68ea78SSimon Horman }; 1382a68ea78SSimon Horman 13971b7597cSYoshihiro Shimoda static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 14071b7597cSYoshihiro Shimoda { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15, 14171b7597cSYoshihiro Shimoda 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 }, 14271b7597cSYoshihiro Shimoda { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11, 14371b7597cSYoshihiro Shimoda 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 } 14471b7597cSYoshihiro Shimoda }; 14571b7597cSYoshihiro Shimoda 14671b7597cSYoshihiro Shimoda static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 14771b7597cSYoshihiro Shimoda { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16, 14871b7597cSYoshihiro Shimoda 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 }, 14971b7597cSYoshihiro Shimoda { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 15071b7597cSYoshihiro Shimoda 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 } 15171b7597cSYoshihiro Shimoda }; 15271b7597cSYoshihiro Shimoda 15371b7597cSYoshihiro Shimoda static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 15471b7597cSYoshihiro Shimoda { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15571b7597cSYoshihiro Shimoda 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 15671b7597cSYoshihiro Shimoda { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10, 15771b7597cSYoshihiro Shimoda 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 } 15871b7597cSYoshihiro Shimoda }; 15971b7597cSYoshihiro Shimoda 16071b7597cSYoshihiro Shimoda static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = { 16171b7597cSYoshihiro Shimoda .hs400_disabled = true, 16271b7597cSYoshihiro Shimoda .hs400_4taps = true, 16371b7597cSYoshihiro Shimoda }; 16471b7597cSYoshihiro Shimoda 165bcfa7f15SWolfram Sang static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_one_rx = { 166bcfa7f15SWolfram Sang .hs400_disabled = true, 167bcfa7f15SWolfram Sang .hs400_4taps = true, 168bcfa7f15SWolfram Sang .dma_one_rx_only = true, 169ec9e80aeSWolfram Sang .old_info1_layout = true, 170bcfa7f15SWolfram Sang }; 171bcfa7f15SWolfram Sang 17271b7597cSYoshihiro Shimoda static const struct renesas_sdhi_quirks sdhi_quirks_4tap = { 17371b7597cSYoshihiro Shimoda .hs400_4taps = true, 17471b7597cSYoshihiro Shimoda .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 17500e8c11cSTakeshi Saito .manual_tap_correction = true, 17671b7597cSYoshihiro Shimoda }; 17771b7597cSYoshihiro Shimoda 17871b7597cSYoshihiro Shimoda static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = { 17971b7597cSYoshihiro Shimoda .hs400_disabled = true, 18071b7597cSYoshihiro Shimoda }; 18171b7597cSYoshihiro Shimoda 182c0a43968SWolfram Sang static const struct renesas_sdhi_quirks sdhi_quirks_fixed_addr = { 183c0a43968SWolfram Sang .fixed_addr_mode = true, 184c0a43968SWolfram Sang }; 185c0a43968SWolfram Sang 18671b7597cSYoshihiro Shimoda static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = { 18771b7597cSYoshihiro Shimoda .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7), 18800e8c11cSTakeshi Saito .manual_tap_correction = true, 18971b7597cSYoshihiro Shimoda }; 19071b7597cSYoshihiro Shimoda 19171b7597cSYoshihiro Shimoda static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = { 19271b7597cSYoshihiro Shimoda .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 19300e8c11cSTakeshi Saito .manual_tap_correction = true, 19471b7597cSYoshihiro Shimoda }; 19571b7597cSYoshihiro Shimoda 19671b7597cSYoshihiro Shimoda static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = { 19771b7597cSYoshihiro Shimoda .hs400_4taps = true, 19871b7597cSYoshihiro Shimoda .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 19971b7597cSYoshihiro Shimoda .hs400_calib_table = r8a7796_es13_calib_table, 20000e8c11cSTakeshi Saito .manual_tap_correction = true, 20171b7597cSYoshihiro Shimoda }; 20271b7597cSYoshihiro Shimoda 20371b7597cSYoshihiro Shimoda static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = { 20471b7597cSYoshihiro Shimoda .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 20571b7597cSYoshihiro Shimoda .hs400_calib_table = r8a77965_calib_table, 20600e8c11cSTakeshi Saito .manual_tap_correction = true, 20771b7597cSYoshihiro Shimoda }; 20871b7597cSYoshihiro Shimoda 20971b7597cSYoshihiro Shimoda static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = { 21071b7597cSYoshihiro Shimoda .hs400_calib_table = r8a77990_calib_table, 21100e8c11cSTakeshi Saito .manual_tap_correction = true, 21271b7597cSYoshihiro Shimoda }; 21371b7597cSYoshihiro Shimoda 21435eea0deSLad Prabhakar static const struct renesas_sdhi_quirks sdhi_quirks_rzg2l = { 21508e03039SFabrizio Castro .fixed_addr_mode = true, 21608e03039SFabrizio Castro .hs400_disabled = true, 21708e03039SFabrizio Castro }; 21808e03039SFabrizio Castro 21971b7597cSYoshihiro Shimoda /* 22071b7597cSYoshihiro Shimoda * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now. 22171b7597cSYoshihiro Shimoda * So, we want to treat them equally and only have a match for ES1.2 to enforce 22271b7597cSYoshihiro Shimoda * this if there ever will be a way to distinguish ES1.2. 22371b7597cSYoshihiro Shimoda */ 22471b7597cSYoshihiro Shimoda static const struct soc_device_attribute sdhi_quirks_match[] = { 22571b7597cSYoshihiro Shimoda { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 22671b7597cSYoshihiro Shimoda { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap }, 227bcfa7f15SWolfram Sang { .soc_id = "r8a7796", .revision = "ES1.0", .data = &sdhi_quirks_4tap_nohs400_one_rx }, 228bcfa7f15SWolfram Sang { .soc_id = "r8a7796", .revision = "ES1.[12]", .data = &sdhi_quirks_4tap_nohs400 }, 22971b7597cSYoshihiro Shimoda { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 }, 230f504dee2SWolfram Sang { .soc_id = "r8a77980", .revision = "ES1.*", .data = &sdhi_quirks_nohs400 }, 2310ffd498dSGeert Uytterhoeven { /* Sentinel. */ } 23271b7597cSYoshihiro Shimoda }; 23371b7597cSYoshihiro Shimoda 23471b7597cSYoshihiro Shimoda static const struct renesas_sdhi_of_data_with_quirks of_r8a7795_compatible = { 23571b7597cSYoshihiro Shimoda .of_data = &of_data_rcar_gen3, 23671b7597cSYoshihiro Shimoda .quirks = &sdhi_quirks_bad_taps2367, 23771b7597cSYoshihiro Shimoda }; 23871b7597cSYoshihiro Shimoda 23971b7597cSYoshihiro Shimoda static const struct renesas_sdhi_of_data_with_quirks of_r8a77961_compatible = { 24071b7597cSYoshihiro Shimoda .of_data = &of_data_rcar_gen3, 24171b7597cSYoshihiro Shimoda .quirks = &sdhi_quirks_bad_taps1357, 24271b7597cSYoshihiro Shimoda }; 24371b7597cSYoshihiro Shimoda 24471b7597cSYoshihiro Shimoda static const struct renesas_sdhi_of_data_with_quirks of_r8a77965_compatible = { 24571b7597cSYoshihiro Shimoda .of_data = &of_data_rcar_gen3, 24671b7597cSYoshihiro Shimoda .quirks = &sdhi_quirks_r8a77965, 24771b7597cSYoshihiro Shimoda }; 24871b7597cSYoshihiro Shimoda 249627151b4SWolfram Sang static const struct renesas_sdhi_of_data_with_quirks of_r8a77970_compatible = { 2506de9727aSWolfram Sang .of_data = &of_data_rcar_gen3_no_sdh_fallback, 251fc1fdbd9SWolfram Sang .quirks = &sdhi_quirks_nohs400, 252627151b4SWolfram Sang }; 253627151b4SWolfram Sang 25471b7597cSYoshihiro Shimoda static const struct renesas_sdhi_of_data_with_quirks of_r8a77990_compatible = { 25571b7597cSYoshihiro Shimoda .of_data = &of_data_rcar_gen3, 25671b7597cSYoshihiro Shimoda .quirks = &sdhi_quirks_r8a77990, 25771b7597cSYoshihiro Shimoda }; 25871b7597cSYoshihiro Shimoda 25935eea0deSLad Prabhakar static const struct renesas_sdhi_of_data_with_quirks of_rzg2l_compatible = { 26008e03039SFabrizio Castro .of_data = &of_data_rcar_gen3, 26135eea0deSLad Prabhakar .quirks = &sdhi_quirks_rzg2l, 26208e03039SFabrizio Castro }; 26308e03039SFabrizio Castro 26471b7597cSYoshihiro Shimoda static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_compatible = { 26571b7597cSYoshihiro Shimoda .of_data = &of_data_rcar_gen3, 26671b7597cSYoshihiro Shimoda }; 26771b7597cSYoshihiro Shimoda 2686af8dd53SWolfram Sang static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_nohs400_compatible = { 2696af8dd53SWolfram Sang .of_data = &of_data_rcar_gen3, 2706af8dd53SWolfram Sang .quirks = &sdhi_quirks_nohs400, 2716af8dd53SWolfram Sang }; 2726af8dd53SWolfram Sang 273c0a43968SWolfram Sang static const struct renesas_sdhi_of_data_with_quirks of_rza2_compatible = { 274c0a43968SWolfram Sang .of_data = &of_data_rza2, 275c0a43968SWolfram Sang .quirks = &sdhi_quirks_fixed_addr, 276c0a43968SWolfram Sang }; 277c0a43968SWolfram Sang 2782a68ea78SSimon Horman static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = { 2799706b472SChris Brandt { .compatible = "renesas,sdhi-r7s9210", .data = &of_rza2_compatible, }, 28060ab43baSFabrizio Castro { .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, }, 28171b7597cSYoshihiro Shimoda { .compatible = "renesas,sdhi-r8a7795", .data = &of_r8a7795_compatible, }, 28271b7597cSYoshihiro Shimoda { .compatible = "renesas,sdhi-r8a77961", .data = &of_r8a77961_compatible, }, 28371b7597cSYoshihiro Shimoda { .compatible = "renesas,sdhi-r8a77965", .data = &of_r8a77965_compatible, }, 284627151b4SWolfram Sang { .compatible = "renesas,sdhi-r8a77970", .data = &of_r8a77970_compatible, }, 28571b7597cSYoshihiro Shimoda { .compatible = "renesas,sdhi-r8a77990", .data = &of_r8a77990_compatible, }, 2866af8dd53SWolfram Sang { .compatible = "renesas,sdhi-r8a77995", .data = &of_rcar_gen3_nohs400_compatible, }, 28735eea0deSLad Prabhakar { .compatible = "renesas,sdhi-r9a09g011", .data = &of_rzg2l_compatible, }, 28835eea0deSLad Prabhakar { .compatible = "renesas,rzg2l-sdhi", .data = &of_rzg2l_compatible, }, 289d6dc425aSSimon Horman { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, }, 2907b651cc6SWolfram Sang { .compatible = "renesas,rcar-gen4-sdhi", .data = &of_rcar_gen3_compatible, }, 2912a68ea78SSimon Horman {}, 2922a68ea78SSimon Horman }; 2932a68ea78SSimon Horman MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match); 2942a68ea78SSimon Horman 2952a68ea78SSimon Horman static void 2962a68ea78SSimon Horman renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable) 2972a68ea78SSimon Horman { 298058db286SMasahiro Yamada struct renesas_sdhi *priv = host_to_priv(host); 299c330601cSWolfram Sang u32 dma_irqs = INFO1_DTRANEND0 | 30048c917faSWolfram Sang (sdhi_has_quirk(priv, old_info1_layout) ? 301c330601cSWolfram Sang INFO1_DTRANEND1_OLD : INFO1_DTRANEND1); 302058db286SMasahiro Yamada 3032a68ea78SSimon Horman if (!host->chan_tx || !host->chan_rx) 3042a68ea78SSimon Horman return; 3052a68ea78SSimon Horman 306c330601cSWolfram Sang writel(enable ? ~dma_irqs : INFO1_MASK_CLEAR, host->ctl + DM_CM_INFO1_MASK); 3072a68ea78SSimon Horman 308058db286SMasahiro Yamada if (priv->dma_priv.enable) 309058db286SMasahiro Yamada priv->dma_priv.enable(host, enable); 3102a68ea78SSimon Horman } 3112a68ea78SSimon Horman 3122a68ea78SSimon Horman static void 313ed9ab884SWolfram Sang renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) 314ed9ab884SWolfram Sang { 3152a68ea78SSimon Horman u64 val = RST_DTRANRST1 | RST_DTRANRST0; 3162a68ea78SSimon Horman 3172a68ea78SSimon Horman renesas_sdhi_internal_dmac_enable_dma(host, false); 3182a68ea78SSimon Horman 319a8687078SWolfram Sang writel(RST_RESERVED_BITS & ~val, host->ctl + DM_CM_RST); 320a8687078SWolfram Sang writel(RST_RESERVED_BITS | val, host->ctl + DM_CM_RST); 3212a68ea78SSimon Horman 3220cbc94daSWolfram Sang clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 3230cbc94daSWolfram Sang 3242a68ea78SSimon Horman renesas_sdhi_internal_dmac_enable_dma(host, true); 3252a68ea78SSimon Horman } 3262a68ea78SSimon Horman 327c330601cSWolfram Sang static bool renesas_sdhi_internal_dmac_dma_irq(struct tmio_mmc_host *host) 328c330601cSWolfram Sang { 329c330601cSWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 330c330601cSWolfram Sang struct renesas_sdhi_dma *dma_priv = &priv->dma_priv; 331c330601cSWolfram Sang 332c330601cSWolfram Sang u32 dma_irqs = INFO1_DTRANEND0 | 33348c917faSWolfram Sang (sdhi_has_quirk(priv, old_info1_layout) ? 334c330601cSWolfram Sang INFO1_DTRANEND1_OLD : INFO1_DTRANEND1); 335c330601cSWolfram Sang u32 status = readl(host->ctl + DM_CM_INFO1); 336c330601cSWolfram Sang 337c330601cSWolfram Sang if (status & dma_irqs) { 338c330601cSWolfram Sang writel(status ^ dma_irqs, host->ctl + DM_CM_INFO1); 339c330601cSWolfram Sang set_bit(SDHI_DMA_END_FLAG_DMA, &dma_priv->end_flags); 340c330601cSWolfram Sang if (test_bit(SDHI_DMA_END_FLAG_ACCESS, &dma_priv->end_flags)) 34185683fb3SAllen Pais queue_work(system_bh_wq, &dma_priv->dma_complete); 342c330601cSWolfram Sang } 343c330601cSWolfram Sang 344c330601cSWolfram Sang return status & dma_irqs; 345c330601cSWolfram Sang } 346c330601cSWolfram Sang 3472a68ea78SSimon Horman static void 348ed9ab884SWolfram Sang renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) 349ed9ab884SWolfram Sang { 35090d95106SMasahiro Yamada struct renesas_sdhi *priv = host_to_priv(host); 351c330601cSWolfram Sang struct renesas_sdhi_dma *dma_priv = &priv->dma_priv; 35290d95106SMasahiro Yamada 353c330601cSWolfram Sang set_bit(SDHI_DMA_END_FLAG_ACCESS, &dma_priv->end_flags); 354c330601cSWolfram Sang if (test_bit(SDHI_DMA_END_FLAG_DMA, &dma_priv->end_flags) || 355c330601cSWolfram Sang host->data->error) 35685683fb3SAllen Pais queue_work(system_bh_wq, &dma_priv->dma_complete); 3572a68ea78SSimon Horman } 3582a68ea78SSimon Horman 35969e7d76aSYoshihiro Shimoda /* 36008860404SLad Prabhakar * renesas_sdhi_internal_dmac_map() will be called with two different 36169e7d76aSYoshihiro Shimoda * sg pointers in two mmc_data by .pre_req(), but tmio host can have a single 36269e7d76aSYoshihiro Shimoda * sg_ptr only. So, renesas_sdhi_internal_dmac_{un}map() should use a sg 36369e7d76aSYoshihiro Shimoda * pointer in a mmc_data instead of host->sg_ptr. 36469e7d76aSYoshihiro Shimoda */ 36569e7d76aSYoshihiro Shimoda static void 36669e7d76aSYoshihiro Shimoda renesas_sdhi_internal_dmac_unmap(struct tmio_mmc_host *host, 36769e7d76aSYoshihiro Shimoda struct mmc_data *data, 36869e7d76aSYoshihiro Shimoda enum renesas_sdhi_dma_cookie cookie) 36969e7d76aSYoshihiro Shimoda { 37069e7d76aSYoshihiro Shimoda bool unmap = cookie == COOKIE_UNMAPPED ? (data->host_cookie != cookie) : 37169e7d76aSYoshihiro Shimoda (data->host_cookie == cookie); 37269e7d76aSYoshihiro Shimoda 37369e7d76aSYoshihiro Shimoda if (unmap) { 37469e7d76aSYoshihiro Shimoda dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, 37569e7d76aSYoshihiro Shimoda mmc_get_dma_dir(data)); 37669e7d76aSYoshihiro Shimoda data->host_cookie = COOKIE_UNMAPPED; 37769e7d76aSYoshihiro Shimoda } 37869e7d76aSYoshihiro Shimoda } 37969e7d76aSYoshihiro Shimoda 38069e7d76aSYoshihiro Shimoda static bool 38169e7d76aSYoshihiro Shimoda renesas_sdhi_internal_dmac_map(struct tmio_mmc_host *host, 38269e7d76aSYoshihiro Shimoda struct mmc_data *data, 38369e7d76aSYoshihiro Shimoda enum renesas_sdhi_dma_cookie cookie) 38469e7d76aSYoshihiro Shimoda { 38569e7d76aSYoshihiro Shimoda if (data->host_cookie == COOKIE_PRE_MAPPED) 38669e7d76aSYoshihiro Shimoda return true; 38769e7d76aSYoshihiro Shimoda 38869e7d76aSYoshihiro Shimoda if (!dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, 38969e7d76aSYoshihiro Shimoda mmc_get_dma_dir(data))) 39069e7d76aSYoshihiro Shimoda return false; 39169e7d76aSYoshihiro Shimoda 39269e7d76aSYoshihiro Shimoda data->host_cookie = cookie; 39369e7d76aSYoshihiro Shimoda 39408860404SLad Prabhakar /* This DMAC needs buffers to be 128-byte aligned */ 39569e7d76aSYoshihiro Shimoda if (!IS_ALIGNED(sg_dma_address(data->sg), 128)) { 39669e7d76aSYoshihiro Shimoda renesas_sdhi_internal_dmac_unmap(host, data, cookie); 39769e7d76aSYoshihiro Shimoda return false; 39869e7d76aSYoshihiro Shimoda } 39969e7d76aSYoshihiro Shimoda 40069e7d76aSYoshihiro Shimoda return true; 40169e7d76aSYoshihiro Shimoda } 40269e7d76aSYoshihiro Shimoda 4032a68ea78SSimon Horman static void 4042a68ea78SSimon Horman renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host, 4052a68ea78SSimon Horman struct mmc_data *data) 4062a68ea78SSimon Horman { 407c0a43968SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 4082a68ea78SSimon Horman struct scatterlist *sg = host->sg_ptr; 4099706b472SChris Brandt u32 dtran_mode = DTRAN_MODE_BUS_WIDTH; 4109706b472SChris Brandt 41148c917faSWolfram Sang if (!sdhi_has_quirk(priv, fixed_addr_mode)) 4129706b472SChris Brandt dtran_mode |= DTRAN_MODE_ADDR_MODE; 4132a68ea78SSimon Horman 41469e7d76aSYoshihiro Shimoda if (!renesas_sdhi_internal_dmac_map(host, data, COOKIE_MAPPED)) 41548e1dc10SYoshihiro Shimoda goto force_pio; 4162a68ea78SSimon Horman 4172a68ea78SSimon Horman if (data->flags & MMC_DATA_READ) { 4182a68ea78SSimon Horman dtran_mode |= DTRAN_MODE_CH_NUM_CH1; 41948c917faSWolfram Sang if (sdhi_has_quirk(priv, dma_one_rx_only) && 4200cbc94daSWolfram Sang test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags)) 421fe6e0494SYoshihiro Shimoda goto force_pio_with_unmap; 4222a68ea78SSimon Horman } else { 4232a68ea78SSimon Horman dtran_mode |= DTRAN_MODE_CH_NUM_CH0; 4242a68ea78SSimon Horman } 4252a68ea78SSimon Horman 426c330601cSWolfram Sang priv->dma_priv.end_flags = 0; 4272a68ea78SSimon Horman renesas_sdhi_internal_dmac_enable_dma(host, true); 4282a68ea78SSimon Horman 4292a68ea78SSimon Horman /* set dma parameters */ 430a8687078SWolfram Sang writel(dtran_mode, host->ctl + DM_CM_DTRAN_MODE); 431a8687078SWolfram Sang writel(sg_dma_address(sg), host->ctl + DM_DTRAN_ADDR); 43248e1dc10SYoshihiro Shimoda 433d3dd5db0SMasahiro Yamada host->dma_on = true; 434d3dd5db0SMasahiro Yamada 43548e1dc10SYoshihiro Shimoda return; 43648e1dc10SYoshihiro Shimoda 437fe6e0494SYoshihiro Shimoda force_pio_with_unmap: 43869e7d76aSYoshihiro Shimoda renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED); 439fe6e0494SYoshihiro Shimoda 44048e1dc10SYoshihiro Shimoda force_pio: 44148e1dc10SYoshihiro Shimoda renesas_sdhi_internal_dmac_enable_dma(host, false); 4422a68ea78SSimon Horman } 4432a68ea78SSimon Horman 44485683fb3SAllen Pais static void renesas_sdhi_internal_dmac_issue_work_fn(struct work_struct *work) 4452a68ea78SSimon Horman { 44685683fb3SAllen Pais struct tmio_mmc_host *host = from_work(host, work, dma_issue); 447c330601cSWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 4482a68ea78SSimon Horman 4492a68ea78SSimon Horman tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 4502a68ea78SSimon Horman 451c330601cSWolfram Sang if (!host->cmd->error) { 4522a68ea78SSimon Horman /* start the DMAC */ 453a8687078SWolfram Sang writel(DTRAN_CTRL_DM_START, host->ctl + DM_CM_DTRAN_CTRL); 454c330601cSWolfram Sang } else { 455c330601cSWolfram Sang /* on CMD errors, simulate DMA end immediately */ 456c330601cSWolfram Sang set_bit(SDHI_DMA_END_FLAG_DMA, &priv->dma_priv.end_flags); 457c330601cSWolfram Sang if (test_bit(SDHI_DMA_END_FLAG_ACCESS, &priv->dma_priv.end_flags)) 45885683fb3SAllen Pais queue_work(system_bh_wq, &priv->dma_priv.dma_complete); 459c330601cSWolfram Sang } 4602a68ea78SSimon Horman } 4612a68ea78SSimon Horman 4622b26e34eSYoshihiro Shimoda static bool renesas_sdhi_internal_dmac_complete(struct tmio_mmc_host *host) 4632a68ea78SSimon Horman { 4642a68ea78SSimon Horman enum dma_data_direction dir; 4652a68ea78SSimon Horman 46658a91d96SYoshihiro Shimoda if (!host->dma_on) 46758a91d96SYoshihiro Shimoda return false; 46858a91d96SYoshihiro Shimoda 4692a68ea78SSimon Horman if (!host->data) 4702b26e34eSYoshihiro Shimoda return false; 4712a68ea78SSimon Horman 4722a68ea78SSimon Horman if (host->data->flags & MMC_DATA_READ) 4732a68ea78SSimon Horman dir = DMA_FROM_DEVICE; 4742a68ea78SSimon Horman else 4752a68ea78SSimon Horman dir = DMA_TO_DEVICE; 4762a68ea78SSimon Horman 4772a68ea78SSimon Horman renesas_sdhi_internal_dmac_enable_dma(host, false); 47869e7d76aSYoshihiro Shimoda renesas_sdhi_internal_dmac_unmap(host, host->data, COOKIE_MAPPED); 4792a68ea78SSimon Horman 4800cbc94daSWolfram Sang if (dir == DMA_FROM_DEVICE) 4810cbc94daSWolfram Sang clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 4820cbc94daSWolfram Sang 48358a91d96SYoshihiro Shimoda host->dma_on = false; 48458a91d96SYoshihiro Shimoda 4852b26e34eSYoshihiro Shimoda return true; 4862b26e34eSYoshihiro Shimoda } 4872b26e34eSYoshihiro Shimoda 48885683fb3SAllen Pais static void renesas_sdhi_internal_dmac_complete_work_fn(struct work_struct *work) 4892b26e34eSYoshihiro Shimoda { 49085683fb3SAllen Pais struct renesas_sdhi_dma *dma_priv = from_work(dma_priv, work, dma_complete); 49185683fb3SAllen Pais struct renesas_sdhi *priv = container_of(dma_priv, typeof(*priv), dma_priv); 49285683fb3SAllen Pais struct tmio_mmc_host *host = priv->host; 4932b26e34eSYoshihiro Shimoda 4942b26e34eSYoshihiro Shimoda spin_lock_irq(&host->lock); 4952b26e34eSYoshihiro Shimoda if (!renesas_sdhi_internal_dmac_complete(host)) 4962b26e34eSYoshihiro Shimoda goto out; 4972b26e34eSYoshihiro Shimoda 4982a68ea78SSimon Horman tmio_mmc_do_data_irq(host); 4992a68ea78SSimon Horman out: 5002a68ea78SSimon Horman spin_unlock_irq(&host->lock); 5012a68ea78SSimon Horman } 5022a68ea78SSimon Horman 50358a91d96SYoshihiro Shimoda static void renesas_sdhi_internal_dmac_end_dma(struct tmio_mmc_host *host) 50458a91d96SYoshihiro Shimoda { 50558a91d96SYoshihiro Shimoda if (host->data) 50658a91d96SYoshihiro Shimoda renesas_sdhi_internal_dmac_complete(host); 50758a91d96SYoshihiro Shimoda } 50858a91d96SYoshihiro Shimoda 50969e7d76aSYoshihiro Shimoda static void renesas_sdhi_internal_dmac_post_req(struct mmc_host *mmc, 51069e7d76aSYoshihiro Shimoda struct mmc_request *mrq, 51169e7d76aSYoshihiro Shimoda int err) 51269e7d76aSYoshihiro Shimoda { 51369e7d76aSYoshihiro Shimoda struct tmio_mmc_host *host = mmc_priv(mmc); 51469e7d76aSYoshihiro Shimoda struct mmc_data *data = mrq->data; 51569e7d76aSYoshihiro Shimoda 51669e7d76aSYoshihiro Shimoda if (!data) 51769e7d76aSYoshihiro Shimoda return; 51869e7d76aSYoshihiro Shimoda 51969e7d76aSYoshihiro Shimoda renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED); 52069e7d76aSYoshihiro Shimoda } 52169e7d76aSYoshihiro Shimoda 52269e7d76aSYoshihiro Shimoda static void renesas_sdhi_internal_dmac_pre_req(struct mmc_host *mmc, 52369e7d76aSYoshihiro Shimoda struct mmc_request *mrq) 52469e7d76aSYoshihiro Shimoda { 52569e7d76aSYoshihiro Shimoda struct tmio_mmc_host *host = mmc_priv(mmc); 52669e7d76aSYoshihiro Shimoda struct mmc_data *data = mrq->data; 52769e7d76aSYoshihiro Shimoda 52869e7d76aSYoshihiro Shimoda if (!data) 52969e7d76aSYoshihiro Shimoda return; 53069e7d76aSYoshihiro Shimoda 53169e7d76aSYoshihiro Shimoda data->host_cookie = COOKIE_UNMAPPED; 53269e7d76aSYoshihiro Shimoda renesas_sdhi_internal_dmac_map(host, data, COOKIE_PRE_MAPPED); 53369e7d76aSYoshihiro Shimoda } 53469e7d76aSYoshihiro Shimoda 5352a68ea78SSimon Horman static void 5362a68ea78SSimon Horman renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host, 5372a68ea78SSimon Horman struct tmio_mmc_data *pdata) 5382a68ea78SSimon Horman { 53990d95106SMasahiro Yamada struct renesas_sdhi *priv = host_to_priv(host); 54090d95106SMasahiro Yamada 541c330601cSWolfram Sang /* Disable DMAC interrupts initially */ 542a8687078SWolfram Sang writel(INFO1_MASK_CLEAR, host->ctl + DM_CM_INFO1_MASK); 543a8687078SWolfram Sang writel(INFO2_MASK_CLEAR, host->ctl + DM_CM_INFO2_MASK); 544c330601cSWolfram Sang writel(0, host->ctl + DM_CM_INFO1); 545c330601cSWolfram Sang writel(0, host->ctl + DM_CM_INFO2); 546d2332f88SSergei Shtylyov 5472a68ea78SSimon Horman /* Each value is set to non-zero to assume "enabling" each DMA */ 5482a68ea78SSimon Horman host->chan_rx = host->chan_tx = (void *)0xdeadbeaf; 5492a68ea78SSimon Horman 55085683fb3SAllen Pais INIT_WORK(&priv->dma_priv.dma_complete, 55185683fb3SAllen Pais renesas_sdhi_internal_dmac_complete_work_fn); 55285683fb3SAllen Pais INIT_WORK(&host->dma_issue, 55385683fb3SAllen Pais renesas_sdhi_internal_dmac_issue_work_fn); 55469e7d76aSYoshihiro Shimoda 55569e7d76aSYoshihiro Shimoda /* Add pre_req and post_req */ 55669e7d76aSYoshihiro Shimoda host->ops.pre_req = renesas_sdhi_internal_dmac_pre_req; 55769e7d76aSYoshihiro Shimoda host->ops.post_req = renesas_sdhi_internal_dmac_post_req; 5582a68ea78SSimon Horman } 5592a68ea78SSimon Horman 5602a68ea78SSimon Horman static void 5612a68ea78SSimon Horman renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host) 5622a68ea78SSimon Horman { 5632a68ea78SSimon Horman /* Each value is set to zero to assume "disabling" each DMA */ 5642a68ea78SSimon Horman host->chan_rx = host->chan_tx = NULL; 5652a68ea78SSimon Horman } 5662a68ea78SSimon Horman 56710154068SJulia Lawall static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = { 5682a68ea78SSimon Horman .start = renesas_sdhi_internal_dmac_start_dma, 5692a68ea78SSimon Horman .enable = renesas_sdhi_internal_dmac_enable_dma, 5702a68ea78SSimon Horman .request = renesas_sdhi_internal_dmac_request_dma, 5712a68ea78SSimon Horman .release = renesas_sdhi_internal_dmac_release_dma, 5722a68ea78SSimon Horman .abort = renesas_sdhi_internal_dmac_abort_dma, 5732a68ea78SSimon Horman .dataend = renesas_sdhi_internal_dmac_dataend_dma, 57458a91d96SYoshihiro Shimoda .end = renesas_sdhi_internal_dmac_end_dma, 575c330601cSWolfram Sang .dma_irq = renesas_sdhi_internal_dmac_dma_irq, 5762a68ea78SSimon Horman }; 5772a68ea78SSimon Horman 5782a68ea78SSimon Horman static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev) 5792a68ea78SSimon Horman { 58071b7597cSYoshihiro Shimoda const struct soc_device_attribute *attr; 58171b7597cSYoshihiro Shimoda const struct renesas_sdhi_of_data_with_quirks *of_data_quirks; 58271b7597cSYoshihiro Shimoda const struct renesas_sdhi_quirks *quirks; 58354541815SNiklas Söderlund struct device *dev = &pdev->dev; 5840cbc94daSWolfram Sang 58571b7597cSYoshihiro Shimoda of_data_quirks = of_device_get_match_data(&pdev->dev); 58671b7597cSYoshihiro Shimoda quirks = of_data_quirks->quirks; 58771b7597cSYoshihiro Shimoda 58871b7597cSYoshihiro Shimoda attr = soc_device_match(sdhi_quirks_match); 58971b7597cSYoshihiro Shimoda if (attr) 59071b7597cSYoshihiro Shimoda quirks = attr->data; 5910cbc94daSWolfram Sang 59254541815SNiklas Söderlund /* value is max of SD_SECCNT. Confirmed by HW engineers */ 59354541815SNiklas Söderlund dma_set_max_seg_size(dev, 0xffffffff); 59454541815SNiklas Söderlund 59571b7597cSYoshihiro Shimoda return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops, 59671b7597cSYoshihiro Shimoda of_data_quirks->of_data, quirks); 5972a68ea78SSimon Horman } 5982a68ea78SSimon Horman 5992a68ea78SSimon Horman static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = { 6002a68ea78SSimon Horman SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 6012a68ea78SSimon Horman pm_runtime_force_resume) 6022a68ea78SSimon Horman SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend, 6032a68ea78SSimon Horman tmio_mmc_host_runtime_resume, 6042a68ea78SSimon Horman NULL) 6052a68ea78SSimon Horman }; 6062a68ea78SSimon Horman 6072a68ea78SSimon Horman static struct platform_driver renesas_internal_dmac_sdhi_driver = { 6082a68ea78SSimon Horman .driver = { 6092a68ea78SSimon Horman .name = "renesas_sdhi_internal_dmac", 6107320915cSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 6112a68ea78SSimon Horman .pm = &renesas_sdhi_internal_dmac_dev_pm_ops, 6122a68ea78SSimon Horman .of_match_table = renesas_sdhi_internal_dmac_of_match, 6132a68ea78SSimon Horman }, 6142a68ea78SSimon Horman .probe = renesas_sdhi_internal_dmac_probe, 61580c602b1SYangtao Li .remove_new = renesas_sdhi_remove, 6162a68ea78SSimon Horman }; 6172a68ea78SSimon Horman 6182a68ea78SSimon Horman module_platform_driver(renesas_internal_dmac_sdhi_driver); 6192a68ea78SSimon Horman 6202a68ea78SSimon Horman MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC"); 6212a68ea78SSimon Horman MODULE_AUTHOR("Yoshihiro Shimoda"); 6222a68ea78SSimon Horman MODULE_LICENSE("GPL v2"); 623