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/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am625.dtsi49 d-cache-sets = <128>;
66 d-cache-sets = <128>;
83 d-cache-sets = <128>;
100 d-cache-sets = <128>;
114 opp-hz = /bits/ 64 <200000000>;
120 opp-hz = /bits/ 64 <400000000>;
126 opp-hz = /bits/ 64 <600000000>;
132 opp-hz = /bits/ 64 <800000000>;
138 opp-hz = /bits/ 64 <1000000000>;
144 opp-hz = /bits/ 64 <1250000000>;
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8186.dtsi45 opp-hz = /bits/ 64 <500000000>;
50 opp-hz = /bits/ 64 <560000000>;
55 opp-hz = /bits/ 64 <612000000>;
60 opp-hz = /bits/ 64 <682000000>;
65 opp-hz = /bits/ 64 <752000000>;
70 opp-hz = /bits/ 64 <822000000>;
75 opp-hz = /bits/ 64 <875000000>;
80 opp-hz = /bits/ 64 <927000000>;
85 opp-hz = /bits/ 64 <980000000>;
90 opp-hz = /bits/ 64 <1050000000>;
[all …]
H A Dmt8188.dtsi39 i-cache-sets = <128>;
42 d-cache-sets = <128>;
57 i-cache-sets = <128>;
60 d-cache-sets = <128>;
75 i-cache-sets = <128>;
78 d-cache-sets = <128>;
93 i-cache-sets = <128>;
96 d-cache-sets = <128>;
111 i-cache-sets = <128>;
114 d-cache-sets = <128>;
[all …]
H A Dmt8183.dtsi49 opp-hz = /bits/ 64 <793000000>;
54 opp-hz = /bits/ 64 <910000000>;
59 opp-hz = /bits/ 64 <1014000000>;
64 opp-hz = /bits/ 64 <1131000000>;
69 opp-hz = /bits/ 64 <1248000000>;
74 opp-hz = /bits/ 64 <1326000000>;
79 opp-hz = /bits/ 64 <1417000000>;
84 opp-hz = /bits/ 64 <1508000000>;
89 opp-hz = /bits/ 64 <1586000000>;
94 opp-hz = /bits/ 64 <1625000000>;
[all …]
/freebsd/sys/kern/
H A Dkern_clocksource.c244 hardfreq = hz / tc_min_ticktock_freq; in getnextcpuevent()
246 hardfreq = hz; in getnextcpuevent()
429 freq = hz * singlemul;
431 freq += hz;
630 * We honor the requested 'hz' value.
631 * We want to run stathz in the neighborhood of 128hz.
635 if (hz >= 1500 || (hz % 128) == 0)
637 else if (hz >= 750)
643 base = round_freq(timer, hz * singlemul);
644 singlemul = max((base + hz / 2) / hz, 1);
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra234.dtsi3548 snps,blen = <256 128 64 32>;
3590 snps,blen = <256 128 64 32>;
3632 snps,blen = <256 128 64 32>;
4432 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */
4470 …<0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4486 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */
4524 …<0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4540 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
4578 …<0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4594 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8qm.dtsi73 d-cache-sets = <128>;
90 d-cache-sets = <128>;
107 d-cache-sets = <128>;
124 d-cache-sets = <128>;
182 opp-hz = /bits/ 64 <600000000>;
188 opp-hz = /bits/ 64 <896000000>;
194 opp-hz = /bits/ 64 <1104000000>;
200 opp-hz = /bits/ 64 <1200000000>;
212 opp-hz = /bits/ 64 <600000000>;
218 opp-hz = /bits/ 64 <1056000000>;
[all …]
H A Dimx8qxp.dtsi68 d-cache-sets = <128>;
85 d-cache-sets = <128>;
102 d-cache-sets = <128>;
119 d-cache-sets = <128>;
141 opp-hz = /bits/ 64 <900000000>;
147 opp-hz = /bits/ 64 <1200000000>;
/freebsd/share/man/man7/
H A Dclocks.737 .Dv HZ
50 This is a real clock with frequency that happens to be 128.
55 This is a virtual clock with a frequency that happens to be 128.
76 This is a virtual clock with a frequency that happens to be 128.
158 .Dv HZ
/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-sm-k26-revA.dts172 reg = <0x100000 0x20000>; /* 128KB */
176 reg = <0x120000 0x20000>; /* 128KB */
220 reg = <0x2200000 0x20000>; /* 128KB */
224 reg = <0x2220000 0x20000>; /* 128KB */
234 reg = <0x2280000 0x20000>; /* 128KB */
467 opp-hz = /bits/ 64 <1333333333>;
470 opp-hz = /bits/ 64 <666666666>;
473 opp-hz = /bits/ 64 <444444444>;
476 opp-hz = /bits/ 64 <333333333>;
/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmt7615.h17 #define MT7615_WTBL_SIZE 128
22 #define MT7615_PM_TIMEOUT (HZ / 12)
23 #define MT7615_HW_SCAN_TIMEOUT (HZ / 10)
24 #define MT7615_RESET_TIMEOUT (30 * HZ)
28 #define MT7615_TX_MGMT_RING_SIZE 128
29 #define MT7615_TX_MCU_RING_SIZE 128
30 #define MT7615_TX_FWDL_RING_SIZE 128
451 return dev->pm.enable ? HZ / 3 : HZ / 10; in mt7615_get_macwork_timeout()
/freebsd/sys/contrib/device-tree/src/arm/intel/pxa/
H A Dpxa27x.dtsi37 gpio-ranges = <&pinctrl 0 0 128>;
153 opp-hz = /bits/ 64 <104000000>;
158 opp-hz = /bits/ 64 <156000000>;
163 opp-hz = /bits/ 64 <208000000>;
168 opp-hz = /bits/ 64 <312000000>;
173 opp-hz = /bits/ 64 <416000000>;
178 opp-hz = /bits/ 64 <520000000>;
183 opp-hz = /bits/ 64 <624000000>;
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76x02.h19 #define MT76x02_PSD_RING_SIZE 128
20 #define MT76x02_N_WCIDS 128
21 #define MT_CALIBRATE_INTERVAL HZ
22 #define MT_MAC_WORK_INTERVAL (HZ / 10)
24 #define MT_WATCHDOG_TIME (HZ / 10)
/freebsd/sys/contrib/device-tree/Bindings/iio/imu/
H A Dadi,adis16480.txt47 * 3000 to 4500 Hz for adis1649x devices.
48 * 700 to 2400 Hz for adis1648x devices.
54 * 1 to 128 Hz for adis1649x devices.
H A Dadi,adis16480.yaml73 * 3000 to 4500 Hz for adis1649x devices.
74 * 700 to 2400 Hz for adis1648x devices.
80 * 1 to 128 Hz for adis1649x devices.
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5420.dtsi158 opp-hz = /bits/ 64 <1800000000>;
163 opp-hz = /bits/ 64 <1700000000>;
168 opp-hz = /bits/ 64 <1600000000>;
173 opp-hz = /bits/ 64 <1500000000>;
178 opp-hz = /bits/ 64 <1400000000>;
183 opp-hz = /bits/ 64 <1300000000>;
188 opp-hz = /bits/ 64 <1200000000>;
193 opp-hz = /bits/ 64 <1100000000>;
198 opp-hz = /bits/ 64 <1000000000>;
203 opp-hz = /bits/ 64 <900000000>;
[all …]
/freebsd/share/man/man4/
H A Deventtimers.452 .Va hz
54 usually 1000Hz.
57 Called with frequency about 128Hz.
136 1, 2 or 4, depending on configured HZ value.
/freebsd/sys/arm/allwinner/
H A Daw_cir.c91 * Frequency sample: 23437.5Hz (Cycle: 42.7us)
96 /* Idle Threshold = (2 + 1) * 128 * 42.7 = ~16.4ms > 9ms */
106 /* Frequency sample 3MHz/64 = 46875Hz (21.3us) */
108 /* Frequency sample 3MHz/128 = 23437.5Hz (42.7us) */
142 #define AW_IR_RAW_BUF_SIZE 128
219 (AW_IR_ACTIVE_T_C_VAL != 0 ? 128 : 1); in aw_ir_decode_packets()
489 * Frequency sample = 3MHz/128 = 23437.5Hz (42.7us) in aw_ir_attach()
/freebsd/sys/contrib/device-tree/Bindings/iio/dac/
H A Dad5755.txt32 - adi,dc-dc-freq-hz:
33 Valid values for DC DC frequency is [Hz]:
86 128
98 adi,dc-dc-freq-hz = <410000>;
/freebsd/sys/contrib/device-tree/src/riscv/allwinner/
H A Dsun20i-d1s.dtsi23 i-cache-sets = <128>;
45 opp-hz = /bits/ 64 <408000000>;
50 opp-hz = /bits/ 64 <1008000000>;
/freebsd/sys/dev/mlx4/mlx4_en/
H A Den.h82 #define MAX_RX_RINGS 128
100 #define STATS_DELAY (HZ / 4)
101 #define SERVICE_TASK_DELAY (HZ / 4)
119 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
167 #define MLX4_EN_RX_COAL_TIME_HIGH 128
181 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
185 #define HEADER_COPY_SIZE (128)
196 #define AVG_SIZE 128
217 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
270 ((MLX4_EN_TX_MAX_DESC_SIZE - 128) / DS_SIZE_ALIGNMENT) /* units */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun8i-a33.dtsi54 opp-hz = /bits/ 64 <120000000>;
60 opp-hz = /bits/ 64 <240000000>;
66 opp-hz = /bits/ 64 <312000000>;
72 opp-hz = /bits/ 64 <408000000>;
78 opp-hz = /bits/ 64 <480000000>;
84 opp-hz = /bits/ 64 <504000000>;
90 opp-hz = /bits/ 64 <600000000>;
96 opp-hz = /bits/ 64 <648000000>;
102 opp-hz = /bits/ 64 <720000000>;
108 opp-hz = /bits/ 64 <816000000>;
[all …]
/freebsd/sys/isa/
H A Drtc.h56 #define RTCSA_DIVIDER 0x20 /* divider correct for 32768 Hz */
57 #define RTCSA_8192 0x03 /* 8192 Hz interrupt */
67 #define RTC_NOPROFRATE 128
69 #define RTCSA_32 0x0b /* 32 Hz interrupt */
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos5433.dtsi101 d-cache-sets = <128>;
117 d-cache-sets = <128>;
133 d-cache-sets = <128>;
149 d-cache-sets = <128>;
243 opp-hz = /bits/ 64 <400000000>;
247 opp-hz = /bits/ 64 <500000000>;
251 opp-hz = /bits/ 64 <600000000>;
255 opp-hz = /bits/ 64 <700000000>;
259 opp-hz = /bits/ 64 <800000000>;
263 opp-hz = /bits/ 64 <900000000>;
[all …]
/freebsd/sys/dev/usb/video/
H A Dudl.h70 uint8_t sc_edid[128];
138 static const uint8_t udl_reg_vals_640x480_60[UDL_MODE_SIZE] = { /* 25.17 Mhz 59.9 Hz
144 static const uint8_t udl_reg_vals_640x480_67[UDL_MODE_SIZE] = { /* 30.25 MHz 66.6 Hz MAC
150 static const uint8_t udl_reg_vals_640x480_72[UDL_MODE_SIZE] = { /* 31.50 Mhz 72.8 Hz
156 static const uint8_t udl_reg_vals_640x480_75[UDL_MODE_SIZE] = { /* 31.50 Mhz 75.7 Hz
162 static const uint8_t udl_reg_vals_800x480_61[UDL_MODE_SIZE] = { /* 33.00 MHz 61.9 Hz */
167 static const uint8_t udl_reg_vals_800x600_56[UDL_MODE_SIZE] = { /* 36.00 MHz 56.2 Hz
173 static const uint8_t udl_reg_vals_800x600_60[UDL_MODE_SIZE] = { /* 40.00 MHz 60.3 Hz
179 static const uint8_t udl_reg_vals_800x600_72[UDL_MODE_SIZE] = { /* 50.00 MHz 72.1 Hz
185 static const uint8_t udl_reg_vals_800x600_74[UDL_MODE_SIZE] = { /* 50.00 MHz 74.4 Hz */
[all …]

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