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/linux/tools/testing/selftests/net/forwarding/
H A Dbridge_mdb.sh6 # | + $h1.10 | | + $h2.10 |
21 # | | vid 10 vid 10 | |
41 vlan_create $h1 10 v$h1 192.0.2.1/28 2001:db8:1::1/64
48 vlan_destroy $h1 10
55 vlan_create $h2 10 v$h2 192.0.2.2/28
62 vlan_destroy $h2 10
73 bridge vlan add vid 10 dev br0 self
79 bridge vlan add vid 10 de
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/linux/lib/crc/x86/
H A Dcrc-pclmul-consts.h12 * G(x) = x^16 + x^15 + x^11 + x^9 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + x^0
24 .bswap_mask = {15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0},
26 0xdccf000000000000, /* LO64_TERMS: (x^2000 mod G) * x^48 */
27 0x4b0b000000000000, /* HI64_TERMS: (x^2064 mod G) * x^48 */
30 0x9d9d000000000000, /* LO64_TERMS: (x^976 mod G) * x^48 */
31 0x7cf5000000000000, /* HI64_TERMS: (x^1040 mod G) * x^48 */
34 0x044c000000000000, /* LO64_TERMS: (x^464 mod G) * x^48 */
35 0xe658000000000000, /* HI64_TERMS: (x^528 mod G) * x^48 */
38 0x6ee3000000000000, /* LO64_TERMS: (x^208 mod G) * x^48 */
39 0xe7b5000000000000, /* HI64_TERMS: (x^272 mod G) * x^48 */
[all …]
/linux/Documentation/gpu/
H A Dafbc.rst22 corresponds to a color channel (i.e. R, G, B, X, A, Y, Cb, Cr).
32 * Component 1: G
43 * Component 1: G(8)
50 * Component 1: G(8)
66 * Component 1: G(8)
76 which doesn't include alpha can be used, e.g. DRM_FORMAT_BGR888.
81 Formats which are typically multi-planar in linear layouts (e.g. YUV
126 - 10-bit per component RGB, with 2-bit alpha
128 * Component 0: R(10)
129 * Component 1: G(10)
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/linux/include/dt-bindings/memory/
H A Dmt8195-memory-port.h13 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
16 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
21 * disp 0 ~ 4G larb0/1/2/3
22 * vcodec 4G ~ 8G larb19/20/21/22/23/24
23 * cam/mdp 8G ~ 12G the other larbs.
24 * N/A 12G ~ 16G
29 * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
110 #define M4U_PORT_L9_IMG_IMGBI_T1_B MTK_M4U_ID(9, 10)
122 #define M4U_PORT_L10_IMG_IMGI_D1_A MTK_M4U_ID(10, 0)
123 #define M4U_PORT_L10_IMG_IMGCI_D1_A MTK_M4U_ID(10, 1)
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H A Dmt8186-memory-port.h15 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
18 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
23 * disp 0 ~ 4G larb0/1/2
24 * vcodec 4G ~ 8G larb4/7
25 * cam/mdp 8G ~ 12G the other larbs.
26 * N/A 12G ~ 16G
27 * CCU0 0x24000_0000 ~ 0x243ff_ffff larb13: port 9/10
63 #define IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(4, 10)
79 #define IOMMU_PORT_L7_JPGENC_C_RDMA MTK_M4U_ID(7, 10)
99 #define IOMMU_PORT_L9_IMG_VIPI_D1 MTK_M4U_ID(9, 10)
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H A Dmediatek,mt8189-memory-port.h21 #define SMI_L17_ID (10)
27 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
30 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
35 * disp/mdp 0 ~ 4G larb0/1/2
36 * vcodec 4G ~ 8G larb4/7
37 * imgsys/cam/ipesys 8G ~ 12G the other larbs.
38 * N/A 12G ~ 16G
72 #define M4U_L2_P10_DISP_FAKE0 MTK_M4U_ID(SMI_L2_ID, 10)
87 #define M4U_L4_P10_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(SMI_L4_ID, 10)
105 #define M4U_L7_P10_VENC_CUR_LUMA MTK_M4U_ID(SMI_L7_ID, 10)
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H A Dmediatek,mt8188-memory-port.h27 #define SMI_L11A_ID 10
46 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
49 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
54 * disp 0 ~ 4G larb0/1/2/3
55 * vcodec 4G ~ 8G larb19(21)[1]/21(22)/23
56 * cam/mdp 8G ~ 12G the other larbs.
57 * N/A 12G ~ 16G
62 * iommu-vdo: larb0/2/5/9/10/11A/11C/13/16B/17B/19/21
144 #define M4U_PORT_L9_YUVCO_T1_A MTK_M4U_ID(SMI_L9_ID, 10)
160 /* LARB 10 -- IMG-D */
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/linux/include/uapi/linux/
H A Dmdio.h28 #define MDIO_MMD_SEP_PMA3 10 /* Separated PMA (3) */
43 #define MDIO_CTRL2 7 /* 10G control 2 */
44 #define MDIO_STAT2 8 /* 10G status 2 */
45 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
46 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
47 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
54 #define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */
64 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
65 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
66 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
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/linux/lib/crc/riscv/
H A Dcrc-clmul-consts.h19 * G(x) = x^16 + x^15 + x^11 + x^9 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + x^0
23 .fold_across_2_longs_const_hi = 0x0000000000001faa, /* x^192 mod G */
24 .fold_across_2_longs_const_lo = 0x000000000000a010, /* x^128 mod G */
25 .barrett_reduction_const_1 = 0xfb2d2bfc0e99d245, /* floor(x^79 / G) */
26 .barrett_reduction_const_2 = 0x0000000000008bb7, /* G - x^16 */
28 .fold_across_2_longs_const_hi = 0x00005890, /* x^96 mod G */
29 .fold_across_2_longs_const_lo = 0x0000f249, /* x^64 mod G */
30 .barrett_reduction_const_1 = 0xfb2d2bfc, /* floor(x^47 / G) */
31 .barrett_reduction_const_2 = 0x00008bb7, /* G - x^16 */
37 * G(x) = x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 +
[all …]
/linux/lib/crypto/
H A Dblake2s.c20 static const u8 blake2s_sigma[10][16] = {
21 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
22 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
23 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
24 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
25 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
26 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
27 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
28 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
29 { 6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10,
64 #define G( blake2s_compress_generic() macro
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H A Dblake2b.c21 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
22 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
23 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
24 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
25 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
26 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
27 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
28 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
29 { 6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5 },
30 { 10,
66 #define G( blake2b_compress_generic() macro
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/linux/tools/perf/util/
H A Dblake2s.c30 static const u8 blake2s_sigma[10][16] = {
31 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
32 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
33 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
34 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
35 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
36 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
37 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
38 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
39 { 6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5 },
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dpixfmt-srggb10p.rst17 10-bit packed Bayer formats
23 These four pixel formats are packed raw sRGB / Bayer formats with 10
46 - G\ :sub:`01high`
48 - G\ :sub:`03high`
49 - G\ :sub:`03low`\ (bits 7--6) B\ :sub:`02low`\ (bits 5--4)
51 G\ :sub:`01low`\ (bits 3--2) B\ :sub:`00low`\ (bits 1--0)
53 - G\ :sub:`10high`
55 - G\ :sub:`12high`
57 - R\ :sub:`13low`\ (bits 7--6) G\ :sub:`12low`\ (bits 5--4)
59 R\ :sub:`11low`\ (bits 3--2) G\ :sub:`10low`\ (bits 1--0)
[all …]
H A Dpixfmt-srggb10.rst17 10-bit Bayer formats expanded to 16 bits
23 These four pixel formats are raw sRGB / Bayer formats with 10 bits per
45 - G\ :sub:`01low`
46 - G\ :sub:`01high`
49 - G\ :sub:`03low`
50 - G\ :sub:`03high`
52 - G\ :sub:`10low`
53 - G\ :sub:`10high`
56 - G\ :sub:`12low`
57 - G\ :sub:`12high`
[all …]
H A Dcrop.svg51 objecttolerance="10"
52 gridtolerance="10"
53 guidetolerance="10"
71 fit-margin-bottom="0" /><g
81 …dth:0.33962813;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:10;stroke-dasharray:non…
85 …dth:0.33962813;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:10;stroke-dasharray:non…
89 …dth:0.33962813;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:10;stroke-dasharray:non…
93 …dth:0.33962813;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:10;stroke-dasharray:non…
97 …dth:0.33962813;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:10;stroke-dasharray:non…
105 …dth:0.33962813;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:10;stroke-dasharray:non…
[all …]
H A Dvbi_hsync.svg22 objecttolerance="10"
23 gridtolerance="10"
24 guidetolerance="10"
64 style="clip-rule:evenodd" /></clipPath></defs><g
68 transform="matrix(1.25,0,0,-1.25,-0.3625824,520.79867)"><g
74 …dth:2.40974998;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:10;stroke-dasharray:non…
78 …dth:2.40974998;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:10;stroke-dasharray:non…
82 …dth:2.40974998;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:10;stroke-dasharray:non…
86 …dth:2.40974998;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:10;stroke-dasharray:non…
90 …dth:4.81949997;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:10;stroke-dasharray:non…
[all …]
/linux/drivers/media/platform/samsung/exynos-gsc/
H A Dgsc-regs.h6 * Register definition file for Samsung G-Scaler driver
12 /* G-Scaler enable */
18 /* G-Scaler S/W reset */
22 /* G-Scaler IRQ */
29 /* G-Scaler input control */
65 /* G-Scaler source image size */
70 /* G-Scaler source image offset */
75 /* G-Scaler cropped source image size */
80 /* G-Scaler output control */
84 #define GSC_OUT_RGB_TYPE_MASK (3 << 10)
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dfsl,fman-port.yaml49 fsl,fman-10g-port:
51 description: The default port rate is 1G.
52 If this property exists, the port is s 10G port.
56 description: The default port rate is 1G.
57 Can be defined only if 10G-support is set.
58 This property marks a best-effort 10G port (10G port that
H A Dmicrochip,sparx5-switch.yaml23 IPv6 (S,G) multicast groups.
31 1G/2.5G/5G/10G switching with 10G/25G aggregation links is required.
233 /* Then the 25G interfaces */
238 phy-mode = "10gbase-r";
247 phy-mode = "10gbase-r";
256 phy-mode = "10gbase-r";
265 phy-mode = "10gbase-r";
/linux/drivers/gpu/drm/exynos/
H A Dregs-gsc.h7 * Register definition file for Samsung G-Scaler driver
13 /* G-Scaler enable */
33 /* G-Scaler S/W reset */
37 /* G-Scaler IRQ */
45 /* G-Scaler input control */
91 /* G-Scaler source image size */
98 /* G-Scaler source image offset */
105 /* G-Scaler cropped source image size */
112 /* G-Scaler output control */
120 #define GSC_OUT_RGB_TYPE_MASK (3 << 10)
[all …]
/linux/Documentation/bpf/
H A Dllvm_reloc.rst40 6: 0f 10 00 00 00 00 00 00 r0 += r1
44 10: 0f 10 00 00 00 00 00 00 r0 += r1
48 14: 0f 10 00 00 00 00 00 00 r0 += r1
115 10 R_BPF_64_32 call insn 32 r_offset + 4 (S + A) / 8 - 1
168 2: 85 10 00 00 ff ff ff ff call -1
173 6: 85 10 00 00 02 00 00 00 call 2
178 10: 61 11 00 00 00 00 00 00 r1 = *(u32 *)(r1 + 0)
179 11: 0f 10 00 00 00 00 00 00 r0 += r1
186 1: 2f 10 00 00 00 00 00 00 r0 *= r1
191 4: 0f 10 00 00 00 00 00 00 r0 += r1
[all …]
/linux/Documentation/networking/device_drivers/ethernet/intel/
H A Dixgbe.rst4 Linux Base Driver for the Intel(R) Ethernet 10 Gigabit PCI Express Adapters
7 Intel 10 Gigabit Linux driver.
53 | Intel | DUAL RATE 1G/10G SFP+ SR (bailed) | FTLX8571D3BCV-IT |
55 | Intel | DUAL RATE 1G/10G SFP+ SR (bailed) | AFBR-703SDZ-IN2 |
57 | Intel | DUAL RATE 1G/10G SFP+ SR (bailed) | AFBR-703SDDZ-IN1 |
61 | Intel | DUAL RATE 1G/10G SFP+ LR (bailed) | FTLX1471D3BCV-IT |
63 | Intel | DUAL RATE 1G/10G SFP+ LR (bailed) | AFCT-701SDZ-IN2 |
65 | Intel | DUAL RATE 1G/10G SFP+ LR (bailed) | AFCT-701SDDZ-IN1 |
74 | Finisar | SFP+ SR bailed, 10g single rate | FTLX8571D3BCL |
76 | Avago | SFP+ SR bailed, 10g single rate | AFBR-700SDZ |
[all …]
/linux/drivers/net/ethernet/tehuti/
H A DKconfig21 tristate "Tehuti Networks 10G Ethernet"
24 Tehuti Networks 10G Ethernet NIC
27 tristate "Tehuti Networks TN40xx 10G Ethernet adapters"
33 This driver supports 10G Ethernet adapters using Tehuti Networks
/linux/arch/arm/boot/dts/st/
H A Dstm32mp13-pinctrl.dtsi36 <STM32_PINMUX('G', 9, AF13)>,/* DCMI_VSYNC */
40 <STM32_PINMUX('G', 10, AF13)>,/* DCMI_D2 */
54 <STM32_PINMUX('G', 9, ANALOG)>,/* DCMI_VSYNC */
58 <STM32_PINMUX('G', 10, ANALOG)>,/* DCMI_D2 */
70 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
71 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
77 <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
98 <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
105 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
106 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
[all …]
/linux/drivers/net/ethernet/microchip/sparx5/lan969x/
H A Dlan969x_calendar.c9 #define LAN969X_DSM_CAL_DEVS_PER_TAXI 10
16 DSM_CAL_DEV_OTHER, /* 1G or less */
21 * (10G, 5G, 2.5G, or 1G or less).
40 { 8, 12, 9, 13, 10, 11, 14, 15, 99, 99 },
106 /* Determine the different port types (10G, in lan969x_dsm_calendar_calc()
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