1*812df545SZhengnan Chen /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*812df545SZhengnan Chen /* 3*812df545SZhengnan Chen * Copyright (c) 2025 MediaTek Inc. 4*812df545SZhengnan Chen * Author: Zhengnan chen <zhengnan.chen@mediatek.com> 5*812df545SZhengnan Chen */ 6*812df545SZhengnan Chen #ifndef _DT_BINDINGS_MEMORY_MEDIATEK_MT8189_MEMORY_PORT_H_ 7*812df545SZhengnan Chen #define _DT_BINDINGS_MEMORY_MEDIATEK_MT8189_MEMORY_PORT_H_ 8*812df545SZhengnan Chen 9*812df545SZhengnan Chen #include <dt-bindings/memory/mtk-memory-port.h> 10*812df545SZhengnan Chen 11*812df545SZhengnan Chen #define SMI_L0_ID (0) 12*812df545SZhengnan Chen #define SMI_L1_ID (1) 13*812df545SZhengnan Chen #define SMI_L2_ID (2) 14*812df545SZhengnan Chen #define SMI_L4_ID (3) 15*812df545SZhengnan Chen #define SMI_L7_ID (4) 16*812df545SZhengnan Chen #define SMI_L9_ID (5) 17*812df545SZhengnan Chen #define SMI_L11_ID (6) 18*812df545SZhengnan Chen #define SMI_L13_ID (7) 19*812df545SZhengnan Chen #define SMI_L14_ID (8) 20*812df545SZhengnan Chen #define SMI_L16_ID (9) 21*812df545SZhengnan Chen #define SMI_L17_ID (10) 22*812df545SZhengnan Chen #define SMI_L19_ID (11) 23*812df545SZhengnan Chen #define SMI_L20_ID (12) 24*812df545SZhengnan Chen 25*812df545SZhengnan Chen /* 26*812df545SZhengnan Chen * MM IOMMU supports 16GB dma address. We separate it to four ranges: 27*812df545SZhengnan Chen * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters 28*812df545SZhengnan Chen * locate in anyone region. BUT: 29*812df545SZhengnan Chen * a) Make sure all the ports inside a larb are in one range. 30*812df545SZhengnan Chen * b) The iova of any master can NOT cross the 4G/8G/12G boundary. 31*812df545SZhengnan Chen * 32*812df545SZhengnan Chen * This is the suggested mapping in this SoC: 33*812df545SZhengnan Chen * 34*812df545SZhengnan Chen * modules dma-address-region larbs-ports 35*812df545SZhengnan Chen * disp/mdp 0 ~ 4G larb0/1/2 36*812df545SZhengnan Chen * vcodec 4G ~ 8G larb4/7 37*812df545SZhengnan Chen * imgsys/cam/ipesys 8G ~ 12G the other larbs. 38*812df545SZhengnan Chen * N/A 12G ~ 16G 39*812df545SZhengnan Chen */ 40*812df545SZhengnan Chen 41*812df545SZhengnan Chen /* Larb0 -- disp */ 42*812df545SZhengnan Chen #define M4U_L0_P0_DISP_OVL0_4L_HDR MTK_M4U_ID(SMI_L0_ID, 0) 43*812df545SZhengnan Chen #define M4U_L0_P1_DISP_OVL0_4L_RDMA0 MTK_M4U_ID(SMI_L0_ID, 1) 44*812df545SZhengnan Chen #define M4U_L0_P2_DISP_OVL1_4L_RDMA1 MTK_M4U_ID(SMI_L0_ID, 2) 45*812df545SZhengnan Chen #define M4U_L0_P3_DISP_OVL0_4L_RDMA2 MTK_M4U_ID(SMI_L0_ID, 3) 46*812df545SZhengnan Chen #define M4U_L0_P4_DISP_OVL1_4L_RDMA3 MTK_M4U_ID(SMI_L0_ID, 4) 47*812df545SZhengnan Chen #define M4U_L0_P5_DISP_RDMA0 MTK_M4U_ID(SMI_L0_ID, 5) 48*812df545SZhengnan Chen #define M4U_L0_P6_DISP_WDMA0 MTK_M4U_ID(SMI_L0_ID, 6) 49*812df545SZhengnan Chen #define M4U_L0_P7_DISP_FAKE_ENG0 MTK_M4U_ID(SMI_L0_ID, 7) 50*812df545SZhengnan Chen 51*812df545SZhengnan Chen /* Larb1 -- disp */ 52*812df545SZhengnan Chen #define M4U_L1_P0_DISP_OVL1_4L_HDR MTK_M4U_ID(SMI_L1_ID, 0) 53*812df545SZhengnan Chen #define M4U_L1_P1_DISP_OVL1_4L_RDMA0 MTK_M4U_ID(SMI_L1_ID, 1) 54*812df545SZhengnan Chen #define M4U_L1_P2_DISP_OVL0_4L_RDMA1 MTK_M4U_ID(SMI_L1_ID, 2) 55*812df545SZhengnan Chen #define M4U_L1_P3_DISP_OVL1_4L_RDMA2 MTK_M4U_ID(SMI_L1_ID, 3) 56*812df545SZhengnan Chen #define M4U_L1_P4_DISP_OVL0_4L_RDMA3 MTK_M4U_ID(SMI_L1_ID, 4) 57*812df545SZhengnan Chen #define M4U_L1_P5_DISP_RDMA1 MTK_M4U_ID(SMI_L1_ID, 5) 58*812df545SZhengnan Chen #define M4U_L1_P6_DISP_WDMA1 MTK_M4U_ID(SMI_L1_ID, 6) 59*812df545SZhengnan Chen #define M4U_L1_P7_DISP_FAKE_ENG1 MTK_M4U_ID(SMI_L1_ID, 7) 60*812df545SZhengnan Chen 61*812df545SZhengnan Chen /* Larb2 -- mmlsys(mdp) */ 62*812df545SZhengnan Chen #define M4U_L2_P0_MDP_RDMA0 MTK_M4U_ID(SMI_L2_ID, 0) 63*812df545SZhengnan Chen #define M4U_L2_P1_MDP_RDMA1 MTK_M4U_ID(SMI_L2_ID, 1) 64*812df545SZhengnan Chen #define M4U_L2_P2_MDP_WROT0 MTK_M4U_ID(SMI_L2_ID, 2) 65*812df545SZhengnan Chen #define M4U_L2_P3_MDP_WROT1 MTK_M4U_ID(SMI_L2_ID, 3) 66*812df545SZhengnan Chen #define M4U_L2_P4_MDP_DUMMY0 MTK_M4U_ID(SMI_L2_ID, 4) 67*812df545SZhengnan Chen #define M4U_L2_P5_MDP_DUMMY1 MTK_M4U_ID(SMI_L2_ID, 5) 68*812df545SZhengnan Chen #define M4U_L2_P6_MDP_RDMA2 MTK_M4U_ID(SMI_L2_ID, 6) 69*812df545SZhengnan Chen #define M4U_L2_P7_MDP_RDMA3 MTK_M4U_ID(SMI_L2_ID, 7) 70*812df545SZhengnan Chen #define M4U_L2_P8_MDP_WROT2 MTK_M4U_ID(SMI_L2_ID, 8) 71*812df545SZhengnan Chen #define M4U_L2_P9_MDP_WROT3 MTK_M4U_ID(SMI_L2_ID, 9) 72*812df545SZhengnan Chen #define M4U_L2_P10_DISP_FAKE0 MTK_M4U_ID(SMI_L2_ID, 10) 73*812df545SZhengnan Chen 74*812df545SZhengnan Chen /* Larb3: null */ 75*812df545SZhengnan Chen 76*812df545SZhengnan Chen /* Larb4 -- vdec */ 77*812df545SZhengnan Chen #define M4U_L4_P0_HW_VDEC_MC_EXT MTK_M4U_ID(SMI_L4_ID, 0) 78*812df545SZhengnan Chen #define M4U_L4_P1_HW_VDEC_UFO_EXT MTK_M4U_ID(SMI_L4_ID, 1) 79*812df545SZhengnan Chen #define M4U_L4_P2_HW_VDEC_PP_EXT MTK_M4U_ID(SMI_L4_ID, 2) 80*812df545SZhengnan Chen #define M4U_L4_P3_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(SMI_L4_ID, 3) 81*812df545SZhengnan Chen #define M4U_L4_P4_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(SMI_L4_ID, 4) 82*812df545SZhengnan Chen #define M4U_L4_P5_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(SMI_L4_ID, 5) 83*812df545SZhengnan Chen #define M4U_L4_P6_HW_VDEC_TILE_EXT MTK_M4U_ID(SMI_L4_ID, 6) 84*812df545SZhengnan Chen #define M4U_L4_P7_HW_VDEC_VLD_EXT MTK_M4U_ID(SMI_L4_ID, 7) 85*812df545SZhengnan Chen #define M4U_L4_P8_HW_VDEC_VLD2_EXT MTK_M4U_ID(SMI_L4_ID, 8) 86*812df545SZhengnan Chen #define M4U_L4_P9_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(SMI_L4_ID, 9) 87*812df545SZhengnan Chen #define M4U_L4_P10_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(SMI_L4_ID, 10) 88*812df545SZhengnan Chen #define M4U_L4_P11_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(SMI_L4_ID, 11) 89*812df545SZhengnan Chen 90*812df545SZhengnan Chen /* Larb5: null */ 91*812df545SZhengnan Chen 92*812df545SZhengnan Chen /* Larb6: null */ 93*812df545SZhengnan Chen 94*812df545SZhengnan Chen /* Larb7 -- venc */ 95*812df545SZhengnan Chen #define M4U_L7_P0_VENC_RCPU MTK_M4U_ID(SMI_L7_ID, 0) 96*812df545SZhengnan Chen #define M4U_L7_P1_VENC_REC MTK_M4U_ID(SMI_L7_ID, 1) 97*812df545SZhengnan Chen #define M4U_L7_P2_VENC_BSDMA MTK_M4U_ID(SMI_L7_ID, 2) 98*812df545SZhengnan Chen #define M4U_L7_P3_VENC_SV_COMV MTK_M4U_ID(SMI_L7_ID, 3) 99*812df545SZhengnan Chen #define M4U_L7_P4_VENC_RD_COMV MTK_M4U_ID(SMI_L7_ID, 4) 100*812df545SZhengnan Chen #define M4U_L7_P5_JPGENC_Y_RDMA MTK_M4U_ID(SMI_L7_ID, 5) 101*812df545SZhengnan Chen #define M4U_L7_P6_JPGENC_C_RDMA MTK_M4U_ID(SMI_L7_ID, 6) 102*812df545SZhengnan Chen #define M4U_L7_P7_JPGENC_Q_RDMA MTK_M4U_ID(SMI_L7_ID, 7) 103*812df545SZhengnan Chen #define M4U_L7_P8_VENC_SUB_W_LUMA MTK_M4U_ID(SMI_L7_ID, 8) 104*812df545SZhengnan Chen #define M4U_L7_P9_JPGENC_BSDMA MTK_M4U_ID(SMI_L7_ID, 9) 105*812df545SZhengnan Chen #define M4U_L7_P10_VENC_CUR_LUMA MTK_M4U_ID(SMI_L7_ID, 10) 106*812df545SZhengnan Chen #define M4U_L7_P11_VENC_CUR_CHROMA MTK_M4U_ID(SMI_L7_ID, 11) 107*812df545SZhengnan Chen #define M4U_L7_P12_VENC_REF_LUMA MTK_M4U_ID(SMI_L7_ID, 12) 108*812df545SZhengnan Chen #define M4U_L7_P13_VENC_REF_CHROMA MTK_M4U_ID(SMI_L7_ID, 13) 109*812df545SZhengnan Chen #define M4U_L7_P14_VENC_SUB_R_LUMA MTK_M4U_ID(SMI_L7_ID, 14) 110*812df545SZhengnan Chen #define M4U_L7_P15_JPGDEC_WDMA MTK_M4U_ID(SMI_L7_ID, 15) 111*812df545SZhengnan Chen #define M4U_L7_P16_JPGDEC_BSDMA MTK_M4U_ID(SMI_L7_ID, 16) 112*812df545SZhengnan Chen #define M4U_L7_P17_JPGDEC_HUFF_OFFSET MTK_M4U_ID(SMI_L7_ID, 17) 113*812df545SZhengnan Chen 114*812df545SZhengnan Chen /* Larb8: null */ 115*812df545SZhengnan Chen 116*812df545SZhengnan Chen /* Larb9 --imgsys */ 117*812df545SZhengnan Chen #define M4U_L9_P0_IMGI_D1 MTK_M4U_ID(SMI_L9_ID, 0) 118*812df545SZhengnan Chen #define M4U_L9_P1_IMGBI_D1 MTK_M4U_ID(SMI_L9_ID, 1) 119*812df545SZhengnan Chen #define M4U_L9_P2_DMGI_D1 MTK_M4U_ID(SMI_L9_ID, 2) 120*812df545SZhengnan Chen #define M4U_L9_P3_DEPI_D1 MTK_M4U_ID(SMI_L9_ID, 3) 121*812df545SZhengnan Chen #define M4U_L9_P4_LCE_D1 MTK_M4U_ID(SMI_L9_ID, 4) 122*812df545SZhengnan Chen #define M4U_L9_P5_SMTI_D1 MTK_M4U_ID(SMI_L9_ID, 5) 123*812df545SZhengnan Chen #define M4U_L9_P6_SMTO_D2 MTK_M4U_ID(SMI_L9_ID, 6) 124*812df545SZhengnan Chen #define M4U_L9_P7_SMTO_D1 MTK_M4U_ID(SMI_L9_ID, 7) 125*812df545SZhengnan Chen #define M4U_L9_P8_CRZO_D1 MTK_M4U_ID(SMI_L9_ID, 8) 126*812df545SZhengnan Chen #define M4U_L9_P9_IMG3O_D1 MTK_M4U_ID(SMI_L9_ID, 9) 127*812df545SZhengnan Chen #define M4U_L9_P10_VIPI_D1 MTK_M4U_ID(SMI_L9_ID, 10) 128*812df545SZhengnan Chen #define M4U_L9_P11_SMTI_D5 MTK_M4U_ID(SMI_L9_ID, 11) 129*812df545SZhengnan Chen #define M4U_L9_P12_TIMGO_D1 MTK_M4U_ID(SMI_L9_ID, 12) 130*812df545SZhengnan Chen #define M4U_L9_P13_UFBC_W0 MTK_M4U_ID(SMI_L9_ID, 13) 131*812df545SZhengnan Chen #define M4U_L9_P14_UFBC_R0 MTK_M4U_ID(SMI_L9_ID, 14) 132*812df545SZhengnan Chen #define M4U_L9_P15_WPE_RDMA1 MTK_M4U_ID(SMI_L9_ID, 15) 133*812df545SZhengnan Chen #define M4U_L9_P16_WPE_RDMA0 MTK_M4U_ID(SMI_L9_ID, 16) 134*812df545SZhengnan Chen #define M4U_L9_P17_WPE_WDMA MTK_M4U_ID(SMI_L9_ID, 17) 135*812df545SZhengnan Chen #define M4U_L9_P18_MFB_RDMA0 MTK_M4U_ID(SMI_L9_ID, 18) 136*812df545SZhengnan Chen #define M4U_L9_P19_MFB_RDMA1 MTK_M4U_ID(SMI_L9_ID, 19) 137*812df545SZhengnan Chen #define M4U_L9_P20_MFB_RDMA2 MTK_M4U_ID(SMI_L9_ID, 20) 138*812df545SZhengnan Chen #define M4U_L9_P21_MFB_RDMA3 MTK_M4U_ID(SMI_L9_ID, 21) 139*812df545SZhengnan Chen #define M4U_L9_P22_MFB_RDMA4 MTK_M4U_ID(SMI_L9_ID, 22) 140*812df545SZhengnan Chen #define M4U_L9_P23_MFB_RDMA5 MTK_M4U_ID(SMI_L9_ID, 23) 141*812df545SZhengnan Chen #define M4U_L9_P24_MFB_WDMA0 MTK_M4U_ID(SMI_L9_ID, 24) 142*812df545SZhengnan Chen #define M4U_L9_P25_MFB_WDMA1 MTK_M4U_ID(SMI_L9_ID, 25) 143*812df545SZhengnan Chen #define M4U_L9_P26_RESERVE6 MTK_M4U_ID(SMI_L9_ID, 26) 144*812df545SZhengnan Chen #define M4U_L9_P27_RESERVE7 MTK_M4U_ID(SMI_L9_ID, 27) 145*812df545SZhengnan Chen #define M4U_L9_P28_RESERVE8 MTK_M4U_ID(SMI_L9_ID, 28) 146*812df545SZhengnan Chen 147*812df545SZhengnan Chen /* Larb10: null */ 148*812df545SZhengnan Chen 149*812df545SZhengnan Chen /* Larb11 -- imgsys */ 150*812df545SZhengnan Chen #define M4U_L11_P0_IMGI_D1 MTK_M4U_ID(SMI_L11_ID, 0) 151*812df545SZhengnan Chen #define M4U_L11_P1_IMGBI_D1 MTK_M4U_ID(SMI_L11_ID, 1) 152*812df545SZhengnan Chen #define M4U_L11_P2_DMGI_D1 MTK_M4U_ID(SMI_L11_ID, 2) 153*812df545SZhengnan Chen #define M4U_L11_P3_DEPI_D1 MTK_M4U_ID(SMI_L11_ID, 3) 154*812df545SZhengnan Chen #define M4U_L11_P4_LCE_D1 MTK_M4U_ID(SMI_L11_ID, 4) 155*812df545SZhengnan Chen #define M4U_L11_P5_SMTI_D1 MTK_M4U_ID(SMI_L11_ID, 5) 156*812df545SZhengnan Chen #define M4U_L11_P6_SMTO_D2 MTK_M4U_ID(SMI_L11_ID, 6) 157*812df545SZhengnan Chen #define M4U_L11_P7_SMTO_D1 MTK_M4U_ID(SMI_L11_ID, 7) 158*812df545SZhengnan Chen #define M4U_L11_P8_CRZO_D1 MTK_M4U_ID(SMI_L11_ID, 8) 159*812df545SZhengnan Chen #define M4U_L11_P9_IMG3O_D1 MTK_M4U_ID(SMI_L11_ID, 9) 160*812df545SZhengnan Chen #define M4U_L11_P10_VIPI_D1 MTK_M4U_ID(SMI_L11_ID, 10) 161*812df545SZhengnan Chen #define M4U_L11_P11_SMTI_D5 MTK_M4U_ID(SMI_L11_ID, 11) 162*812df545SZhengnan Chen #define M4U_L11_P12_TIMGO_D1 MTK_M4U_ID(SMI_L11_ID, 12) 163*812df545SZhengnan Chen #define M4U_L11_P13_UFBC_W0 MTK_M4U_ID(SMI_L11_ID, 13) 164*812df545SZhengnan Chen #define M4U_L11_P14_UFBC_R0 MTK_M4U_ID(SMI_L11_ID, 14) 165*812df545SZhengnan Chen #define M4U_L11_P15_WPE_RDMA1 MTK_M4U_ID(SMI_L11_ID, 15) 166*812df545SZhengnan Chen #define M4U_L11_P16_WPE_RDMA0 MTK_M4U_ID(SMI_L11_ID, 16) 167*812df545SZhengnan Chen #define M4U_L11_P17_WPE_WDMA MTK_M4U_ID(SMI_L11_ID, 17) 168*812df545SZhengnan Chen #define M4U_L11_P18_MFB_RDMA0 MTK_M4U_ID(SMI_L11_ID, 18) 169*812df545SZhengnan Chen #define M4U_L11_P19_MFB_RDMA1 MTK_M4U_ID(SMI_L11_ID, 19) 170*812df545SZhengnan Chen #define M4U_L11_P20_MFB_RDMA2 MTK_M4U_ID(SMI_L11_ID, 20) 171*812df545SZhengnan Chen #define M4U_L11_P21_MFB_RDMA3 MTK_M4U_ID(SMI_L11_ID, 21) 172*812df545SZhengnan Chen #define M4U_L11_P22_MFB_RDMA4 MTK_M4U_ID(SMI_L11_ID, 22) 173*812df545SZhengnan Chen #define M4U_L11_P23_MFB_RDMA5 MTK_M4U_ID(SMI_L11_ID, 23) 174*812df545SZhengnan Chen #define M4U_L11_P24_MFB_WDMA0 MTK_M4U_ID(SMI_L11_ID, 24) 175*812df545SZhengnan Chen #define M4U_L11_P25_MFB_WDMA1 MTK_M4U_ID(SMI_L11_ID, 25) 176*812df545SZhengnan Chen #define M4U_L11_P26_RESERVE6 MTK_M4U_ID(SMI_L11_ID, 26) 177*812df545SZhengnan Chen #define M4U_L11_P27_RESERVE7 MTK_M4U_ID(SMI_L11_ID, 27) 178*812df545SZhengnan Chen #define M4U_L11_P28_RESERVE8 MTK_M4U_ID(SMI_L11_ID, 28) 179*812df545SZhengnan Chen 180*812df545SZhengnan Chen /* Larb12: null */ 181*812df545SZhengnan Chen 182*812df545SZhengnan Chen /* Larb13 -- cam */ 183*812df545SZhengnan Chen #define M4U_L13_P0_MRAWI MTK_M4U_ID(SMI_L13_ID, 0) 184*812df545SZhengnan Chen #define M4U_L13_P1_MRAWO_0 MTK_M4U_ID(SMI_L13_ID, 1) 185*812df545SZhengnan Chen #define M4U_L13_P2_MRAWO_1 MTK_M4U_ID(SMI_L13_ID, 2) 186*812df545SZhengnan Chen #define M4U_L13_P3_CAMSV_1 MTK_M4U_ID(SMI_L13_ID, 3) 187*812df545SZhengnan Chen #define M4U_L13_P4_CAMSV_2 MTK_M4U_ID(SMI_L13_ID, 4) 188*812df545SZhengnan Chen #define M4U_L13_P5_CAMSV_3 MTK_M4U_ID(SMI_L13_ID, 5) 189*812df545SZhengnan Chen #define M4U_L13_P6_CAMSV_4 MTK_M4U_ID(SMI_L13_ID, 6) 190*812df545SZhengnan Chen #define M4U_L13_P7_CAMSV_5 MTK_M4U_ID(SMI_L13_ID, 7) 191*812df545SZhengnan Chen #define M4U_L13_P8_CAMSV_6 MTK_M4U_ID(SMI_L13_ID, 8) 192*812df545SZhengnan Chen #define M4U_L13_P9_CCUI MTK_M4U_ID(SMI_L13_ID, 9) 193*812df545SZhengnan Chen #define M4U_L13_P10_CCUO MTK_M4U_ID(SMI_L13_ID, 10) 194*812df545SZhengnan Chen #define M4U_L13_P11_FAKE MTK_M4U_ID(SMI_L13_ID, 11) 195*812df545SZhengnan Chen #define M4U_L13_P12_PDAI_0 MTK_M4U_ID(SMI_L13_ID, 12) 196*812df545SZhengnan Chen #define M4U_L13_P13_PDAI_1 MTK_M4U_ID(SMI_L13_ID, 13) 197*812df545SZhengnan Chen #define M4U_L13_P14_PDAO MTK_M4U_ID(SMI_L13_ID, 14) 198*812df545SZhengnan Chen 199*812df545SZhengnan Chen /* Larb14 -- cam */ 200*812df545SZhengnan Chen #define M4U_L14_P0_RESERVE MTK_M4U_ID(SMI_L14_ID, 0) 201*812df545SZhengnan Chen #define M4U_L14_P1_RESERVE MTK_M4U_ID(SMI_L14_ID, 1) 202*812df545SZhengnan Chen #define M4U_L14_P2_RESERVE MTK_M4U_ID(SMI_L14_ID, 2) 203*812df545SZhengnan Chen #define M4U_L14_P3_CAMSV_0 MTK_M4U_ID(SMI_L14_ID, 3) 204*812df545SZhengnan Chen #define M4U_L14_P4_CCUI MTK_M4U_ID(SMI_L14_ID, 4) 205*812df545SZhengnan Chen #define M4U_L14_P5_CCUO MTK_M4U_ID(SMI_L14_ID, 5) 206*812df545SZhengnan Chen #define M4U_L14_P6_CAMSV_7 MTK_M4U_ID(SMI_L14_ID, 6) 207*812df545SZhengnan Chen #define M4U_L14_P7_CAMSV_8 MTK_M4U_ID(SMI_L14_ID, 7) 208*812df545SZhengnan Chen #define M4U_L14_P8_CAMSV_9 MTK_M4U_ID(SMI_L14_ID, 8) 209*812df545SZhengnan Chen #define M4U_L14_P9_CAMSV_10 MTK_M4U_ID(SMI_L14_ID, 9) 210*812df545SZhengnan Chen 211*812df545SZhengnan Chen /* Larb15: null */ 212*812df545SZhengnan Chen 213*812df545SZhengnan Chen /* Larb16 -- cam */ 214*812df545SZhengnan Chen #define M4U_L16_P0_IMGO_R1_A MTK_M4U_ID(SMI_L16_ID, 0) 215*812df545SZhengnan Chen #define M4U_L16_P1_RRZO_R1_A MTK_M4U_ID(SMI_L16_ID, 1) 216*812df545SZhengnan Chen #define M4U_L16_P2_CQI_R1_A MTK_M4U_ID(SMI_L16_ID, 2) 217*812df545SZhengnan Chen #define M4U_L16_P3_BPCI_R1_A MTK_M4U_ID(SMI_L16_ID, 3) 218*812df545SZhengnan Chen #define M4U_L16_P4_YUVO_R1_A MTK_M4U_ID(SMI_L16_ID, 4) 219*812df545SZhengnan Chen #define M4U_L16_P5_UFDI_R2_A MTK_M4U_ID(SMI_L16_ID, 5) 220*812df545SZhengnan Chen #define M4U_L16_P6_RAWI_R2_A MTK_M4U_ID(SMI_L16_ID, 6) 221*812df545SZhengnan Chen #define M4U_L16_P7_RAWI_R3_A MTK_M4U_ID(SMI_L16_ID, 7) 222*812df545SZhengnan Chen #define M4U_L16_P8_AAO_R1_A MTK_M4U_ID(SMI_L16_ID, 8) 223*812df545SZhengnan Chen #define M4U_L16_P9_AFO_R1_A MTK_M4U_ID(SMI_L16_ID, 9) 224*812df545SZhengnan Chen #define M4U_L16_P10_FLKO_R1_A MTK_M4U_ID(SMI_L16_ID, 10) 225*812df545SZhengnan Chen #define M4U_L16_P11_LCESO_R1_A MTK_M4U_ID(SMI_L16_ID, 11) 226*812df545SZhengnan Chen #define M4U_L16_P12_CRZO_R1_A MTK_M4U_ID(SMI_L16_ID, 12) 227*812df545SZhengnan Chen #define M4U_L16_P13_LTMSO_R1_A MTK_M4U_ID(SMI_L16_ID, 13) 228*812df545SZhengnan Chen #define M4U_L16_P14_RSSO_R1_A MTK_M4U_ID(SMI_L16_ID, 14) 229*812df545SZhengnan Chen #define M4U_L16_P15_AAHO_R1_A MTK_M4U_ID(SMI_L16_ID, 15) 230*812df545SZhengnan Chen #define M4U_L16_P16_LSCI_R1_A MTK_M4U_ID(SMI_L16_ID, 16) 231*812df545SZhengnan Chen 232*812df545SZhengnan Chen /* Larb17 -- cam */ 233*812df545SZhengnan Chen #define M4U_L17_P0_IMGO_R1_B MTK_M4U_ID(SMI_L17_ID, 0) 234*812df545SZhengnan Chen #define M4U_L17_P1_RRZO_R1_B MTK_M4U_ID(SMI_L17_ID, 1) 235*812df545SZhengnan Chen #define M4U_L17_P2_CQI_R1_B MTK_M4U_ID(SMI_L17_ID, 2) 236*812df545SZhengnan Chen #define M4U_L17_P3_BPCI_R1_B MTK_M4U_ID(SMI_L17_ID, 3) 237*812df545SZhengnan Chen #define M4U_L17_P4_YUVO_R1_B MTK_M4U_ID(SMI_L17_ID, 4) 238*812df545SZhengnan Chen #define M4U_L17_P5_UFDI_R2_B MTK_M4U_ID(SMI_L17_ID, 5) 239*812df545SZhengnan Chen #define M4U_L17_P6_RAWI_R2_B MTK_M4U_ID(SMI_L17_ID, 6) 240*812df545SZhengnan Chen #define M4U_L17_P7_RAWI_R3_B MTK_M4U_ID(SMI_L17_ID, 7) 241*812df545SZhengnan Chen #define M4U_L17_P8_AAO_R1_B MTK_M4U_ID(SMI_L17_ID, 8) 242*812df545SZhengnan Chen #define M4U_L17_P9_AFO_R1_B MTK_M4U_ID(SMI_L17_ID, 9) 243*812df545SZhengnan Chen #define M4U_L17_P10_FLKO_R1_B MTK_M4U_ID(SMI_L17_ID, 10) 244*812df545SZhengnan Chen #define M4U_L17_P11_LCESO_R1_B MTK_M4U_ID(SMI_L17_ID, 11) 245*812df545SZhengnan Chen #define M4U_L17_P12_CRZO_R1_B MTK_M4U_ID(SMI_L17_ID, 12) 246*812df545SZhengnan Chen #define M4U_L17_P13_LTMSO_R1_B MTK_M4U_ID(SMI_L17_ID, 13) 247*812df545SZhengnan Chen #define M4U_L17_P14_RSSO_R1_B MTK_M4U_ID(SMI_L17_ID, 14) 248*812df545SZhengnan Chen #define M4U_L17_P15_AAHO_R1_B MTK_M4U_ID(SMI_L17_ID, 15) 249*812df545SZhengnan Chen #define M4U_L17_P16_LSCI_R1_B MTK_M4U_ID(SMI_L17_ID, 16) 250*812df545SZhengnan Chen 251*812df545SZhengnan Chen /* Larb19 -- ipesys */ 252*812df545SZhengnan Chen #define M4U_L19_P0_DVS_RDMA MTK_M4U_ID(SMI_L19_ID, 0) 253*812df545SZhengnan Chen #define M4U_L19_P1_DVS_WDMA MTK_M4U_ID(SMI_L19_ID, 1) 254*812df545SZhengnan Chen #define M4U_L19_P2_DVP_RDMA MTK_M4U_ID(SMI_L19_ID, 2) 255*812df545SZhengnan Chen #define M4U_L19_P3_DVP_WDMA MTK_M4U_ID(SMI_L19_ID, 3) 256*812df545SZhengnan Chen 257*812df545SZhengnan Chen /* Larb20 -- ipesys */ 258*812df545SZhengnan Chen #define M4U_L20_P0_FDVT_RDA_0 MTK_M4U_ID(SMI_L20_ID, 0) 259*812df545SZhengnan Chen #define M4U_L20_P1_FDVT_RDB_0 MTK_M4U_ID(SMI_L20_ID, 1) 260*812df545SZhengnan Chen #define M4U_L20_P2_FDVT_WRA_0 MTK_M4U_ID(SMI_L20_ID, 2) 261*812df545SZhengnan Chen #define M4U_L20_P3_FDVT_WRB_0 MTK_M4U_ID(SMI_L20_ID, 3) 262*812df545SZhengnan Chen #define M4U_L20_P4_RSC_RDMA MTK_M4U_ID(SMI_L20_ID, 4) 263*812df545SZhengnan Chen #define M4U_L20_P5_RSC_WDMA MTK_M4U_ID(SMI_L20_ID, 5) 264*812df545SZhengnan Chen 265*812df545SZhengnan Chen /* fake larb21 for gce */ 266*812df545SZhengnan Chen #define M4U_L21_GCE_DM MTK_M4U_ID(21, 0) 267*812df545SZhengnan Chen #define M4U_L21_GCE_MM MTK_M4U_ID(21, 1) 268*812df545SZhengnan Chen 269*812df545SZhengnan Chen /* fake larb & port for svp and dual svp and wfd */ 270*812df545SZhengnan Chen #define M4U_PORT_SVP_HEAP MTK_M4U_ID(22, 0) 271*812df545SZhengnan Chen #define M4U_PORT_DUAL_SVP_HEAP MTK_M4U_ID(22, 1) 272*812df545SZhengnan Chen #define M4U_PORT_WFD_HEAP MTK_M4U_ID(22, 2) 273*812df545SZhengnan Chen 274*812df545SZhengnan Chen /* fake larb0 for apu */ 275*812df545SZhengnan Chen #define M4U_L0_APU_DATA MTK_M4U_ID(0, 0) 276*812df545SZhengnan Chen #define M4U_L0_APU_CODE MTK_M4U_ID(0, 1) 277*812df545SZhengnan Chen #define M4U_L0_APU_SECURE MTK_M4U_ID(0, 2) 278*812df545SZhengnan Chen #define M4U_L0_APU_VLM MTK_M4U_ID(0, 3) 279*812df545SZhengnan Chen 280*812df545SZhengnan Chen /* infra/peri */ 281*812df545SZhengnan Chen #define IFR_IOMMU_PORT_PCIE_0 MTK_IFAIOMMU_PERI_ID(0, 26) 282*812df545SZhengnan Chen 283*812df545SZhengnan Chen #endif 284