| /freebsd/sys/dev/mii/ |
| H A D | miidevs | 3 /*-
35 * For a complete list see http://standards-oui.ieee.org/
39 * IEEE 802.3u-1995, subclause 22.2.4.3.1, figure 22-12, depicts the right
40 * mapping; the bit positions are defined in IEEE 802-1990, figure 5.2.
41 * (There is a formal 802.3 interpretation, number 1-07/98 of July 09 1998,
69 oui PMCSIERRA 0x00e004 PMC-Sierra
110 oui xxPMCSIERRA 0x0009c0 PMC-Sierra
111 oui xxPMCSIERRA2 0x009057 PMC-Sierra
121 model AGERE ET1011 0x0001 ET1011 10/100/1000baseT PHY
122 model AGERE ET1011C 0x0004 ET1011C 10/100/1000baseT PHY
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| H A D | bmtphyreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
48 #define AUX_CTL_FEF_EN 0x0020 /* far-end fault enable */
51 #define AUX_STS_FX_MODE 0x0400 /* 100base-FX mode (strap pin) */
53 #define AUX_STS_100BASE_LINK 0x0100 /* 1 = 100base link */
59 #define AUX_STS_TXERROR 0x0004 /* Tx error detected */
63 #define MII_BMTPHY_RXERROR_CTR 0x12 /* 100base-X Rx error counter */
66 #define MII_BMTPHY_FCS_CTR 0x13 /* 100base-X false carrier counter */
69 #define MII_BMTPHY_DIS_CTR 0x14 /* 100base-X disconnect counter */
81 #define AUX_CSR_ANEG 0x0008 /* auto-negotiation activated */
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| H A D | rgephyreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
60 #define RGEPHY_S100 RGEPHY_BMCR_SPD0 /* 100mpbs */
64 #define RGEPHY_BMSR_100T4 0x8000 /* 100 base T4 capable */
65 #define RGEPHY_BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */
66 #define RGEPHY_BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */
67 #define RGEPHY_BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */
68 #define RGEPHY_BMSR_10THDX 0x0800 /* 10 base T half duplex capable */
69 #define RGEPHY_BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | ti,dp83869.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
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| H A D | ethernet-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
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| H A D | qcom,qca807x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Robert Marko <robert.marko@sartura.hr>
15 IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and
16 1000BASE-T PHY-s.
21 Both models have a combo port that supports 1000BASE-X and
22 100BASE-FX fiber.
25 output only pins that natively drive LED-s for up to 2 attached
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| H A D | ti,dp83867.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
21 The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet
34 nvmem-cells:
40 nvmem-cell-names:
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| /freebsd/sys/contrib/device-tree/Bindings/net/dsa/ |
| H A D | nxp,sja1105.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...] |
| /freebsd/share/man/man4/ |
| H A D | bce.4 | 1 .\" Copyright (c) 2006-2014 QLogic Corporation
35 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
62 .Bl -item -offset indent -compact
72 10/100/1000Mbps operation in full-duplex mode
74 10/100Mbps operation in half-duplex mode
80 .Bl -tag -width ".Cm 10baseT/UTP"
92 .Cm full-duplex
94 .Cm half-duplex
96 .It Cm 100baseTX
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| H A D | aue.4 | 2 .\" SPDX-License-Identifier: BSD-4-Clause
18 .\" 4. Neither the name of the author nor the names of any co-contributors
44 .Bd -ragged -offset indent
56 .Bd -literal -offset indent
66 will operate at 100Base-TX and full-duplex.
68 The Pegasus contains a 10/100
72 100Mbps peripherals, the existing USB standard specifies a maximum
75 achieve 100Mbps speeds with these devices.
77 The Pegasus supports a 64-bit multicast hash table, single perfect
85 .Bl -tag -width xxxxxxxxxxxxxxxxxxxx
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| /titanic_50/usr/src/uts/common/io/mxfe/ |
| H A D | mxfe.h | 15 * 3. Neither the name of the author nor the names of any co-contributors
71 #define PCI_CMD_MWIE 0x0010 /* memory write-invalidate enable */
80 #define CSR_RDB 0x18 /* Receive descriptor base address */
81 #define CSR_TDB 0x20 /* Transmit descriptor base address */
88 #define CSR_TSTAT 0x60 /* 10Base-T status */
90 #define CSR_TCTL 0x70 /* 10Base-T control */
94 #define CSR_TXBR 0x9c /* Transmit burst counter/time-out register */
103 #define PAR_MWIE 0x01000000U /* PCI memory-write-invalidate */
104 #define PAR_MRLE 0x00800000U /* PCI memory-read-line */
105 #define PAR_MRME 0x00200000U /* PCI memory-read-multiple */
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| /titanic_50/usr/src/uts/common/io/hme/ |
| H A D | hme_phy.h | 29 /* DP83840 - 10/100 Mbps Physical layer from National semiconductor */
32 * MII supports a 16-bit register stack of upto 32, addressable through the
39 #define HME_PHY_ANAR 04 /* Auto-Negotiation Advertisement Register */
40 #define HME_PHY_ANLPAR 05 /* Auto-Negotiation Link Partner Ability Reg */
41 #define HME_PHY_ANER 06 /* Auto-Negotiation Expansion Register */
43 /* Registers 7-15 are reserved for future assignments by MII working group */
46 /* Registers 16-17 are reserved for future assignment by Vendor */
61 /* Registers 29-31 are reserved for future assignment by Vendor */
68 #define HME_PHY_BTXPC 31 /* BASE-TX Phy control Register */
75 #define PHY_BMCR_100M (1 << 13) /* Speed selection, 1=100Mbps */
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| /titanic_50/usr/src/uts/sun/io/eri/ |
| H A D | eri_phy.h | 23 * Copyright (c) 1999-2000 by Sun Microsystems, Inc.
37 * MII supports a 16-bit register stack of upto 32, addressable through the
44 #define ERI_PHY_ANAR 04 /* Auto-Negotiation Advertisement Register */
45 #define ERI_PHY_ANLPAR 05 /* Auto-Negotiation Link Partner Ability Reg */
46 #define ERI_PHY_ANER 06 /* Auto-Negotiation Expansion Register */
48 /* Registers 7-15 are reserved for future assignments by MII working group */
51 /* Registers 16-17 are reserved for future assignment by Vendor */
66 /* Registers 29-31 are reserved for future assignment by Vendor */
75 #define PHY_BMCR_100M (1 << 13) /* Speed selection, 1=100Mbps */
82 #define PHY_BMCR_RES1 (0x7f << 0) /* 0-6 Reserved */
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| /titanic_50/usr/src/grub/grub-0.97/netboot/ |
| H A D | sundance.c | 3 * sundance.c -- Etherboot device driver for the Sundance ST201 "Alta".
4 * Written 2002-2002 by Timothy Legge <tlegge@rogers.com>
22 * Written 1999-2002 by Donald Becker
28 * Linux Driver Version LK1.09a, 10-Jul-2003 (2.4.25)
32 * v1.1 01-01-2003 timlegge Initial implementation
33 * v1.7 04-10-2003 timlegge Transfers Linux Kernel (30 sec)
34 * v1.8 04-13-2003 timlegge Fix multiple transmission bug
35 * v1.9 08-19-2003 timlegge Support Multicast
36 * v1.10 01-17-2004 timlegge Initial driver output cleanup
37 * v1.11 03-21-2004 timlegge Remove unused variables
[all …]
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| H A D | 3c90x.c | 2 * 3c90x.c -- This file implements the 3c90x driver for etherboot. Written
9 * This program may be re-distributed in source or binary form, modified,
13 * documentation of any binary-only distributions. This program is distributed
18 * --------
21 * the 3c905B-TX card, as well as with some assistance from the 3c59x
27 * v0.10 1-26-1998 GRB Initial implementation.
28 * v0.90 1-27-1998 GRB System works.
29 * v1.00pre1 2-11-1998 GRB Got prom boot issue fixed.
30 * v2.0 9-24-1999 SCS Modified for 3c905 (from 3c905b code)
31 * Re-wrote poll and transmit for
[all …]
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| H A D | e1000_hw.h | 4 Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
138 e1000_igp_cable_length_100 = 100,
291 /* MAC decode size is 128K - This is the size of BAR0 */
298 #define SPEED_100 100
309 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
311 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
355 * E1000_RAR_ENTRIES - 1 multicast addresses.
379 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
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| H A D | tlan.c | 9 * tlan.c -- Etherboot device driver for the Texas Instruments ThunderLAN
10 * Written 2003-2003 by Timothy Legge <tlegge@rogers.com>
31 * (C) 1997-1998 Caldera, Inc.
33 * (C) 1999-2001 Torben Mathiasen
38 * v1.0 07-08-2003 timlegge Initial not quite working version
39 * v1.1 07-27-2003 timlegge Sync 5.0 and 5.1 versions
40 * v1.2 08-19-2003 timlegge Implement Multicast Support
41 * v1.3 08-23-2003 timlegge Fix the transmit Function
42 * v1.4 01-17-2004 timlegge Initial driver output cleanup
44 * Indent Options: indent -kr -i8
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | microchip,sparx5-serdes.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Daniel Machon <daniel.machon@microchip.com>
22 * Rx built-in fault detector (loss-of-lock/loss-of-signal)
23 * Adjustable tx de-emphasis (FFE)
24 * Tx output amplitude control
32 The SERDES6G is a high-speed SERDES interface, which can operate at
[all …]
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| /titanic_50/usr/src/man/man7d/ |
| H A D | dmfe.7d | 8 dmfe \- Davicom Fast Ethernet driver for Davicom DM9102A
18 The \fBdmfe\fR Ethernet device provides 100Base-TX networking interfaces using
28 The 100Base-TX standard specifies an auto-negotiation protocol to automatically
30 performing auto-negotiation with the remote-end of the link (link partner) and
33 also supports a forced-mode of operation under which the driver selects the
38 The \fB/dev/dmfe\fR cloning character-special device is used to access all
47 initialized on first attach and de-initialized (stopped) at last detach.
56 Maximum SDU is 1500 (ETHERMTU - defined in \fBsys/ethernet.h\fR).
80 The sap length value is -2, meaning the physical address component is
81 followed immediately by a 2-byte sap component within the DLSAP address.
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| H A D | hme.7d | 8 hme \- SUNW,hme Fast-Ethernet device driver
18 The \fBSUNW,hme\fR Fast-Ethernet driver is a multi-threaded, loadable,
20 Provider Interface, \fBdlpi\fR(7P), over a \fBSUNW,hme\fR Fast-Ethernet
21 controller. The motherboard and add-in SBus \fBSUNW,hme\fR controllers of
30 provides 100Base-TX networking interfaces using SUN's \fBFEPS ASIC\fR and an
33 Transceiver which connects to a \fBRJ-45\fR connector. In addition to the RJ-45
37 may use any physical media (copper or fiber) specified in the 100Base-TX
42 The 100Base-TX standard specifies an "auto-negotiation" protocol to
44 is capable of doing "auto-negotiation" with the remote-end of the link (Link
47 also supports \fBforced-mode\fR of operation where the driver can select the
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| H A D | sfe.7d | 8 sfe \- SiS900 series Fast Ethernet device driver
18 The \fBsfe\fR driver is a loadable, clonable, GLD-based STREAMS driver
53 SAP length is -2. The 6-byte physical address is followed immediately by a
54 2-byte SAP.
66 Broadcast address is the 6-byte Ethernet broadcast address
88 Enables the 100 Base TX full-duplex link option. (This is generally the fastest
100 Enables the 100 Base TX half-duplex link option. (Typically used when the link
101 partner is a 100 Mbps hub.)
111 Enables the 10 Base-T full-duplex link option. (This less-frequently used mode
122 Enables the 10 Base-T half-duplex link option. (This is the fall-back when no
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| /freebsd/sys/dev/igc/ |
| H A D | igc_defines.h | 1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
127 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
128 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
214 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
216 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
219 #define IGC_CTRL_SPD_100 0x00000100 /* Force 100Mb */
251 #define IGC_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
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| /freebsd/sys/net/ |
| H A D | sff8472.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2013 George V. Neville-Neil
33 * The following set of constants are from Document SFF-8472
42 * Base Address 0xa0 (Identification Data)
43 * 0-95 Serial ID Defined by SFP MSA
44 * 96-127 Vendor Specific Data
45 * 128-255 Reserved
47 * Base Address 0xa2 (Diagnostic Data)
48 * 0-55 Alarm and Warning Thresholds
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| /freebsd/sys/dev/e1000/ |
| H A D | e1000_defines.h | 2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
172 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
173 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
261 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
263 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
266 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
331 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
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| /titanic_50/usr/src/uts/common/io/e1000api/ |
| H A D | e1000_defines.h | 3 Copyright (c) 2001-2015, Intel Corporation
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
173 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
174 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
262 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
264 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
267 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
331 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
340 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
[all …]
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