Home
last modified time | relevance | path

Searched +full:1 +full:- +full:clock (Results 1 – 25 of 1101) sorted by relevance

12345678910>>...45

/linux/arch/arm/boot/dts/ti/omap/
H A Dam33xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for AM33xx clock data
8 sys_clkin_ck: clock-sys-clkin-22@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <22>;
17 adc_tsc_fck: clock-adc-tsc-fck {
18 #clock-cells = <0>;
19 compatible = "fixed-factor-clock";
[all …]
H A Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for AM43xx clock data
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
[all …]
H A Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP5 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
[all …]
H A Ddm814x-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <1>;
11 compatible = "ti,dm814-adpll-s-clock";
14 clock-names = "clkinp", "clkinpulow", "clkinphif";
15 clock-output-names = "481c5040.adpll.dcoclkldo",
22 #clock-cells = <1>;
23 compatible = "ti,dm814-adpll-lj-clock";
26 clock-names = "clkinp", "clkinpulow";
27 clock-output-names = "481c5080.adpll.dcoclkldo",
33 #clock-cells = <1>;
[all …]
H A Domap3xxx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP3 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
25 ti,bit-shift = <6>;
[all …]
H A Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP4 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
[all …]
H A Domap36xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP34xx/OMAP36xx clock data
8 clock@a00 {
11 #clock-cells = <2>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2@0 {
17 #clock-cells = <0>;
18 compatible = "ti,composite-no-wait-gate-clock";
19 clock-output-names = "ssi_ssr_gate_fck_3430es2";
[all …]
H A Domap34xx-omap36xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP34XX/OMAP36XX clock data
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <1>;
16 clock@a14 {
19 #clock-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
[all …]
H A Ddm816x-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 #clock-cells = <1>;
6 compatible = "ti,dm816-fapll-clock";
9 clock-indices = <1>, <2>, <3>, <4>, <5>,
11 clock-output-names = "main_pll_clk1",
21 #clock-cells = <1>;
22 compatible = "ti,dm816-fapll-clock";
25 clock-indices = <1>, <2>, <3>, <4>;
26 clock-output-names = "ddr_pll_clk1",
33 #clock-cells = <1>;
[all …]
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <3>;
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
20 clock-mult = <1>;
21 clock-div = <5>;
[all …]
H A Domap3430es1-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP3430 ES1 clock data
9 #clock-cells = <0>;
10 compatible = "ti,wait-gate-clock";
13 ti,bit-shift = <0>;
17 #clock-cells = <0>;
18 compatible = "ti,divider-clock";
20 ti,max-div = <7>;
22 ti,index-starts-at-one;
26 #clock-cells = <0>;
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt8195-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8195-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Functional Clock Controller for MT8195
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The clock architecture in Mediatek like below
14 PLLs -->
15 dividers -->
17 -->
[all …]
H A Dmediatek,mt8192-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8192-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Functional Clock Controller for MT8192
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The Mediatek functional clock controller provides various clocks on MT8192.
18 - enum:
19 - mediatek,mt8192-scp_adsp
20 - mediatek,mt8192-imp_iic_wrap_c
[all …]
H A Dsamsung,exynos5260-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5260-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5260 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
[all …]
H A Dsilabs,si5351.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/silabs,si5351.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Silicon Labs Si5351A/B/C programmable I2C clock generators
10 The Silicon Labs Si5351A/B/C are programmable I2C clock generators with up to
11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
12 output clocks are accessible. The internal structure of the clock generators
13 can be found in [1].
15 [1] Si5351A/B/C Data Sheet
[all …]
/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-clock.dtsi4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/clock/bcm-sr.h>
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
38 clock-frequency = <50000000>;
42 #clock-cells = <0>;
43 compatible = "fixed-factor-clock";
45 clock-div = <2>;
46 clock-mult = <1>;
49 genpll0: genpll0@1d104 {
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for Keystone 2 clock tree
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #clock-cells = <0>;
15 compatible = "ti,keystone,pll-mux-clock";
18 bit-shift = <23>;
19 bit-mask = <1>;
20 clock-output-names = "mainmuxclk";
[all …]
/linux/arch/arm/boot/dts/hisilicon/
H A Dhi3620.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012-2013 HiSilicon Ltd.
6 * Copyright (C) 2012-2013 Linaro Ltd.
11 #include <dt-bindings/clock/hi3620-clock.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
29 clock-output-names = "apb_pclk";
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-img.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019-2021 NXP
6 img_ipg_clk: clock-img-ipg {
7 compatible = "fixed-clock";
8 #clock-cells = <0>;
9 clock-frequency = <200000000>;
10 clock-output-names = "img_ipg_clk";
13 img_pxl_clk: clock-img-pxl {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
[all …]
H A Dimx8-ss-audio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-clock.h>
8 #include <dt-bindings/clock/imx8-lpcg.h>
9 #include <dt-bindings/dma/fsl-edma.h>
10 #include <dt-bindings/firmware/imx/rsrc.h>
12 audio_ipg_clk: clock-audio-ipg {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <120000000>;
[all …]
H A Dimx8-ss-dma.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/dma/fsl-edma.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
11 dma_ipg_clk: clock-dma-ipg {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <120000000>;
15 clock-output-names = "dma_ipg_clk";
[all …]
/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC
6 #include <dt-bindings/gpio/gpio.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
18 L2: cache-controller {
19 compatible = "arm,l210-cache";
21 interrupt-parent = <&vica>;
23 cache-unified;
24 cache-level = <2>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos4.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
19 #include <dt-bindings/clock/exynos4.h>
20 #include <dt-bindings/clock/exynos-audss-clk.h>
21 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/interrupt-controller/irq.h>
25 interrupt-parent = <&gic>;
26 #address-cells = <1>;
27 #size-cells = <1>;
[all …]
H A Dexynos5410.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5410.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
35 compatible = "arm,cortex-a15";
37 clock-frequency = <1600000000>;
40 cpu1: cpu@1 {
[all …]
H A Dexynos5250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include <dt-bindings/clock/exynos5250.h>
19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
46 #address-cells = <1>;
47 #size-cells = <0>;
49 cpu-map {
62 compatible = "arm,cortex-a15";
64 clocks = <&clock CLK_ARM_CLK>;
65 clock-names = "cpu";
[all …]

12345678910>>...45