Lines Matching +full:1 +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP3430 ES1 clock data
9 #clock-cells = <0>;
10 compatible = "ti,wait-gate-clock";
13 ti,bit-shift = <0>;
17 #clock-cells = <0>;
18 compatible = "ti,divider-clock";
20 ti,max-div = <7>;
22 ti,index-starts-at-one;
26 #clock-cells = <0>;
27 compatible = "fixed-factor-clock";
29 clock-mult = <1>;
30 clock-div = <1>;
34 #clock-cells = <0>;
35 compatible = "ti,wait-gate-clock";
38 ti,bit-shift = <1>;
42 #clock-cells = <0>;
43 compatible = "ti,wait-gate-clock";
46 ti,bit-shift = <2>;
49 clock@a00 {
52 #clock-cells = <2>;
53 #address-cells = <1>;
54 #size-cells = <0>;
56 d2d_26m_fck: clock-d2d-26m-fck@3 {
58 #clock-cells = <0>;
59 compatible = "ti,wait-gate-clock";
60 clock-output-names = "d2d_26m_fck";
64 fshostusb_fck: clock-fshostusb-fck@5 {
66 #clock-cells = <0>;
67 compatible = "ti,wait-gate-clock";
68 clock-output-names = "fshostusb_fck";
72 ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1@0 {
74 #clock-cells = <0>;
75 compatible = "ti,composite-no-wait-gate-clock";
76 clock-output-names = "ssi_ssr_gate_fck_3430es1";
81 clock@a40 {
84 #clock-cells = <2>;
85 #address-cells = <1>;
86 #size-cells = <0>;
88 ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1@8 {
90 #clock-cells = <0>;
91 compatible = "ti,composite-divider-clock";
92 clock-output-names = "ssi_ssr_div_fck_3430es1";
94 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
97 usb_l4_div_ick: clock-usb-l4-div-ick@4 {
99 #clock-cells = <0>;
100 compatible = "ti,composite-divider-clock";
101 clock-output-names = "usb_l4_div_ick";
103 ti,max-div = <1>;
104 ti,index-starts-at-one;
109 #clock-cells = <0>;
110 compatible = "ti,composite-clock";
115 #clock-cells = <0>;
116 compatible = "fixed-factor-clock";
118 clock-mult = <1>;
119 clock-div = <2>;
122 clock@a10 {
125 #clock-cells = <2>;
126 #address-cells = <1>;
127 #size-cells = <0>;
129 hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1@4 {
131 #clock-cells = <0>;
132 compatible = "ti,omap3-no-wait-interface-clock";
133 clock-output-names = "hsotgusb_ick_3430es1";
137 fac_ick: clock-fac-ick@8 {
139 #clock-cells = <0>;
140 compatible = "ti,omap3-interface-clock";
141 clock-output-names = "fac_ick";
145 ssi_ick: clock-ssi-ick-3430es1@0 {
147 #clock-cells = <0>;
148 compatible = "ti,omap3-no-wait-interface-clock";
149 clock-output-names = "ssi_ick_3430es1";
153 usb_l4_gate_ick: clock-usb-l4-gate-ick@5 {
155 #clock-cells = <0>;
156 compatible = "ti,composite-interface-clock";
157 clock-output-names = "usb_l4_gate_ick";
163 #clock-cells = <0>;
164 compatible = "fixed-factor-clock";
166 clock-mult = <1>;
167 clock-div = <1>;
171 #clock-cells = <0>;
172 compatible = "ti,composite-clock";
176 clock@e00 {
179 #clock-cells = <2>;
180 #address-cells = <1>;
181 #size-cells = <0>;
183 dss1_alwon_fck: clock-dss1-alwon-fck-3430es1@0 {
185 #clock-cells = <0>;
186 compatible = "ti,gate-clock";
187 clock-output-names = "dss1_alwon_fck_3430es1";
189 ti,set-rate-parent;
194 #clock-cells = <0>;
195 compatible = "ti,omap3-no-wait-interface-clock";
198 ti,bit-shift = <0>;