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/linux/drivers/comedi/drivers/
H A Dplx9080.h1 /* SPDX-License-Identifier: GPL-2.0+ */
26 * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
32 * Describes the format of a scatter-gather DMA descriptor for the PLX
33 * PCI 9080. All members are raw, little-endian register values that
37 * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0
40 * terminal count" bit, and a data transfer direction.
50 * Register Offsets and Bit Definitions
55 /* Local Address Space 1 Range Register */
58 #define PLX_LASRR_IO BIT(0) /* Map to: 1=I/O, 0=Mem */
59 #define PLX_LASRR_MLOC_ANY32 (BIT(1) * 0) /* Locate anywhere in 32 bit */
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H A Dni_at_ao.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Driver for NI AT-AO-6/10 boards
6 * COMEDI - Linux Control and Measurement Device Interface
12 * Description: National Instruments AT-AO-6/10
13 * Devices: [National Instruments] AT-AO-6 (at-ao-6), AT-AO-10 (at-ao-10)
19 * [0] - I/O port base address
20 * [1] - IRQ (unused)
21 * [2] - DMA (unused)
22 * [3] - analog output range, set by jumpers on hardware
23 * 0 for -10 to 10V bipolar
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/linux/drivers/net/ethernet/marvell/
H A Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
39 PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
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H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define PCI_VPD_ROM_SZ 7L<<14 /* VPD ROM size 0=256, 1=512, ... */
16 #define PCI_REV_DESC 1<<2 /* Reverse Descriptor bytes */
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
136 CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
137 CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
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/linux/drivers/net/wireless/ath/ath10k/
H A Drx_desc.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
14 RX_ATTENTION_FLAGS_FIRST_MPDU = BIT(0),
15 RX_ATTENTION_FLAGS_LAST_MPDU = BIT(1),
16 RX_ATTENTION_FLAGS_MCAST_BCAST = BIT(2),
17 RX_ATTENTION_FLAGS_PEER_IDX_INVALID = BIT(3),
18 RX_ATTENTION_FLAGS_PEER_IDX_TIMEOUT = BIT(4),
19 RX_ATTENTION_FLAGS_POWER_MGMT = BIT(5),
20 RX_ATTENTION_FLAGS_NON_QOS = BIT(6),
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/linux/drivers/media/platform/samsung/s3c-camif/
H A Dcamif-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include "camif-core.h"
15 #include <media/drv-intf/s3c_camif.h>
19 * id = 0 - codec (FIMC C), 1 - preview (FIMC P).
24 #define CISRCFMT_ITU601_8BIT BIT(31)
27 #define CISRCFMT_ORDER422_YCRYCB (1 << 14)
35 #define CIWDOFST_WINOFSEN BIT(31)
36 #define CIWDOFST_CLROVCOFIY BIT(30)
37 #define CIWDOFST_CLROVRLB_PR BIT(28)
38 /* #define CIWDOFST_CLROVPRFIY BIT(27) */
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/linux/drivers/usb/cdns3/
H A Dcdns3-gadget.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2018-2019 Cadence.
6 * Copyright (C) 2017-2018 NXP
15 #include <linux/dma-direction.h>
18 * USBSS-DEV register interface.
23 * struct cdns3_usb_regs - device controller registers.
43 * @usb_cap1: Capability 1.
49 * @usb_cpkt1: Custom Packet 1.
53 * @buf_addr: Address for On-chip Buffer operations.
54 * @buf_data: Data for On-chip Buffer operations.
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/linux/drivers/net/wireless/ath/ath12k/
H A Drx_desc.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
27 #define RX_MPDU_START_INFO0_FLOW_ID_TOEPLITZ BIT(7)
28 #define RX_MPDU_START_INFO0_PKT_SEL_FP_UCAST_DATA BIT(8)
29 #define RX_MPDU_START_INFO0_PKT_SEL_FP_MCAST_DATA BIT(9)
30 #define RX_MPDU_START_INFO0_PKT_SEL_FP_CTRL_BAR BIT(10)
33 #define RX_MPDU_START_INFO0_MCAST_ECHO_DROP_EN BIT(17)
34 #define RX_MPDU_START_INFO0_WDS_LEARN_DETECT_EN BIT(18)
35 #define RX_MPDU_START_INFO0_INTRA_BSS_CHECK_EN BIT(19)
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/linux/drivers/tty/serial/
H A Dsh-sci.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 SCBRR, /* Bit Rate Register */
39 #define SCSMR_C_A BIT(7) /* Communication Mode */
40 #define SCSMR_CSYNC BIT(7) /* - Clocked synchronous mode */
41 #define SCSMR_ASYNC 0 /* - Asynchronous mode */
42 #define SCSMR_CHR BIT(6) /* 7-bit Character Length */
43 #define SCSMR_PE BIT(5) /* Parity Enable */
44 #define SCSMR_ODD BIT(4) /* Odd Parity */
45 #define SCSMR_STOP BIT(3) /* Stop Bit Length */
48 /* Serial Mode Register, SCIFA/SCIFB only bits */
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/linux/drivers/net/wireless/ath/ath11k/
H A Drx_desc.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
29 #define RX_DESC_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0)
89 #define RX_ATTENTION_INFO1_FIRST_MPDU BIT(0)
90 #define RX_ATTENTION_INFO1_RSVD_1A BIT(1)
91 #define RX_ATTENTION_INFO1_MCAST_BCAST BIT(2)
92 #define RX_ATTENTION_INFO1_AST_IDX_NOT_FOUND BIT(3)
93 #define RX_ATTENTION_INFO1_AST_IDX_TIMEDOUT BIT(4)
94 #define RX_ATTENTION_INFO1_POWER_MGMT BIT(5)
95 #define RX_ATTENTION_INFO1_NON_QOS BIT(6)
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H A Dhal_desc.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
53 HAL_PHYRX_DATA = 1 /* 0x1 */,
476 #define HAL_TLV_HDR_TAG GENMASK(9, 1)
489 #define RX_MPDU_DESC_INFO0_FRAG_FLAG BIT(20)
490 #define RX_MPDU_DESC_INFO0_MPDU_RETRY BIT(21)
491 #define RX_MPDU_DESC_INFO0_AMPDU_FLAG BIT(22)
492 #define RX_MPDU_DESC_INFO0_BAR_FRAME BIT(23)
493 #define RX_MPDU_DESC_INFO0_VALID_PN BIT(24)
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/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
12 /* [15:0] The Version register for H264 core (Read Only) */
18 #define TW5864_EMU_EN_DDR BIT(0)
19 /* Enable bit for Inter module */
20 #define TW5864_EMU_EN_ME BIT(1)
21 /* Enable bit for Sensor Interface module */
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/linux/include/media/i2c/
H A Dsaa7115.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 saa7115.h - definition for saa7111/3/4/5 inputs and frequency flags
16 #define SAA7115_COMPOSITE1 1
27 #define SAA7115_IPORT_ON 1
39 * Register 0x85 should set bit 0 to 0 (it's 1 b
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/linux/arch/m68k/include/asm/
H A Dmac_via.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * via them as are assorted bits and bobs - eg rtc, adb. The picture
7 * is a bit incomplete as the Mac documentation doesn't cover this well
51 * is the bit to flip screen buffers.
52 * 0=alternate, 1=main.
53 * on II,IIx,IIcx,IIci,IIfx this is a bit
54 * for Rev ID. 0=II,IIx, 1=IIcx,IIci,IIfx
59 * state-control line SEL" on all but IIfx
62 * this bit enables the "Overlay" address
65 * vector. 1=use overlay map.
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/linux/Documentation/bpf/
H A Dclassic_vs_extended.rst12 - Number of registers increase from 2 to 10:
15 new layout extends this to be 10 internal registers and a read-only frame
16 pointer. Since 64-bit CPUs are passing arguments to functions via registers
17 the number of args from eBPF program to in-kernel function is restricted
18 to 5 and one register is used to accept return value from an in-kernel
20 sparcv9/mips64 have 7 - 8 registers for arguments; x86_64 has 6 callee saved
25 64-bit architectures.
27 On 32-bit architectures JIT may map programs that use only 32-bit arithmetic
30 R0 - R5 are scratch registers and eBPF program needs spill/fill them if
31 necessary across calls. Note that there is only one eBPF program (== one
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/linux/Documentation/devicetree/bindings/hwmon/
H A Dmax6697.txt4 - compatible:
16 - reg: I2C address
20 - smbus-timeout-disable
23 - extended-range-enable
24 Only valid for MAX6581. Set to enable extended temperature range.
26 - beta-compensation-enable
27 Only valid for MAX6693 and MX6694. Set to enable beta compensation on
28 remote temperature channel 1.
30 - alert-mask
31 Alert bit mask. Alert disabled for bits set.
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/linux/drivers/net/ethernet/intel/idpf/
H A Dvirtchnl2_lan_desc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 VIRTCHNL2_TXDID_DATA = BIT(0),
17 VIRTCHNL2_TXDID_CTX = BIT(1),
18 /* TXDID bit 2 is reserved
19 * TXDID bit 3 is free for future use
20 * TXDID bit 4 is reserved
22 VIRTCHNL2_TXDID_FLEX_TSO_CTX = BIT(5),
23 /* TXDID bit 6 is reserved */
24 VIRTCHNL2_TXDID_FLEX_L2TAG1_L2TAG2 = BIT(7),
26 * TXDID bit 10 is reserved
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/linux/arch/mips/include/asm/octeon/
H A Dcvmx-fau.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
50 CVMX_FAU_OP_SIZE_16 = 1,
57 * bit will be set. Otherwise the value of the register before
61 uint64_t error:1;
67 * bit will be set. Otherwise the value of the register before
71 uint64_t error:1;
77 * bit will be set. Otherwise the value of the register before
81 uint64_t error:1;
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/linux/include/linux/bcma/
H A Dbcma_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
41 #define BCMA_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */
49 #define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
91 #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
92 #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
93 #define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1
103 #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
104 #define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */
105 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
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/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Drx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2025 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2015-2017 Intel Deutschland GmbH
10 /* API for pre-9000 hardware */
13 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1
26 * struct iwl_rx_phy_info - phy info
34 * @beacon_time_stamp: beacon at on-air rise
39 * @byte_count: frame's byte-count
70 * bits 0:3 - reserved
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/linux/include/media/drv-intf/
H A Dcx25840.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * cx25840.h - definition for cx25840/1/2/3 inputs
17 * only get mono.
31 /* Composite video inputs In1-In8 */
32 CX25840_COMPOSITE1 = 1,
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/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac1000.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
26 #define GMAC_INT_STATUS_PMT BIT(3)
27 #define GMAC_INT_STATUS_MMCIS BIT(4)
28 #define GMAC_INT_STATUS_MMCRIS BIT(5)
29 #define GMAC_INT_STATUS_MMCTIS BIT(6)
30 #define GMAC_INT_STATUS_MMCCSUM BIT(7)
31 #define GMAC_INT_STATUS_TSTAMP BIT(9)
32 #define GMAC_INT_STATUS_LPIIS BIT(10)
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/linux/include/linux/clk/
H A Dti.h1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <linux/clk-provider.h>
14 * struct clk_omap_reg - OMAP register declaration
16 * @bit: register bit offset
23 u8 bit; member
29 * struct dpll_data - DPLL registers and integration data
43 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
45 * @min_divider: minimum valid non-bypass divider value (actual)
46 * @max_divider: maximum valid non-bypass divider value (actual)
56 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
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/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_type_e610.h1 /* SPDX-License-Identifier: GPL-2.0 */
76 * using ixgbe_read_netlist_module, we need to account for the 2-word TLV
86 #define GL_FWSTS_EP_PF0 BIT(24)
87 #define GL_FWSTS_EP_PF1 BIT(25)
94 #define IXGBE_GL_MNG_FWSM_RECOVERY_M BIT(1)
95 #define IXGBE_GL_MNG_FWSM_ROLLBACK_M BIT(2)
100 #define IXGBE_GLNVM_FLA_LOCKED_M BIT(6)
104 #define IXGBE_SR_CTRL_WORD_VALID BIT(0)
105 #define IXGBE_SR_CTRL_WORD_OROM_BANK BIT(3)
106 #define IXGBE_SR_CTRL_WORD_NETLIST_BANK BIT(4)
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/linux/Documentation/input/devices/
H A Dsentelic.rst8 :Copyright: |copy| 2002-2011 Sentelic Corporation.
10 :Last update: Dec-07-2011
18 1. Set sample rate to 200;
26 Packet 1
27 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
28 BYTE |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------------|
29 1 |Y|X|y|x|1|M|R|L| 2 |X|X|X|X|X|X|X|X| 3 |Y|Y|Y|Y|Y|Y|Y|Y| 4 | | |B|F|W|W|W|W|
30 |---------------| |---------------| |---------------| |---------------|
32 Byte 1: Bit7 => Y overflow
34 Bit5 => Y sign bit
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