Lines Matching +full:1 +full:- +full:bit +full:- +full:only
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
26 #define GMAC_INT_STATUS_PMT BIT(3)
27 #define GMAC_INT_STATUS_MMCIS BIT(4)
28 #define GMAC_INT_STATUS_MMCRIS BIT(5)
29 #define GMAC_INT_STATUS_MMCTIS BIT(6)
30 #define GMAC_INT_STATUS_MMCCSUM BIT(7)
31 #define GMAC_INT_STATUS_TSTAMP BIT(9)
32 #define GMAC_INT_STATUS_LPIIS BIT(10)
36 #define GMAC_INT_DISABLE_RGMII BIT(0)
37 #define GMAC_INT_DISABLE_PCSLINK BIT(1)
38 #define GMAC_INT_DISABLE_PCSAN BIT(2)
39 #define GMAC_INT_DISABLE_PMT BIT(3)
40 #define GMAC_INT_DISABLE_TIMESTAMP BIT(9)
62 * For LPI control and status bit definitions, see common.h.
68 #define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
70 #define GMAC_ADDR_LOW(reg) ((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \
72 #define GMAC_MAX_PERFECT_ADDRESSES 1
78 #define GMAC_RGSMIIIS_LNKMODE BIT(0)
79 #define GMAC_RGSMIIIS_SPEED GENMASK(2, 1)
80 #define GMAC_RGSMIIIS_SPEED_SHIFT 1
81 #define GMAC_RGSMIIIS_LNKSTS BIT(3)
82 #define GMAC_RGSMIIIS_JABTO BIT(4)
83 #define GMAC_RGSMIIIS_FALSECARDET BIT(5)
84 #define GMAC_RGSMIIIS_SMIDRXS BIT(16)
105 #define GMAC_CONTROL_PS 0x00008000 /* Port Select 0:GMI 1:MII */
106 #define GMAC_CONTROL_FES 0x00004000 /* Speed 0:10 1:100 */
108 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
146 #define GMAC_DEBUG_TXSTSFSTS BIT(25) /* MTL TxStatus FIFO Full Status */
147 #define GMAC_DEBUG_TXFSTS BIT(24) /* MTL Tx FIFO Not Empty Status */
148 #define GMAC_DEBUG_TWCSTS BIT(22) /* MTL Tx FIFO Write Controller */
153 #define GMAC_DEBUG_TRCSTS_READ 1
156 #define GMAC_DEBUG_TXPAUSED BIT(19) /* MAC Transmitter in PAUSE */
161 #define GMAC_DEBUG_TFCSTS_WAIT 1
165 #define GMAC_DEBUG_TPESTS BIT(16)
166 #define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */
169 #define GMAC_DEBUG_RXFSTS_BT 1
175 #define GMAC_DEBUG_RRCSTS_RDATA 1
178 #define GMAC_DEBUG_RWCSTS BIT(4) /* MTL Rx FIFO Write Controller Active */
180 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)
181 #define GMAC_DEBUG_RFCFCSTS_SHIFT 1
183 #define GMAC_DEBUG_RPESTS BIT(0)
185 /*--- DMA BLOCK defines ---*/
196 double_ratio = 0x00004000, /* 2:1 */
197 triple_ratio = 0x00008000, /* 3:1 */
198 quadruple_ratio = 0x0000c000, /* 4:1 */
203 #define DMA_BUS_MODE_RPBL_MASK 0x007e0000 /* Rx-Programmable Burst Len */
266 * Bit Field
267 * 0,00 - Full minus 1KB (only valid when rxfifo >= 4KB and EFC enabled)
268 * 0,01 - Full minus 2KB (only valid when rxfifo >= 4KB and EFC enabled)
269 * 0,10 - Full minus 3KB (only valid when rxfifo >= 4KB and EFC enabled)
270 * 0,11 - Full minus 4KB (only valid when rxfifo > 4KB and EFC enabled)
271 * 1,00 - Full minus 5KB (only valid when rxfifo > 8KB and EFC enabled)
272 * 1,01 - Full minus 6KB (only valid when rxfifo > 8KB and EFC enabled)
273 * 1,10 - Full minus 7KB (only valid when rxfifo > 8KB and EFC enabled)
274 * 1,11 - Reserved
279 * Be sure that bit 3 in GMAC Register 6 is set for Unicast Pause frame
280 * detection (IEEE Specification Requirement, Annex 31B, 31B.1, Pause
283 * Be sure that DZPA (bit 7 in Flow Control Register, GMAC Register 6),
326 #define GMAC_PTP_TCR_ATSFC BIT(24)
327 #define GMAC_PTP_TCR_ATSEN0 BIT(25)