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/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/linux/arch/arc/include/asm/
H A Duaccess.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * -__clear_user( ) called multiple times during elf load was byte loop
10 * -Hand crafted constant propagation for "constant" copy sizes
11 * -stock kernel shrunk by 33K at -O3
14 * -Added option to (UN)inline copy_(to|from)_user to reduce code sz
15 * -kernel shrunk by 200K even at -O3 (gcc 4.2.1)
16 * -Enabled when doing -Os
32 case 1: __arc_get_user_one(*(k), u, "ldb", __ret); break; \
34 case 4: __arc_get_user_one(*(k), u, "ld", __ret); break; \
[all …]
/linux/arch/alpha/lib/
H A Dmemmove.S1 /* SPDX-License-Identifier: GPL-2.0 */
7 * This is hand-massaged output from the original memcpy.c. We defer to
15 .align 4
22 .prologue 1
24 addq $16,$18,$4
26 cmpule $4,$17,$1 /* dest + n <= src */
29 bis $1,$2,$1
32 bne $1,memcpy !samegp
34 and $2,7,$2 /* Test for src/dest co-alignment. */
35 and $16,7,$1
[all …]
/linux/drivers/media/test-drivers/vicodec/
H A Dcodec-v4l2-fwht.c1 // SPDX-License-Identifier: LGPL-2.1
11 #include "codec-v4l2-fwht.h"
14 { V4L2_PIX_FMT_YUV420, 1, 3, 2, 1, 1, 2, 2, 3, 3, V4L2_FWHT_FL_PIXENC_YUV},
15 { V4L2_PIX_FMT_YVU420, 1, 3, 2, 1, 1, 2, 2, 3, 3, V4L2_FWHT_FL_PIXENC_YUV},
16 { V4L2_PIX_FMT_YUV422P, 1, 2, 1, 1, 1, 2, 1, 3, 3, V4L2_FWHT_FL_PIXENC_YUV},
17 { V4L2_PIX_FMT_NV12, 1, 3, 2, 1, 2, 2, 2, 3, 2, V4L2_FWHT_FL_PIXENC_YUV},
18 { V4L2_PIX_FMT_NV21, 1, 3, 2, 1, 2, 2, 2, 3, 2, V4L2_FWHT_FL_PIXENC_YUV},
19 { V4L2_PIX_FMT_NV16, 1, 2, 1, 1, 2, 2, 1, 3, 2, V4L2_FWHT_FL_PIXENC_YUV},
20 { V4L2_PIX_FMT_NV61, 1, 2, 1, 1, 2, 2, 1, 3, 2, V4L2_FWHT_FL_PIXENC_YUV},
21 { V4L2_PIX_FMT_NV24, 1, 3, 1, 1, 2, 1, 1, 3, 2, V4L2_FWHT_FL_PIXENC_YUV},
[all …]
/linux/Documentation/hwmon/
H A Dxdpe152c4.rst1 .. SPDX-License-Identifier: GPL-2.0
21 -----------
23 This driver implements support for Infineon Digital Multi-phase Controller
27 - Intel VR13, VR13HC and VR14 rev 1.86
29 - Intel SVID rev 1.93. protocol.
30 - PMBus rev 1.3.1 interface.
41 indexes 1, 2 are for "iin" and 3, 4 for "iout":
43 **curr[1-4]_crit**
45 **curr[1-4]_crit_alarm**
47 **curr[1-4]_input**
[all …]
/linux/arch/arm64/include/asm/
H A Dsysreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
86 * Op0 = 0, CRn = 4
[all …]
/linux/include/sound/
H A Dump_msg.h1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /* MIDI 1.0 / 2.0 Status Code (4bit) */
30 UMP_CC_MODULATION = 1,
32 UMP_CC_FOOT = 4,
131 u32 type:4;
132 u32 group:4;
133 u32 status:4;
134 u32 channel:4;
140 u32 channel:4;
141 u32 status:4;
[all …]
/linux/Documentation/input/devices/
H A Delantech.rst4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
6 Extra information for hardware version 1 found and
15 1. Introduction
18 4. Hardware version 1
20 4.2 Native relative mode 4 byte packet format
21 4.3 Native absolute mode 4 byte packet format
25 5.2.1 Parity checking and packet re-synchronization
31 6.2.1 One/Three finger touch
33 7. Hardware version 4
36 7.2.1 Status packet
[all …]
/linux/include/dt-bindings/pinctrl/
H A Dpads-imx8qxp.h1 /* SPDX-License-Identifier: GPL-2.0+ */
12 #define IMX8QXP_PCIE_CTRL0_CLKREQ_B 1
15 #define IMX8QXP_USB_SS3_TC0 4
190 … IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 IMX8QXP_PCIE_CTRL0_PERST_B 4
192 … IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 IMX8QXP_PCIE_CTRL0_CLKREQ_B 4
194 … IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 IMX8QXP_PCIE_CTRL0_WAKE_B 4
196 … IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8QXP_USB_SS3_TC0 1
198 … IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8QXP_USB_SS3_TC0 4
200 … IMX8QXP_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8QXP_USB_SS3_TC1 1
201 … IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8QXP_USB_SS3_TC1 4
[all …]
H A Dpads-imx8dxl.h1 /* SPDX-License-Identifier: GPL-2.0+ */
11 #define IMX8DXL_PCIE_CTRL0_CLKREQ_B 1
14 #define IMX8DXL_USB_SS3_TC0 4
149 … IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 IMX8DXL_PCIE_CTRL0_PERST_B 4
152 … IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 IMX8DXL_PCIE_CTRL0_CLKREQ_B 4
155 … IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 IMX8DXL_PCIE_CTRL0_WAKE_B 4
158 … IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8DXL_USB_SS3_TC0 1
160 … IMX8DXL_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8DXL_USB_SS3_TC0 4
163 … IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8DXL_USB_SS3_TC1 1
164 … IMX8DXL_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8DXL_USB_SS3_TC1 4
[all …]
/linux/arch/powerpc/boot/
H A Dstring.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 addi r5,r3,-1
14 addi r4,r4,-1
15 1: lbzu r0,1(r4)
17 stbu r0,1(r5)
18 bne 1b
26 addi r6,r3,-1
27 addi r4,r4,-1
28 1: lbzu r0,1(r4)
30 stbu r0,1(r6)
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3568-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 /omit-if-no-ref/
16 acodec_pins: acodec-pins {
19 <1 RK_PB1 5 &pcfg_pull_none>,
21 <1 RK_PA1 5 &pcfg_pull_none>,
23 <1 RK_PA0 5 &pcfg_pull_none>,
25 <1 RK_PA7 5 &pcfg_pull_none>,
27 <1 RK_PB0 5 &pcfg_pull_none>,
[all …]
/linux/tools/testing/selftests/bpf/prog_tests/
H A Dbtf.c1 /* SPDX-License-Identifier: GPL-2.0 */
100 * int q[4][8];
105 .descr = "struct test #1",
108 BTF_TYPE_INT_ENC(0, BTF_INT_SIGNED, 0, 32, 4), /* [1] */
112 BTF_TYPE_INT_ENC(0, BTF_INT_SIGNED, 0, 8, 1), /* [3] */
114 BTF_TYPE_ARRAY_ENC(1, 1, 8), /* [4] */
118 BTF_MEMBER_ENC(NAME_TBD, 1, 64),/* int n; */
120 BTF_MEMBER_ENC(NAME_TBD, 4, 128),/* int p[8] */
121 BTF_MEMBER_ENC(NAME_TBD, 6, 384),/* int q[4][8] */
124 /* int[4][8] */
[all …]
/linux/sound/soc/codecs/
H A Dsma1303.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * sma1303.h -- sma1303 ALSA SoC Audio driver
109 #define SMA1303_RESETBYI2C_MASK (1<<1)
110 #define SMA1303_RESETBYI2C_NORMAL (0<<1)
111 #define SMA1303_RESETBYI2C_RESET (1<<1)
113 #define SMA1303_POWER_MASK (1<<0)
115 #define SMA1303_POWER_ON (1<<0)
118 #define SMA1303_CONTROLLER_DEVICE_MASK (1<<7)
120 #define SMA1303_CONTROLLER_MODE (1<<7)
122 #define SMA1303_I2S_MODE_MASK (7<<4)
[all …]
H A Dpcm512x.h1 /* SPDX-License-Identifier: GPL-2.0-only */
21 #define PCM512x_RESET (PCM512x_PAGE_BASE(0) + 1)
24 #define PCM512x_PLL_EN (PCM512x_PAGE_BASE(0) + 4)
81 #define PCM512x_OUTPUT_AMPLITUDE (PCM512x_PAGE_BASE(1) + 1)
82 #define PCM512x_ANALOG_GAIN_CTRL (PCM512x_PAGE_BASE(1) + 2)
83 #define PCM512x_UNDERVOLTAGE_PROT (PCM512x_PAGE_BASE(1) + 5)
84 #define PCM512x_ANALOG_MUTE_CTRL (PCM512x_PAGE_BASE(1) + 6)
85 #define PCM512x_ANALOG_GAIN_BOOST (PCM512x_PAGE_BASE(1) + 7)
86 #define PCM512x_VCOM_CTRL_1 (PCM512x_PAGE_BASE(1) + 8)
87 #define PCM512x_VCOM_CTRL_2 (PCM512x_PAGE_BASE(1) + 9)
[all …]
/linux/drivers/media/dvb-frontends/
H A Dstv090x_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #define STV090x_OFFST_MCHIP_IDENT_FIELD 4
15 #define STV090x_WIDTH_MCHIP_IDENT_FIELD 4
17 #define STV090x_WIDTH_MRELEASE_FIELD 4
23 #define STV090x_WIDTH_DACR1_VALUE_FIELD 4
31 #define STV090x_WIDTH_OUTSERRS1_HZ_FIELD 1
33 #define STV090x_WIDTH_OUTSERRS2_HZ_FIELD 1
34 #define STV090x_OFFST_OUTSERRS3_HZ_FIELD 4
35 #define STV090x_WIDTH_OUTSERRS3_HZ_FIELD 1
37 #define STV090x_WIDTH_OUTPARRS3_HZ_FIELD 1
[all …]
/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
14 #define MC_FW_STATE_POR (1)
19 #define MC_FW_STATE_BOOTING (4)
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
63 /* MCDI version 1
[all …]
/linux/arch/powerpc/lib/
H A Dcopy_32.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Memory copy functions for 32-bit PowerPC.
5 * Copyright (C) 1996-2005 Paul Mackerras.
12 #include <asm/code-patching-asm.h>
16 lwz r7,4(r4); \
20 stw r7,4(r6); \
27 lwz r7,4(r4); \
28 8 ## n ## 1: \
34 8 ## n ## 4: \
35 stw r7,4(r6); \
[all …]
H A Dcopyuser_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <asm/asm-compat.h>
9 #include <asm/feature-fixups.h>
12 /* 0 == most CPUs, 1 == POWER6, 2 == Cell */
17 #define sLd sld /* Shift towards low-numbered address. */
18 #define sHd srd /* Shift towards high-numbered address. */
20 #define sLd srd /* Shift towards low-numbered address. */
21 #define sHd sld /* Shift towards high-numbered address. */
39 100: EX_TABLE(100b, .Lld_exc - r3_offset)
43 100: EX_TABLE(100b, .Lst_exc - r3_offset)
[all …]
/linux/tools/testing/selftests/rseq/
H A Drseq-mips-bits.h1 /* SPDX-License-Identifier: LGPL-2.1 OR MIT */
5 * (C) Copyright 2016-2022 - Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
8 #include "rseq-bits-template.h"
19 RSEQ_ASM_DEFINE_TABLE(9, 1f, 2f, 4f) /* start, commit, abort */ in RSEQ_TEMPLATE_IDENTIFIER()
20 RSEQ_ASM_DEFINE_EXIT_POINT(1f, %l[cmpfail]) in RSEQ_TEMPLATE_IDENTIFIER()
22 RSEQ_ASM_DEFINE_EXIT_POINT(1f, %l[error1]) in RSEQ_TEMPLATE_IDENTIFIER()
23 RSEQ_ASM_DEFINE_EXIT_POINT(1f, %l[error2]) in RSEQ_TEMPLATE_IDENTIFIER()
26 RSEQ_ASM_STORE_RSEQ_CS(1, 3f, rseq_cs) in RSEQ_TEMPLATE_IDENTIFIER()
27 RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) in RSEQ_TEMPLATE_IDENTIFIER()
29 LONG_L " $4, %[v]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
[all …]
/linux/tools/testing/selftests/powerpc/copyloops/
H A Dcopyuser_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <asm/asm-compat.h>
9 #include <asm/feature-fixups.h>
12 /* 0 == most CPUs, 1 == POWER6, 2 == Cell */
17 #define sLd sld /* Shift towards low-numbered address. */
18 #define sHd srd /* Shift towards high-numbered address. */
20 #define sLd srd /* Shift towards low-numbered address. */
21 #define sHd sld /* Shift towards high-numbered address. */
39 100: EX_TABLE(100b, .Lld_exc - r3_offset)
43 100: EX_TABLE(100b, .Lst_exc - r3_offset)
[all …]
/linux/arch/m68k/lib/
H A Dchecksum.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * Andreas Schwab, <schwab@issan.informatik.uni-dortmund.de>
19 * length-counter instead of the length counter
20 * (%1). Thanks to Roman Hodek for pointing this out.
22 * data-registers to hold input values and one tries to
43 * is aligned on either a 2-byte or 4-byte boundary. in csum_partial()
46 "btst #1,%3\n\t" /* Check alignment */ in csum_partial()
48 "subql #2,%1\n\t" /* buff%4==2: treat first word */ in csum_partial()
49 "jgt 1f\n\t" in csum_partial()
50 "addql #2,%1\n\t" /* len was == 2, treat only rest */ in csum_partial()
[all …]
/linux/drivers/net/ethernet/sfc/siena/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
14 #define MC_FW_STATE_POR (1)
19 #define MC_FW_STATE_BOOTING (4)
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
63 /* MCDI version 1
[all …]
/linux/Documentation/devicetree/bindings/scsi/
H A Dhisilicon-sas.txt6 - compatible : value should be as follows:
7 (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset
8 (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset
9 (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset
10 - sas-addr : array of 8 bytes for host SAS address
11 - reg : Contains two regions. The first is the address and length of the SAS
15 - hisilicon,sas-syscon: phandle of syscon used for sas control
16 - ctrl-reset-reg : offset to controller reset register in ctrl reg
17 - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg
18 - ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg
[all …]

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