Lines Matching +full:1 +full:- +full:4
1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
14 #define MC_FW_STATE_POR (1)
19 #define MC_FW_STATE_BOOTING (4)
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
63 /* MCDI version 1
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
98 #define MCDI_HEADER_RESYNC_WIDTH 1
102 #define MCDI_HEADER_SEQ_WIDTH 4
104 #define MCDI_HEADER_RSVD_WIDTH 1
106 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1
108 #define MCDI_HEADER_ERROR_WIDTH 1
110 #define MCDI_HEADER_RESPONSE_WIDTH 1
126 * - To advance a shared memory request if XFLAGS_EVREQ was set
127 * - As a notification (link state, i2c event), controlled
139 * - LEVEL==INFO Command succeeded
140 * - LEVEL==ERR Command failed
151 * non-existent MCDI command MC_CMD_DEBUG_LOG.
156 * Since the event is written in big-endian byte order, this works
157 * providing bits 56-63 of the event are 0xc0.
169 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4
185 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)
186 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)
187 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4)
189 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)
190 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)
191 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4)
193 #define SIENA_MC_BOOTROM_RECOVERY_VEC (0x800 - 2 * 0x4)
194 #define HUNT_MC_BOOTROM_RECOVERY_VEC (0x8000 - 2 * 0x4)
195 #define MEDFORD_MC_BOOTROM_RECOVERY_VEC (0x10000 - 2 * 0x4)
198 #define MEDFORD_MC_BOOTROM_REAL_NOFLASH_VEC (0x10000 - 4 * 0x4)
202 (1 << MC_CMD_READ32) | \
203 (1 << MC_CMD_WRITE32) | \
204 (1 << MC_CMD_COPYCODE) | \
205 (1 << MC_CMD_GET_VERSION), \
226 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default
227 * stack ID (which must be in the range 1-255) along with an EVB port ID.
233 * may be followed by the (0-based) number of the first argument that
236 #define MC_CMD_ERR_ARG_OFST 4
240 * specific to Solarflare firmware should use values in the range 0x1000 -
241 * 0x10ff. The range 0x2000 - 0x20ff is reserved for private error codes (see
246 /* enum: Non-existent command target */
268 /* enum: Read-only */
274 /* enum: Non-recursive resource is already acquired */
299 /* enum: V-adaptor not found. */
303 /* enum: V-switch not found. */
311 /* enum: Invalid v-switch type. */
313 /* enum: Invalid v-port type. */
334 * event and then resend its request. This error code is followed by a 32-bit
349 * an operation failed due to lack of SR-IOV privilege. Normally it is
358 * sub-variant switching.
400 /* enum: Legacy mode as described in XN-200039-TC. */
402 /* enum: Switchdev mode as described in XN-200039-TC. */
404 /* enum: Bootstrap mode as described in XN-200039-TC. */
406 /* enum: Link-mode change is in-progress as described in XN-200039-TC. */
424 * an on-NIC ARM module is expected to be connected.
447 * and must never set a non-zero mask value for this field.
478 * lookup. (Values are not arbitrary - constrained by table access ABI.)
507 /* enum: Undefined unless CT_HIT=1. */
509 /* enum: Undefined unless DO_CT=1. */
511 /* enum: Undefined unless CT_HIT=1. */
513 /* enum: 1 if the packet ingressed the NIC from one of the MACs, else 0. */
515 /* enum: 1 if the packet has 1 or more VLAN tags, else 0. */
517 /* enum: 1 if the packet has 2 or more VLAN tags, else 0. */
519 /* enum: 1 if the outer packet has 1 or more VLAN tags, else 0; only present
523 /* enum: 1 if the outer packet has 2 or more VLAN tags, else 0; only present
554 * matching? TODO: there was a proposal for driver-allocation fields. The
620 * should be treated same as NONE. (Values are not arbitrary - constrained by
641 * from CT counter 42. Generation counts are also type-specific. This value is
645 /* enum: Action Rule counters - can be referenced in AR response. */
647 /* enum: Conntrack counters - can be referenced in CT response. */
649 /* enum: Outer Rule counters - can be referenced in OR response. */
652 /* TABLE_ID enum: Unique IDs for tables. The 32-bit ID values have been
654 * block the tables belongs to (0=VNIC TX, none currently; 1=MAE; 2=VNIC RX),
658 * all supported - MC_CMD_TABLE_LIST returns the list of actually supported
661 /* enum: Outer_Rule_Table in the MAE - refer to SF-123102-TC. */
663 /* enum: Outer_Rule_No_CT_Table in the MAE - refer to SF-123102-TC. */
665 /* enum: Mgmt_Filter_Table in the MAE - refer to SF-123102-TC. */
667 /* enum: Conntrack_Table in the MAE - refer to SF-123102-TC. */
669 /* enum: Action_Rule_Table in the MAE - refer to SF-123102-TC. */
671 /* enum: Mgroup_Default_Action_Set_Table in the MAE - refer to SF-123102-TC. */
673 /* enum: Encap_Hdr_Part1_Table in the MAE - refer to SF-123102-TC. */
675 /* enum: Encap_Hdr_Part2_Table in the MAE - refer to SF-123102-TC. */
677 /* enum: Replace_Src_MAC_Table in the MAE - refer to SF-123102-TC. */
679 /* enum: Replace_Dst_MAC_Table in the MAE - refer to SF-123102-TC. */
681 /* enum: Dst_Mport_VC_Table in the MAE - refer to SF-123102-TC. */
683 /* enum: LACP_LAG_Config_Table in the MAE - refer to SF-123102-TC. */
685 /* enum: LACP_Balance_Table in the MAE - refer to SF-123102-TC. */
687 /* enum: Dst_Mport_Host_Chan_Table in the MAE - refer to SF-123102-TC. */
689 /* enum: VNIC_Rx_Encap_Table in VNIC Rx - refer to SF-123102-TC. */
691 /* enum: Steering_Table in VNIC Rx - refer to SF-123102-TC. */
693 /* enum: RSS_Context_Table in VNIC Rx - refer to SF-123102-TC. */
695 /* enum: Indirection_Table in VNIC Rx - refer to SF-123102-TC. */
741 * corresponding table definitions in SF-123102-TC; however, the mapping should
753 /* enum: Source m-port (a full m-port label). */
755 /* enum: Destination m-port (a full m-port label). */
757 /* enum: Source m-group ID. */
759 /* enum: Physical network port ID (or m-port ID; same thing, for physical
774 /* enum: Counter ID associated with a response. All-bits-1 is a null value to
784 * 48-bit value for this field is in network order, i.e. a MAC address of
785 * AA:BB:CC:DD:EE:FF becomes a 48-bit value of 0xAABBCCDDEEFF.
794 /* enum: Outer VLAN ID (least significant 12 bits of full 16-bit TCI) only. */
800 /* enum: Inner VLAN ID (least significant 12 bits of full 16-bit TCI) only. */
805 * frame to the 128-bit value for this field is in network order, with IPv4
813 /* enum: IPv4 Type-of-Service or IPv6 Traffic Class field. */
817 /* enum: Layer 4 source port. */
819 /* enum: Layer 4 destination port. */
851 /* enum: True if only/inner frame has an IP Time-To-Live of <= 1. (Note: the
853 * with TTL=0 - which we shouldn't be seeing! - as well.)
876 /* enum: Construction mode for encap_tunnel_id - see MAE_CT_VNI_MODE enum. */
891 /* enum: Encapsulation type - see MAE_MCDI_ENCAP_TYPE enum. */
903 * byte mapped to a 32-bit value in network order, i.e. the IPv4 address
907 /* enum: NAT direction: 0=>source, 1=>destination. */
917 /* enum: True to suppress delivery when source and destination m-ports match.
930 /* enum: True to decrement IP Time-To-Live. */
936 /* enum: Number of VLAN tags to pop. Valid values are 0, 1, or 2. */
938 /* enum: Number of VLANs tags to push. Valid values are 0, 1, or 2. */
957 /* enum: True to override the reported source m-port for host deliveries. */
964 * DO_REPLACE_ECN is not set, ECN_CONTROL[0] and ECN_CONTROL[1] are set to
976 /* enum: 64-byte chunk of added encapsulation header. */
978 /* enum: 32-byte chunk of added encapsulation header. */
980 /* enum: 16-byte chunk of added encapsulation header. */
982 /* enum: 8-byte chunk of added encapsulation header. */
984 /* enum: 4-byte chunk of added encapsulation header. */
986 /* enum: 2-byte chunk of added encapsulation header. */
992 /* enum: Static value for layer 4 LACP hash of the encapsulation header. */
996 * encapsulated packet to a LAG m-port.
1008 /* enum: Next action set payload ID for replay. The null value is all-1-bits.
1011 /* enum: Next action set row ID for replay. The null value is all-1-bits. */
1014 * null value is all-1-bits.
1018 * value is all-1-bits.
1021 /* enum: True to include layer 4 in LACP hash on delivery to a LAG m-port. */
1027 /* enum: Length of balance table region: 0=>64, 1=>128, 2=>256. */
1029 /* enum: UDP port to match for UDP-based encapsulations; required to be 0 for
1046 * false to bitwise-OR the USER_MARK into it.
1050 * false to bitwise-OR the USER_FLAG into it.
1059 /* enum: Key mode for IPv4 TCP packets - see TABLE_RSS_KEY_MODE enum. */
1061 /* enum: Key mode for IPv6 TCP packets - see TABLE_RSS_KEY_MODE enum. */
1063 /* enum: Key mode for IPv4 UDP packets - see TABLE_RSS_KEY_MODE enum. */
1065 /* enum: Key mode for IPv6 UDP packets - see TABLE_RSS_KEY_MODE enum. */
1067 /* enum: Key mode for other IPv4 packets - see TABLE_RSS_KEY_MODE enum. */
1069 /* enum: Key mode for other IPv6 packets - see TABLE_RSS_KEY_MODE enum. */
1071 /* enum: Spreading mode - 0=>indirection; 1=>even. */
1075 * spread across (only values 1-255 are valid for this mode).
1091 #define MCDI_EVENT_CONT_WIDTH 1
1103 #define MCDI_EVENT_DATA_LEN 4
1118 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
1123 /* enum: 1Gbs */
1137 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
1166 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
1167 /* enum: Descriptor loader reported failure. Specific to EF10-family NICs. */
1170 * EF10-family NICs
1173 /* enum: Overlength packet. Specific to EF10-family NICs. */
1175 /* enum: Malformed option descriptor. Specific to EF10-family NICs. */
1177 /* enum: Option descriptor part way through a packet. Specific to EF10-family
1181 /* enum: DMA or PIO data access error. Specific to EF10-family NICs */
1188 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1
1206 /* enum: AOE failed to load - no valid image? */
1214 /* enum: Generic AOE fault - likely to have been reported via other means too
1244 /* enum: FPGA boot-flash contains an invalid image header */
1300 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4
1306 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1
1316 /* enum: MUM failed to load - no valid image? */
1350 #define MCDI_EVENT_LINKCHANGE_V2_SPEED_WIDTH 4
1355 #define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_WIDTH 1
1380 #define MCDI_EVENT_EV_EVQ_PHASE_WIDTH 1
1382 #define MCDI_EVENT_EV_CODE_WIDTH 4
1480 * MC_CMD_DESC_PROXY_FUNC_CONFIG_COMMIT and SF-122927-TC for details.
1485 * SF-122927-TC for details.
1491 * first event's (CONT=1) DATA field carries negotiated virtio feature bits 0
1494 * SF-122927-TC for details.
1508 #define MCDI_EVENT_CMDDONE_DATA_LEN 4
1512 #define MCDI_EVENT_LINKCHANGE_DATA_LEN 4
1516 #define MCDI_EVENT_SENSOREVT_DATA_LEN 4
1520 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 4
1524 #define MCDI_EVENT_TX_ERR_DATA_LEN 4
1531 #define MCDI_EVENT_PTP_SECONDS_LEN 4
1538 #define MCDI_EVENT_PTP_MAJOR_LEN 4
1545 #define MCDI_EVENT_PTP_NANOSECONDS_LEN 4
1552 #define MCDI_EVENT_PTP_MINOR_LEN 4
1558 #define MCDI_EVENT_PTP_UUID_LEN 4
1562 #define MCDI_EVENT_RX_ERR_DATA_LEN 4
1566 #define MCDI_EVENT_PAR_ERR_DATA_LEN 4
1570 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LEN 4
1574 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 4
1579 #define MCDI_EVENT_PTP_TIME_MAJOR_LEN 4
1582 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */
1594 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1
1599 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1
1600 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of
1611 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 4
1615 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 4
1619 * should resend it. A non-zero value means that the authorization has been
1625 #define MCDI_EVENT_DBRET_DATA_LEN 4
1629 #define MCDI_EVENT_LINKCHANGE_V2_DATA_LEN 4
1633 #define MCDI_EVENT_MODULECHANGE_DATA_LEN 4
1638 #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LEN 4
1643 #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LEN 4
1648 #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LEN 4
1655 #define MCDI_EVENT_DESC_PROXY_DATA_LEN 4
1660 #define MCDI_EVENT_DESC_PROXY_GENERATION_LEN 4
1663 /* Virtio features negotiated with the host driver. First event (CONT=1)
1667 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LEN 4
1674 #define FCDI_EVENT_CONT_WIDTH 1
1686 #define FCDI_EVENT_DATA_LEN 4
1689 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1
1697 #define FCDI_EVENT_EV_CODE_WIDTH 4
1718 /* enum: Port id config to map MC-FC port idx */
1727 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LEN 4
1735 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LEN 4
1739 #define FCDI_EVENT_LINK_STATE_DATA_LEN 4
1743 #define FCDI_EVENT_PTP_STATE_LEN 4
1752 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LEN 4
1760 #define FCDI_EVENT_PORT_CONFIG_DATA_LEN 4
1764 #define FCDI_EVENT_BOOT_RESULT_LEN 4
1772 * such that bits 32-63 containing | event code, level, source etc remain the
1780 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_NUM(len) (((len)-8)/8)
1783 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 4
1788 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LEN 4
1793 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LEN 4
1800 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_LEN 4
1804 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_LEN 4
1807 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1
1816 #define MUM_EVENT_CONT_WIDTH 1
1828 #define MUM_EVENT_DATA_LEN 4
1839 #define MUM_EVENT_PORT_PHY_READY_WIDTH 1
1841 #define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1
1842 #define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1
1845 #define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1
1848 #define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1
1850 #define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4
1851 #define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1
1854 #define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1
1857 #define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1
1863 #define MUM_EVENT_EV_CODE_WIDTH 4
1875 #define MUM_EVENT_SENSOR_DATA_LEN 4
1879 #define MUM_EVENT_PORT_PHY_FLAGS_LEN 4
1883 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LEN 4
1887 #define MUM_EVENT_PORT_PHY_CAPS_LEN 4
1891 #define MUM_EVENT_PORT_PHY_TECH_LEN 4
1903 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4
1910 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4
1915 * Read multiple 32byte words from MC memory. Note - this command really
1927 #define MC_CMD_READ32_IN_ADDR_LEN 4
1928 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4
1929 #define MC_CMD_READ32_IN_NUMWORDS_LEN 4
1932 #define MC_CMD_READ32_OUT_LENMIN 4
1935 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
1936 #define MC_CMD_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
1938 #define MC_CMD_READ32_OUT_BUFFER_LEN 4
1939 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1
1957 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))
1958 #define MC_CMD_WRITE32_IN_BUFFER_NUM(len) (((len)-4)/4)
1960 #define MC_CMD_WRITE32_IN_ADDR_LEN 4
1961 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4
1962 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4
1963 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1
1973 * Copy MC code between two locations and jump. Note - this command really
1991 #define MC_CMD_COPYCODE_IN_SRC_ADDR_LEN 4
2005 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1
2008 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1
2011 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1
2013 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4
2014 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1
2017 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1
2020 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1
2022 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4
2023 #define MC_CMD_COPYCODE_IN_DEST_ADDR_LEN 4
2025 #define MC_CMD_COPYCODE_IN_NUMWORDS_LEN 4
2028 #define MC_CMD_COPYCODE_IN_JUMP_LEN 4
2038 * Select function for function-specific commands.
2046 #define MC_CMD_SET_FUNC_IN_LEN 4
2049 #define MC_CMD_SET_FUNC_IN_FUNC_LEN 4
2071 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 4
2074 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
2075 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4
2076 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_OFST 4
2078 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1
2079 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_OFST 4
2080 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1
2081 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1
2082 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_OFST 4
2084 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1
2099 #define MC_CMD_GET_ASSERTS_IN_LEN 4
2102 #define MC_CMD_GET_ASSERTS_IN_CLEAR_LEN 4
2108 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 4
2111 /* enum: A system-level assertion has failed. */
2113 /* enum: A thread-level assertion has failed. */
2120 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4
2121 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 4
2124 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4
2132 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 4
2134 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4
2142 #define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_LEN 4
2145 /* enum: A system-level assertion has failed. */
2147 /* enum: A thread-level assertion has failed. */
2154 #define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_OFST 4
2155 #define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_LEN 4
2158 #define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_LEN 4
2166 #define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_LEN 4
2168 #define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_LEN 4
2171 #define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_LEN 4
2180 #define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_LEN 4
2183 /* enum: A system-level assertion has failed. */
2185 /* enum: A thread-level assertion has failed. */
2192 #define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_OFST 4
2193 #define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_LEN 4
2196 #define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_LEN 4
2204 #define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_LEN 4
2206 #define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_LEN 4
2209 #define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_LEN 4
2211 /* MC firmware unique build ID (as binary SHA-1 value) */
2218 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_LEN 4
2222 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_LEN 4
2229 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_LEN 4
2233 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_LEN 4
2238 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_LEN 4
2239 /* MC firmware extra version info (as null-terminated US-ASCII string) */
2242 /* MC firmware build name (as null-terminated US-ASCII string) */
2261 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 4
2267 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4
2268 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_LEN 4
2287 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4
2290 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 4
2293 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4
2295 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4
2308 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2311 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4
2312 #define MC_CMD_GET_VERSION_OUT_PCOL_LEN 4
2319 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_LEN 4
2323 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_LEN 4
2330 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2333 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4
2334 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_LEN 4
2341 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_LEN 4
2345 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_LEN 4
2360 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2363 #define MC_CMD_GET_VERSION_V2_OUT_PCOL_OFST 4
2364 #define MC_CMD_GET_VERSION_V2_OUT_PCOL_LEN 4
2371 #define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_LEN 4
2375 #define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_LEN 4
2383 #define MC_CMD_GET_VERSION_V2_OUT_FLAGS_LEN 4
2386 #define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
2388 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
2389 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
2392 #define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
2395 #define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
2397 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
2398 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
2401 #define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
2404 #define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
2407 #define MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
2410 #define MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
2413 #define MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
2416 #define MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
2419 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
2422 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_WIDTH 1
2425 #define MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
2426 /* MC firmware unique build ID (as binary SHA-1 value) */
2431 #define MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_LEN 4
2432 /* MC firmware build name (as null-terminated US-ASCII string) */
2435 /* The SUC firmware version as four numbers - a.b.c.d */
2437 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_LEN 4
2438 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_NUM 4
2439 /* SUC firmware build date (as 64-bit Unix timestamp) */
2443 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_LEN 4
2447 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_LEN 4
2451 * indicates family, memory sizes etc. See SF-116728-SW for further details.
2454 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_LEN 4
2455 /* The CMC firmware version as four numbers - a.b.c.d */
2457 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_LEN 4
2458 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_NUM 4
2459 /* CMC firmware build date (as 64-bit Unix timestamp) */
2463 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_LEN 4
2467 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_LEN 4
2472 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2473 * => B, ...) FPGA_VERSION[2]: Sub-revision number
2476 #define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_LEN 4
2478 /* Extra FPGA revision information (as null-terminated US-ASCII string) */
2481 /* Board name / adapter model (as null-terminated US-ASCII string) */
2486 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_LEN 4
2487 /* Board serial number (as null-terminated US-ASCII string) */
2499 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2502 #define MC_CMD_GET_VERSION_V3_OUT_PCOL_OFST 4
2503 #define MC_CMD_GET_VERSION_V3_OUT_PCOL_LEN 4
2510 #define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_LEN 4
2514 #define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_LEN 4
2522 #define MC_CMD_GET_VERSION_V3_OUT_FLAGS_LEN 4
2525 #define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
2527 #define MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
2528 #define MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
2531 #define MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
2534 #define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
2536 #define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
2537 #define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
2540 #define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
2543 #define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
2546 #define MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
2549 #define MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
2552 #define MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
2555 #define MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
2558 #define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
2561 #define MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_WIDTH 1
2564 #define MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
2565 /* MC firmware unique build ID (as binary SHA-1 value) */
2570 #define MC_CMD_GET_VERSION_V3_OUT_MCFW_SECURITY_LEVEL_LEN 4
2571 /* MC firmware build name (as null-terminated US-ASCII string) */
2574 /* The SUC firmware version as four numbers - a.b.c.d */
2576 #define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_LEN 4
2577 #define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_NUM 4
2578 /* SUC firmware build date (as 64-bit Unix timestamp) */
2582 #define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_LEN 4
2586 #define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_LEN 4
2590 * indicates family, memory sizes etc. See SF-116728-SW for further details.
2593 #define MC_CMD_GET_VERSION_V3_OUT_SUCFW_CHIP_ID_LEN 4
2594 /* The CMC firmware version as four numbers - a.b.c.d */
2596 #define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_LEN 4
2597 #define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_NUM 4
2598 /* CMC firmware build date (as 64-bit Unix timestamp) */
2602 #define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_LEN 4
2606 #define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_LEN 4
2611 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2612 * => B, ...) FPGA_VERSION[2]: Sub-revision number
2615 #define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_LEN 4
2617 /* Extra FPGA revision information (as null-terminated US-ASCII string) */
2620 /* Board name / adapter model (as null-terminated US-ASCII string) */
2625 #define MC_CMD_GET_VERSION_V3_OUT_BOARD_REVISION_LEN 4
2626 /* Board serial number (as null-terminated US-ASCII string) */
2629 /* The version of the datapath hardware design as three number - a.b.c */
2631 #define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_LEN 4
2634 * number - a.b.c
2637 #define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_LEN 4
2645 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2648 #define MC_CMD_GET_VERSION_V4_OUT_PCOL_OFST 4
2649 #define MC_CMD_GET_VERSION_V4_OUT_PCOL_LEN 4
2656 #define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_LEN 4
2660 #define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_LEN 4
2668 #define MC_CMD_GET_VERSION_V4_OUT_FLAGS_LEN 4
2671 #define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
2673 #define MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
2674 #define MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
2677 #define MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
2680 #define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
2682 #define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
2683 #define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
2686 #define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
2689 #define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
2692 #define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
2695 #define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
2698 #define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
2701 #define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
2704 #define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
2707 #define MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_WIDTH 1
2710 #define MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
2711 /* MC firmware unique build ID (as binary SHA-1 value) */
2716 #define MC_CMD_GET_VERSION_V4_OUT_MCFW_SECURITY_LEVEL_LEN 4
2717 /* MC firmware build name (as null-terminated US-ASCII string) */
2720 /* The SUC firmware version as four numbers - a.b.c.d */
2722 #define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_LEN 4
2723 #define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_NUM 4
2724 /* SUC firmware build date (as 64-bit Unix timestamp) */
2728 #define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_LEN 4
2732 #define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_LEN 4
2736 * indicates family, memory sizes etc. See SF-116728-SW for further details.
2739 #define MC_CMD_GET_VERSION_V4_OUT_SUCFW_CHIP_ID_LEN 4
2740 /* The CMC firmware version as four numbers - a.b.c.d */
2742 #define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_LEN 4
2743 #define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_NUM 4
2744 /* CMC firmware build date (as 64-bit Unix timestamp) */
2748 #define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_LEN 4
2752 #define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_LEN 4
2757 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2758 * => B, ...) FPGA_VERSION[2]: Sub-revision number
2761 #define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_LEN 4
2763 /* Extra FPGA revision information (as null-terminated US-ASCII string) */
2766 /* Board name / adapter model (as null-terminated US-ASCII string) */
2771 #define MC_CMD_GET_VERSION_V4_OUT_BOARD_REVISION_LEN 4
2772 /* Board serial number (as null-terminated US-ASCII string) */
2775 /* The version of the datapath hardware design as three number - a.b.c */
2777 #define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_LEN 4
2780 * number - a.b.c
2783 #define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_LEN 4
2785 /* The SOC boot version as four numbers - a.b.c.d */
2787 #define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_LEN 4
2788 #define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_NUM 4
2789 /* The SOC uboot version as four numbers - a.b.c.d */
2791 #define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_LEN 4
2792 #define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_NUM 4
2793 /* The SOC main rootfs version as four numbers - a.b.c.d */
2795 #define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 4
2796 #define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 4
2797 /* The SOC recovery buildroot version as four numbers - a.b.c.d */
2799 #define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 4
2800 #define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 4
2807 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2810 #define MC_CMD_GET_VERSION_V5_OUT_PCOL_OFST 4
2811 #define MC_CMD_GET_VERSION_V5_OUT_PCOL_LEN 4
2818 #define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_LEN 4
2822 #define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_LEN 4
2830 #define MC_CMD_GET_VERSION_V5_OUT_FLAGS_LEN 4
2833 #define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
2835 #define MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
2836 #define MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
2839 #define MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
2842 #define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
2844 #define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
2845 #define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
2848 #define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
2851 #define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
2854 #define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
2857 #define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
2860 #define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
2863 #define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
2866 #define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
2869 #define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_WIDTH 1
2872 #define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
2873 /* MC firmware unique build ID (as binary SHA-1 value) */
2878 #define MC_CMD_GET_VERSION_V5_OUT_MCFW_SECURITY_LEVEL_LEN 4
2879 /* MC firmware build name (as null-terminated US-ASCII string) */
2882 /* The SUC firmware version as four numbers - a.b.c.d */
2884 #define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_LEN 4
2885 #define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_NUM 4
2886 /* SUC firmware build date (as 64-bit Unix timestamp) */
2890 #define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_LEN 4
2894 #define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_LEN 4
2898 * indicates family, memory sizes etc. See SF-116728-SW for further details.
2901 #define MC_CMD_GET_VERSION_V5_OUT_SUCFW_CHIP_ID_LEN 4
2902 /* The CMC firmware version as four numbers - a.b.c.d */
2904 #define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_LEN 4
2905 #define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_NUM 4
2906 /* CMC firmware build date (as 64-bit Unix timestamp) */
2910 #define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_LEN 4
2914 #define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_LEN 4
2919 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2920 * => B, ...) FPGA_VERSION[2]: Sub-revision number
2923 #define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_LEN 4
2925 /* Extra FPGA revision information (as null-terminated US-ASCII string) */
2928 /* Board name / adapter model (as null-terminated US-ASCII string) */
2933 #define MC_CMD_GET_VERSION_V5_OUT_BOARD_REVISION_LEN 4
2934 /* Board serial number (as null-terminated US-ASCII string) */
2937 /* The version of the datapath hardware design as three number - a.b.c */
2939 #define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_LEN 4
2942 * number - a.b.c
2945 #define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_LEN 4
2947 /* The SOC boot version as four numbers - a.b.c.d */
2949 #define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_LEN 4
2950 #define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_NUM 4
2951 /* The SOC uboot version as four numbers - a.b.c.d */
2953 #define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_LEN 4
2954 #define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_NUM 4
2955 /* The SOC main rootfs version as four numbers - a.b.c.d */
2957 #define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 4
2958 #define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 4
2959 /* The SOC recovery buildroot version as four numbers - a.b.c.d */
2961 #define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 4
2962 #define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 4
2963 /* Board version as four numbers - a.b.c.d. BOARD_VERSION[0] duplicates the
2967 #define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_LEN 4
2968 #define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_NUM 4
2969 /* Bundle version as four numbers - a.b.c.d */
2971 #define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_LEN 4
2972 #define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_NUM 4
2985 #define MC_CMD_PTP_IN_LEN 1
2988 #define MC_CMD_PTP_IN_OP_LEN 1
3046 /* enum: Get the clock attributes. NOTE- extended version of
3074 #define MC_CMD_PTP_IN_CMD_LEN 4
3075 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4
3076 #define MC_CMD_PTP_IN_PERIPH_ID_LEN 4
3081 #define MC_CMD_PTP_IN_ENABLE_QUEUE_LEN 4
3084 #define MC_CMD_PTP_IN_ENABLE_MODE_LEN 4
3085 /* enum: PTP, version 1 */
3087 /* enum: PTP, version 1, with VLAN headers - deprecated */
3091 /* enum: PTP, version 2, with VLAN headers - deprecated */
3101 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3102 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3103 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3109 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))
3110 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_NUM(len) (((len)-12)/1)
3112 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3113 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3114 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3117 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_LEN 4
3120 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1
3121 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1
3128 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3129 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3130 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3135 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3136 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3137 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3142 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3143 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3144 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3149 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3150 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3151 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3156 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_LEN 4
3160 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_LEN 4
3172 #define MC_CMD_PTP_IN_ADJUST_SECONDS_LEN 4
3175 #define MC_CMD_PTP_IN_ADJUST_MAJOR_LEN 4
3178 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_LEN 4
3181 #define MC_CMD_PTP_IN_ADJUST_MINOR_LEN 4
3186 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3187 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3188 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3193 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_LEN 4
3197 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_LEN 4
3209 #define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_LEN 4
3212 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_LEN 4
3215 #define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_LEN 4
3218 #define MC_CMD_PTP_IN_ADJUST_V2_MINOR_LEN 4
3221 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_LEN 4
3226 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3227 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3228 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3231 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_LEN 4
3238 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_LEN 4
3242 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_LEN 4
3249 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3250 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3251 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3256 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3257 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3258 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3261 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4
3266 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3267 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3268 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3273 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3274 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3275 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3278 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_LEN 4
3283 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3284 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3285 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3287 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_LEN 4
3289 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_LEN 4
3295 #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num))
3296 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_NUM(len) (((len)-12)/1)
3298 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3299 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3300 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3302 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_LEN 4
3304 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1
3305 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1
3312 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3313 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3314 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3317 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_LEN 4
3320 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_LEN 4
3323 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_LEN 4
3326 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_LEN 4
3331 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3332 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3333 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3336 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_LEN 4
3339 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_LEN 4
3342 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_LEN 4
3345 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_LEN 4
3348 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_LEN 4
3353 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3354 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3355 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3360 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_LEN 4
3364 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_LEN 4
3373 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3374 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3375 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3378 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_LEN 4
3381 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4
3387 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3388 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3389 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3390 /* 1 to enable UUID filtering, 0 to disable */
3392 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_LEN 4
3397 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_LEN 4
3401 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_LEN 4
3408 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3409 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3410 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3411 /* 1 to enable Domain filtering, 0 to disable */
3413 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_LEN 4
3416 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_LEN 4
3421 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3422 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3423 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3426 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_LEN 4
3435 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3436 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3437 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3442 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3444 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4
3445 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_LEN 4
3454 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_LEN 4
3459 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3460 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3461 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3466 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3467 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3468 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3473 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3474 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3475 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3480 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3481 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3482 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3485 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 4
3491 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1
3496 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3497 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3498 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3501 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_LEN 4
3508 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4
3513 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3514 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3515 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3516 /* 1 to enable PPS test mode, 0 to disable and return result. */
3518 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_LEN 4
3523 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3524 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3525 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3526 /* NIC - Host System Clock Synchronization status */
3528 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 4
3537 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 4
3539 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 4
3541 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 4
3550 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_LEN 4
3553 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_LEN 4
3555 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4
3556 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_LEN 4
3558 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4
3559 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_LEN 4
3571 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 4
3574 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 4
3576 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4
3577 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 4
3579 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4
3580 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 4
3586 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 4
3589 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 4
3591 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 4
3592 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 4
3594 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 4
3595 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 4
3598 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 4
3604 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 4
3606 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4
3607 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 4
3610 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 4
3613 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 4
3616 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 4
3619 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 4
3622 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 4
3625 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 4
3628 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 4
3631 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 4
3634 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 4
3637 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 4
3640 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 4
3643 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 4
3646 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 4
3649 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 4
3656 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_NUM(len) (((len)-0)/20)
3660 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1
3665 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 4
3667 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4
3668 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 4
3670 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4
3671 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 4
3674 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 4
3677 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 4
3680 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 4
3683 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 4
3689 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 4
3712 /* enum: PPS time event period not sufficiently close to 1s. */
3721 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4
3722 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 4
3728 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 4
3730 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4
3731 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 4
3734 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 4
3737 #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1
3740 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))
3741 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_NUM(len) (((len)-0)/1)
3743 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1
3744 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1
3749 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4
3753 * be assumed. Note this enum is deprecated. Do not add to it- use the
3757 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 4
3762 /* enum: Major register has units of seconds, minor 2^-27s per tick */
3773 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 4
3778 /* enum: Major register has units of seconds, minor 2^-27s per tick */
3790 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4
3791 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 4
3794 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4
3797 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1
3799 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1
3800 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1
3803 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_WIDTH 1
3806 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_WIDTH 1
3808 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 4
3810 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 4
3812 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 4
3822 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_TIME_FORMAT_LEN 4
3827 /* enum: Major register has units of seconds, minor 2^-27s per tick */
3839 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SYNC_WINDOW_MIN_OFST 4
3840 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SYNC_WINDOW_MIN_LEN 4
3843 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_CAPABILITIES_LEN 4
3846 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_REPORT_SYNC_STATUS_WIDTH 1
3848 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RX_TSTAMP_OOB_LBN 1
3849 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RX_TSTAMP_OOB_WIDTH 1
3852 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_64BIT_SECONDS_WIDTH 1
3855 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FP44_FREQ_ADJ_WIDTH 1
3857 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED0_LEN 4
3859 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED1_LEN 4
3861 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED2_LEN 4
3865 * response is not supported a value of -0.1 ns should be assumed, which is
3866 * equivalent to a -10% adjustment.
3871 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LO_LEN 4
3875 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_HI_LEN 4
3887 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LO_LEN 4
3891 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_HI_LEN 4
3899 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 4
3901 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4
3902 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 4
3905 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 4
3908 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 4
3914 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 4
3916 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4
3917 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 4
3920 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 4
3923 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 4
3924 /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */
3926 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 4
3927 /* Uncorrected error on non-PTP receive timestamps in NIC clock format */
3929 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 4
3932 #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4
3935 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_LEN 4
3956 #define MC_CMD_CSR_READ32_IN_ADDR_LEN 4
3957 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4
3958 #define MC_CMD_CSR_READ32_IN_STEP_LEN 4
3960 #define MC_CMD_CSR_READ32_IN_NUMWORDS_LEN 4
3963 #define MC_CMD_CSR_READ32_OUT_LENMIN 4
3966 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
3967 #define MC_CMD_CSR_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
3970 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4
3971 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1
3989 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))
3990 #define MC_CMD_CSR_WRITE32_IN_BUFFER_NUM(len) (((len)-8)/4)
3993 #define MC_CMD_CSR_WRITE32_IN_ADDR_LEN 4
3994 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4
3995 #define MC_CMD_CSR_WRITE32_IN_STEP_LEN 4
3997 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4
3998 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1
4003 #define MC_CMD_CSR_WRITE32_OUT_LEN 4
4005 #define MC_CMD_CSR_WRITE32_OUT_STATUS_LEN 4
4020 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at
4022 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current
4027 #define MC_CMD_HP_IN_SUBCMD_LEN 4
4028 /* enum: OCSD (Option Card Sensor Data) sub-command. */
4030 /* enum: Last known valid HP sub-command. */
4032 /* The address to the array of sensor fields. (Or NULL to use a sub-command.)
4034 #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4
4036 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4
4037 #define MC_CMD_HP_IN_OCSD_ADDR_LO_LEN 4
4041 #define MC_CMD_HP_IN_OCSD_ADDR_HI_LEN 4
4044 /* The requested update interval, in seconds. (Or the sub-command if ADDR is
4048 #define MC_CMD_HP_IN_OCSD_INTERVAL_LEN 4
4051 #define MC_CMD_HP_OUT_LEN 4
4053 #define MC_CMD_HP_OUT_OCSD_STATUS_LEN 4
4079 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_NUM(len) (((len)-0)/12)
4083 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1
4103 #define MC_CMD_MDIO_READ_IN_BUS_LEN 4
4109 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4
4110 #define MC_CMD_MDIO_READ_IN_PRTAD_LEN 4
4113 #define MC_CMD_MDIO_READ_IN_DEVAD_LEN 4
4120 #define MC_CMD_MDIO_READ_IN_ADDR_LEN 4
4126 #define MC_CMD_MDIO_READ_OUT_VALUE_LEN 4
4130 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4
4131 #define MC_CMD_MDIO_READ_OUT_STATUS_LEN 4
4151 #define MC_CMD_MDIO_WRITE_IN_BUS_LEN 4
4157 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4
4158 #define MC_CMD_MDIO_WRITE_IN_PRTAD_LEN 4
4161 #define MC_CMD_MDIO_WRITE_IN_DEVAD_LEN 4
4168 #define MC_CMD_MDIO_WRITE_IN_ADDR_LEN 4
4171 #define MC_CMD_MDIO_WRITE_IN_VALUE_LEN 4
4174 #define MC_CMD_MDIO_WRITE_OUT_LEN 4
4179 #define MC_CMD_MDIO_WRITE_OUT_STATUS_LEN 4
4198 #define MC_CMD_DBI_WRITE_IN_DBIWROP_NUM(len) (((len)-0)/12)
4204 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1
4214 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LEN 4
4217 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4
4218 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 4
4219 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_OFST 4
4222 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_OFST 4
4224 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1
4225 #define MC_CMD_DBIWROP_TYPEDEF_CS2_OFST 4
4227 #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1
4231 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LEN 4
4238 * Read a 32-bit register from the indirect port register map. The port to
4244 #define MC_CMD_PORT_READ32_IN_LEN 4
4247 #define MC_CMD_PORT_READ32_IN_ADDR_LEN 4
4253 #define MC_CMD_PORT_READ32_OUT_VALUE_LEN 4
4255 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4
4256 #define MC_CMD_PORT_READ32_OUT_STATUS_LEN 4
4261 * Write a 32-bit register to the indirect port register map. The port to
4270 #define MC_CMD_PORT_WRITE32_IN_ADDR_LEN 4
4272 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4
4273 #define MC_CMD_PORT_WRITE32_IN_VALUE_LEN 4
4276 #define MC_CMD_PORT_WRITE32_OUT_LEN 4
4279 #define MC_CMD_PORT_WRITE32_OUT_STATUS_LEN 4
4284 * Read a 128-bit register from the indirect port register map. The port to
4290 #define MC_CMD_PORT_READ128_IN_LEN 4
4293 #define MC_CMD_PORT_READ128_IN_ADDR_LEN 4
4302 #define MC_CMD_PORT_READ128_OUT_STATUS_LEN 4
4307 * Write a 128-bit register to the indirect port register map. The port to
4316 #define MC_CMD_PORT_WRITE128_IN_ADDR_LEN 4
4318 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4
4322 #define MC_CMD_PORT_WRITE128_OUT_LEN 4
4325 #define MC_CMD_PORT_WRITE128_OUT_STATUS_LEN 4
4328 #define MC_CMD_CAPABILITIES_LEN 4
4331 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1
4333 #define MC_CMD_CAPABILITIES_TURBO_LBN 1
4334 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1
4337 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1
4340 #define MC_CMD_CAPABILITIES_PTP_WIDTH 1
4342 #define MC_CMD_CAPABILITIES_AOE_LBN 4
4343 #define MC_CMD_CAPABILITIES_AOE_WIDTH 1
4346 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1
4349 #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1
4371 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_NUM(len) (((len)-72)/2)
4373 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4
4374 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
4380 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4
4385 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4
4400 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4
4405 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4
4410 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4
4415 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4
4416 /* Siena only. This field contains a 16-bit value for each of the types of
4431 * Read DBI register(s) -- extended functionality
4443 #define MC_CMD_DBI_READX_IN_DBIRDOP_NUM(len) (((len)-0)/8)
4448 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_LEN 4
4451 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4
4452 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_LEN 4
4455 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1
4460 #define MC_CMD_DBI_READX_OUT_LENMIN 4
4463 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))
4464 #define MC_CMD_DBI_READX_OUT_VALUE_NUM(len) (((len)-0)/4)
4467 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4
4468 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1
4475 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LEN 4
4478 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4
4479 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 4
4480 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_OFST 4
4483 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_OFST 4
4485 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1
4486 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_OFST 4
4488 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1
4495 * Set the 16byte seed for the MC pseudo-random generator.
4525 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))
4526 #define MC_CMD_LTSSM_HIST_OUT_DATA_NUM(len) (((len)-0)/4)
4527 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */
4529 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4
4551 /* new state to set if UPDATE=1 */
4553 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4
4556 #define MC_CMD_DRV_ATTACH_WIDTH 1
4559 #define MC_CMD_DRV_ATTACH_IN_ATTACH_WIDTH 1
4561 #define MC_CMD_DRV_PREBOOT_LBN 1
4562 #define MC_CMD_DRV_PREBOOT_WIDTH 1
4564 #define MC_CMD_DRV_ATTACH_IN_PREBOOT_LBN 1
4565 #define MC_CMD_DRV_ATTACH_IN_PREBOOT_WIDTH 1
4568 #define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_WIDTH 1
4571 #define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_WIDTH 1
4573 #define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_LBN 4
4574 #define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_WIDTH 1
4577 #define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1
4580 #define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_WIDTH 1
4581 /* 1 to set new state, or 0 to just report the existing state */
4582 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
4583 #define MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4
4586 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 4
4605 /* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
4612 * (i.e. non-production) builds.
4615 /* enum: Only this option is allowed for non-admin functions */
4622 /* new state to set if UPDATE=1 */
4624 #define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_LEN 4
4627 /* MC_CMD_DRV_ATTACH_WIDTH 1 */
4630 #define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_WIDTH 1
4632 /* MC_CMD_DRV_PREBOOT_LBN 1 */
4633 /* MC_CMD_DRV_PREBOOT_WIDTH 1 */
4635 #define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_LBN 1
4636 #define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_WIDTH 1
4639 #define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_WIDTH 1
4642 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_WIDTH 1
4644 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_LBN 4
4645 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_WIDTH 1
4648 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1
4651 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_WIDTH 1
4652 /* 1 to set new state, or 0 to just report the existing state */
4653 #define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_OFST 4
4654 #define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_LEN 4
4657 #define MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_LEN 4
4676 /* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
4683 * (i.e. non-production) builds.
4686 /* enum: Only this option is allowed for non-admin functions */
4688 /* Version of the driver to be reported by management protocols (e.g. NC-SI)
4689 * handled by the NIC. This is a zero-terminated ASCII string.
4695 #define MC_CMD_DRV_ATTACH_OUT_LEN 4
4698 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 4
4704 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 4
4706 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4
4707 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 4
4708 /* enum: Labels the lowest-numbered function visible to the OS */
4727 /* enum: If set, indicates that TX only spreading is enabled. Even-numbered
4728 * TXQs will use one engine, and odd-numbered TXQs will use the other. This
4729 * also has the effect that only even-numbered RXQs will receive traffic.
4741 #define MC_CMD_SHMUART_IN_LEN 4
4744 #define MC_CMD_SHMUART_IN_FLAG_LEN 4
4752 * Generic per-port reset. There is no equivalent for per-board reset. Locks
4753 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated -
4770 * Generic per-resource reset. There is no equivalent for per-board reset.
4778 #define MC_CMD_ENTITY_RESET_IN_LEN 4
4783 #define MC_CMD_ENTITY_RESET_IN_FLAG_LEN 4
4786 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1
4802 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_LEN 4
4804 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4
4805 #define MC_CMD_PCIE_CREDITS_IN_WIPE_LEN 4
4813 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4
4836 #define MC_CMD_RXD_MONITOR_IN_QID_LEN 4
4837 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4
4838 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_LEN 4
4840 #define MC_CMD_RXD_MONITOR_IN_WIPE_LEN 4
4845 #define MC_CMD_RXD_MONITOR_OUT_QID_LEN 4
4846 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4
4847 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_LEN 4
4849 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_LEN 4
4851 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_LEN 4
4853 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_LEN 4
4855 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_LEN 4
4857 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_LEN 4
4859 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_LEN 4
4861 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_LEN 4
4863 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_LEN 4
4865 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_LEN 4
4867 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_LEN 4
4869 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_LEN 4
4871 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_LEN 4
4873 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_LEN 4
4875 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_LEN 4
4877 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_LEN 4
4879 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_LEN 4
4881 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_LEN 4
4883 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_LEN 4
4899 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num))
4900 #define MC_CMD_PUTS_IN_STRING_NUM(len) (((len)-12)/1)
4902 #define MC_CMD_PUTS_IN_DEST_LEN 4
4905 #define MC_CMD_PUTS_IN_UART_WIDTH 1
4907 #define MC_CMD_PUTS_IN_PORT_LBN 1
4908 #define MC_CMD_PUTS_IN_PORT_WIDTH 1
4909 #define MC_CMD_PUTS_IN_DHOST_OFST 4
4912 #define MC_CMD_PUTS_IN_STRING_LEN 1
4913 #define MC_CMD_PUTS_IN_STRING_MINNUM 1
4938 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 4
4941 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1
4943 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1
4944 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1
4947 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1
4950 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1
4952 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4
4953 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1
4956 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1
4959 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1
4961 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4
4962 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_LEN 4
4965 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 4
4967 #define MC_CMD_PHY_CAP_10HDX_LBN 1
4968 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1
4971 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1
4974 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1
4976 #define MC_CMD_PHY_CAP_100FDX_LBN 4
4977 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1
4980 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1
4983 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1
4986 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1
4989 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1
4992 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1
4995 #define MC_CMD_PHY_CAP_AN_WIDTH 1
4998 #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1
5001 #define MC_CMD_PHY_CAP_DDM_WIDTH 1
5004 #define MC_CMD_PHY_CAP_100000FDX_WIDTH 1
5007 #define MC_CMD_PHY_CAP_25000FDX_WIDTH 1
5010 #define MC_CMD_PHY_CAP_50000FDX_WIDTH 1
5013 #define MC_CMD_PHY_CAP_BASER_FEC_WIDTH 1
5016 #define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_WIDTH 1
5019 #define MC_CMD_PHY_CAP_RS_FEC_WIDTH 1
5022 #define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_WIDTH 1
5025 #define MC_CMD_PHY_CAP_25G_BASER_FEC_WIDTH 1
5028 #define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_WIDTH 1
5031 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 4
5034 #define MC_CMD_GET_PHY_CFG_OUT_PRT_LEN 4
5037 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_LEN 4
5043 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_LEN 4
5061 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 4
5090 #define MC_CMD_START_BIST_IN_LEN 4
5093 #define MC_CMD_START_BIST_IN_TYPE_LEN 4
5136 #define MC_CMD_POLL_BIST_OUT_RESULT_LEN 4
5143 /* enum: Timed-out. */
5145 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4
5146 #define MC_CMD_POLL_BIST_OUT_PRIVATE_LEN 4
5152 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
5155 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4
5156 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_LEN 4
5158 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_LEN 4
5160 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_LEN 4
5162 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_LEN 4
5165 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_LEN 4
5170 /* enum: Intra-pair short. */
5172 /* enum: Inter-pair short. */
5178 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_LEN 4
5183 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_LEN 4
5188 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_LEN 4
5196 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
5199 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4
5200 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_LEN 4
5224 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
5227 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4
5228 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_LEN 4
5231 /* enum: RAM test - walk ones. */
5233 /* enum: RAM test - walk zeros. */
5235 /* enum: RAM test - walking inversions zeros/ones. */
5237 /* enum: RAM test - walking inversions checkerboard. */
5239 /* enum: Register test - set / clear individual bits. */
5245 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_LEN 4
5248 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_LEN 4
5269 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_LEN 4
5272 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_LEN 4
5275 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_LEN 4
5278 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_LEN 4
5281 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 4
5296 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4
5299 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))
5300 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_NUM(len) (((len)-0)/4)
5302 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4
5303 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1
5329 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LEN 4
5332 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
5333 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LEN 4
5370 /* enum: PMA-PMD. */
5372 /* enum: Cross-Port. */
5374 /* enum: XGMII-Wireside. */
5390 /* enum: PMA lanes MAC-Serdes. */
5396 /* enum: PMA lanes MAC-Serdes Wireside. */
5418 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_LEN 4
5422 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LEN 4
5431 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_LEN 4
5435 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LEN 4
5444 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_LEN 4
5448 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LEN 4
5457 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_LEN 4
5461 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LEN 4
5475 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LEN 4
5478 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4
5479 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LEN 4
5516 /* enum: PMA-PMD. */
5518 /* enum: Cross-Port. */
5520 /* enum: XGMII-Wireside. */
5536 /* enum: PMA lanes MAC-Serdes. */
5542 /* enum: PMA lanes MAC-Serdes Wireside. */
5564 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_LEN 4
5568 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LEN 4
5577 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_LEN 4
5581 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LEN 4
5590 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_LEN 4
5594 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LEN 4
5603 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_LEN 4
5607 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LEN 4
5616 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_LEN 4
5620 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LEN 4
5629 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_LEN 4
5633 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LEN 4
5642 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_LEN 4
5646 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LEN 4
5652 /* AN_TYPE structuredef: Auto-negotiation types defined in IEEE802.3 */
5653 #define AN_TYPE_LEN 4
5655 #define AN_TYPE_TYPE_LEN 4
5658 /* enum: Clause 28 - BASE-T */
5660 /* enum: Clause 37 - BASE-X */
5662 /* enum: Clause 73 - BASE-R startup protocol for backplane and copper cable
5663 * assemblies. Includes Clause 72/Clause 92 link-training.
5671 #define FEC_TYPE_LEN 4
5673 #define FEC_TYPE_TYPE_LEN 4
5676 /* enum: Clause 74 BASE-R FEC (a.k.a Firecode) */
5678 /* enum: Clause 91/Clause 108 Reed-Solomon FEC */
5699 /* Near-side advertised capabilities. Refer to
5703 #define MC_CMD_GET_LINK_OUT_CAP_LEN 4
5704 /* Link-partner advertised capabilities. Refer to
5707 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
5708 #define MC_CMD_GET_LINK_OUT_LP_CAP_LEN 4
5710 * reads non-zero.
5713 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_LEN 4
5716 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_LEN 4
5720 #define MC_CMD_GET_LINK_OUT_FLAGS_LEN 4
5723 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1
5725 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1
5726 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1
5729 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1
5732 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1
5735 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1
5738 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1
5741 #define MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_WIDTH 1
5744 #define MC_CMD_GET_LINK_OUT_MODULE_UP_WIDTH 1
5747 #define MC_CMD_GET_LINK_OUT_FCNTL_LEN 4
5751 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 4
5754 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1
5756 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1
5757 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1
5760 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1
5763 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1
5767 /* Near-side advertised capabilities. Refer to
5771 #define MC_CMD_GET_LINK_OUT_V2_CAP_LEN 4
5772 /* Link-partner advertised capabilities. Refer to
5775 #define MC_CMD_GET_LINK_OUT_V2_LP_CAP_OFST 4
5776 #define MC_CMD_GET_LINK_OUT_V2_LP_CAP_LEN 4
5778 * reads non-zero.
5781 #define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_LEN 4
5784 #define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_LEN 4
5788 #define MC_CMD_GET_LINK_OUT_V2_FLAGS_LEN 4
5791 #define MC_CMD_GET_LINK_OUT_V2_LINK_UP_WIDTH 1
5793 #define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_LBN 1
5794 #define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_WIDTH 1
5797 #define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_WIDTH 1
5800 #define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_WIDTH 1
5803 #define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_WIDTH 1
5806 #define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_WIDTH 1
5809 #define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_WIDTH 1
5812 #define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_WIDTH 1
5815 #define MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 4
5819 #define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_LEN 4
5822 /* MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 */
5824 /* MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 */
5825 /* MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 */
5828 /* MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 */
5831 /* MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 */
5833 * e.g. plugged-in module). In general, subset of
5836 * to SUPPORTED_CAP for non-pluggable PMDs. Refer to
5840 #define MC_CMD_GET_LINK_OUT_V2_LD_CAP_LEN 4
5841 /* Auto-negotiation type used on the link */
5843 #define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_LEN 4
5848 #define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_LEN 4
5852 #define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_LEN 4
5855 #define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_WIDTH 1
5857 #define MC_CMD_GET_LINK_OUT_V2_PMD_READY_LBN 1
5858 #define MC_CMD_GET_LINK_OUT_V2_PMD_READY_WIDTH 1
5861 #define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_WIDTH 1
5864 #define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_WIDTH 1
5866 #define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_LBN 4
5867 #define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_WIDTH 1
5870 #define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_WIDTH 1
5873 #define MC_CMD_GET_LINK_OUT_V2_HI_BER_WIDTH 1
5876 #define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_WIDTH 1
5879 #define MC_CMD_GET_LINK_OUT_V2_AN_DONE_WIDTH 1
5882 #define MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_WIDTH 1
5897 /* Near-side advertised capabilities. Refer to
5901 #define MC_CMD_SET_LINK_IN_CAP_LEN 4
5903 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4
5904 #define MC_CMD_SET_LINK_IN_FLAGS_LEN 4
5905 #define MC_CMD_SET_LINK_IN_LOWPOWER_OFST 4
5907 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1
5908 #define MC_CMD_SET_LINK_IN_POWEROFF_OFST 4
5909 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1
5910 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1
5911 #define MC_CMD_SET_LINK_IN_TXDIS_OFST 4
5913 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1
5914 #define MC_CMD_SET_LINK_IN_LINKDOWN_OFST 4
5916 #define MC_CMD_SET_LINK_IN_LINKDOWN_WIDTH 1
5919 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 4
5926 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 4
5933 /* Near-side advertised capabilities. Refer to
5937 #define MC_CMD_SET_LINK_IN_V2_CAP_LEN 4
5939 #define MC_CMD_SET_LINK_IN_V2_FLAGS_OFST 4
5940 #define MC_CMD_SET_LINK_IN_V2_FLAGS_LEN 4
5941 #define MC_CMD_SET_LINK_IN_V2_LOWPOWER_OFST 4
5943 #define MC_CMD_SET_LINK_IN_V2_LOWPOWER_WIDTH 1
5944 #define MC_CMD_SET_LINK_IN_V2_POWEROFF_OFST 4
5945 #define MC_CMD_SET_LINK_IN_V2_POWEROFF_LBN 1
5946 #define MC_CMD_SET_LINK_IN_V2_POWEROFF_WIDTH 1
5947 #define MC_CMD_SET_LINK_IN_V2_TXDIS_OFST 4
5949 #define MC_CMD_SET_LINK_IN_V2_TXDIS_WIDTH 1
5950 #define MC_CMD_SET_LINK_IN_V2_LINKDOWN_OFST 4
5952 #define MC_CMD_SET_LINK_IN_V2_LINKDOWN_WIDTH 1
5955 #define MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_LEN 4
5962 #define MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_LEN 4
5964 #define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_LEN 1
5970 #define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_WIDTH 1
5986 #define MC_CMD_SET_ID_LED_IN_LEN 4
5989 #define MC_CMD_SET_ID_LED_IN_STATE_LEN 4
6013 #define MC_CMD_SET_MAC_IN_MTU_LEN 4
6014 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4
6015 #define MC_CMD_SET_MAC_IN_DRAIN_LEN 4
6019 #define MC_CMD_SET_MAC_IN_ADDR_LO_LEN 4
6023 #define MC_CMD_SET_MAC_IN_ADDR_HI_LEN 4
6027 #define MC_CMD_SET_MAC_IN_REJECT_LEN 4
6030 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1
6032 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1
6033 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1
6035 #define MC_CMD_SET_MAC_IN_FCNTL_LEN 4
6049 #define MC_CMD_SET_MAC_IN_FLAGS_LEN 4
6052 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1
6060 #define MC_CMD_SET_MAC_EXT_IN_MTU_LEN 4
6061 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4
6062 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_LEN 4
6066 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_LEN 4
6070 #define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_LEN 4
6074 #define MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4
6077 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1
6079 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1
6080 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1
6082 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_LEN 4
6096 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 4
6099 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1
6106 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 4
6109 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1
6111 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1
6112 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1
6115 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1
6118 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1
6120 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4
6121 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1
6129 #define MC_CMD_SET_MAC_V3_IN_MTU_LEN 4
6130 #define MC_CMD_SET_MAC_V3_IN_DRAIN_OFST 4
6131 #define MC_CMD_SET_MAC_V3_IN_DRAIN_LEN 4
6135 #define MC_CMD_SET_MAC_V3_IN_ADDR_LO_LEN 4
6139 #define MC_CMD_SET_MAC_V3_IN_ADDR_HI_LEN 4
6143 #define MC_CMD_SET_MAC_V3_IN_REJECT_LEN 4
6146 #define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_WIDTH 1
6148 #define MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_LBN 1
6149 #define MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_WIDTH 1
6151 #define MC_CMD_SET_MAC_V3_IN_FCNTL_LEN 4
6165 #define MC_CMD_SET_MAC_V3_IN_FLAGS_LEN 4
6168 #define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_WIDTH 1
6175 #define MC_CMD_SET_MAC_V3_IN_CONTROL_LEN 4
6178 #define MC_CMD_SET_MAC_V3_IN_CFG_MTU_WIDTH 1
6180 #define MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_LBN 1
6181 #define MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_WIDTH 1
6184 #define MC_CMD_SET_MAC_V3_IN_CFG_REJECT_WIDTH 1
6187 #define MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_WIDTH 1
6189 #define MC_CMD_SET_MAC_V3_IN_CFG_FCS_LBN 4
6190 #define MC_CMD_SET_MAC_V3_IN_CFG_FCS_WIDTH 1
6195 * circumstances. 1. Some will always work (e.g. a VF can always address its
6201 * and 4. Some could be implementation-specific and fail with ENOTSUP if not
6202 * available (no examples exist right now). See SF-123581-TC section 4.3 for
6208 #define MC_CMD_SET_MAC_V3_IN_TARGET_LO_LEN 4
6212 #define MC_CMD_SET_MAC_V3_IN_TARGET_HI_LEN 4
6216 #define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_LEN 4
6218 #define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
6220 #define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
6224 #define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
6226 #define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
6228 #define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
6230 #define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
6234 #define MC_CMD_SET_MAC_V3_IN_TARGET_LINK_END_LEN 4
6238 #define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_LEN 4
6242 #define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_LEN 4
6250 #define MC_CMD_SET_MAC_V2_OUT_LEN 4
6256 #define MC_CMD_SET_MAC_V2_OUT_MTU_LEN 4
6265 * statistics are dmad to that (page-aligned location). Locks required: None.
6279 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LEN 4
6282 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
6283 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_LEN 4
6293 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4
6297 /* enum: PMA-PMD Link Up. */
6299 /* enum: PMA-PMD RX Fault. */
6301 /* enum: PMA-PMD TX Fault. */
6303 /* enum: PMA-PMD Signal */
6305 /* enum: PMA-PMD SNR A. */
6307 /* enum: PMA-PMD SNR B. */
6309 /* enum: PMA-PMD SNR C. */
6311 /* enum: PMA-PMD SNR D. */
6333 /* enum: AN link-up. */
6339 /* enum: Clause 22 Link-Up. */
6352 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location).
6367 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LEN 4
6370 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
6371 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_LEN 4
6375 #define MC_CMD_MAC_STATS_IN_CMD_LEN 4
6378 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1
6380 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1
6381 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1
6384 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1
6387 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1
6389 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4
6390 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1
6393 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1
6403 #define MC_CMD_MAC_STATS_IN_DMA_LEN_LEN 4
6406 #define MC_CMD_MAC_STATS_IN_PORT_ID_LEN 4
6416 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LEN 4
6419 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
6420 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_LEN 4
6521 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with
6562 * 64-bit word of the DMA buffer (at DMA_LEN - sizeof(uint64_t)). Note that
6564 * the last 64-bit word in the buffer when DMA_LEN == MC_CMD_MAC_NSTATS *
6565 * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details.
6578 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LEN 4
6581 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4
6582 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_LEN 4
6588 /* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2)
6591 /* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2)
6594 /* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
6596 /* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */
6598 /* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */
6600 /* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */
6617 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LEN 4
6620 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4
6621 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_LEN 4
6658 * or not 32-bit aligned
6697 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LEN 4
6700 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_OFST 4
6701 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_LEN 4
6736 #define MC_CMD_SRIOV_IN_ENABLE_LEN 4
6737 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4
6738 #define MC_CMD_SRIOV_IN_VI_BASE_LEN 4
6740 #define MC_CMD_SRIOV_IN_VF_COUNT_LEN 4
6745 #define MC_CMD_SRIOV_OUT_VI_SCALE_LEN 4
6746 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4
6747 #define MC_CMD_SRIOV_OUT_VF_TOTAL_LEN 4
6753 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LEN 4
6756 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4
6757 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LEN 4
6763 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_LEN 4
6767 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_LEN 4
6773 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LEN 4
6780 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_LEN 4
6784 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_LEN 4
6790 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LEN 4
6822 #define MC_CMD_MEMCPY_IN_RECORD_NUM(len) (((len)-0)/32)
6826 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1
6846 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4
6849 /* A type value of 1 is unused. */
6850 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
6851 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4
6867 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4
6873 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
6874 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
6875 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
6879 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_LEN 4
6883 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_LEN 4
6890 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
6891 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
6892 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
6894 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_LEN 4
6896 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_LEN 4
6905 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
6906 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
6907 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
6920 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
6921 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
6922 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
6928 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1
6930 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1
6932 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1
6937 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
6938 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
6939 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
6941 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 4
6944 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1
6946 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1
6947 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1
6950 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4
6952 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 4
6965 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4
6967 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_LEN 4
6984 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4
6986 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 4
7025 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4
7028 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 4
7084 #define MC_CMD_NVRAM_INFO_IN_LEN 4
7086 #define MC_CMD_NVRAM_INFO_IN_TYPE_LEN 4
7093 #define MC_CMD_NVRAM_INFO_OUT_TYPE_LEN 4
7096 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4
7097 #define MC_CMD_NVRAM_INFO_OUT_SIZE_LEN 4
7099 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 4
7101 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 4
7104 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1
7106 #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1
7107 #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1
7110 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
7113 #define MC_CMD_NVRAM_INFO_OUT_CRC_WIDTH 1
7116 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1
7119 #define MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1
7122 #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1
7124 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_LEN 4
7126 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_LEN 4
7131 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_LEN 4
7134 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4
7135 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_LEN 4
7137 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 4
7139 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 4
7142 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1
7144 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1
7145 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1
7148 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
7151 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1
7154 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1
7156 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 4
7158 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_LEN 4
7162 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 4
7183 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4
7185 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 4
7196 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 4
7199 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4
7200 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4
7201 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 4
7203 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
7223 #define MC_CMD_NVRAM_READ_IN_TYPE_LEN 4
7226 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4
7227 #define MC_CMD_NVRAM_READ_IN_OFFSET_LEN 4
7230 #define MC_CMD_NVRAM_READ_IN_LENGTH_LEN 4
7235 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 4
7238 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4
7239 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 4
7242 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 4
7246 * from. This allows it to perform a read-modify-write-verify with the write
7252 #define MC_CMD_NVRAM_READ_IN_V2_MODE_LEN 4
7262 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B
7268 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1
7271 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
7272 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_NUM(len) (((len)-0)/1)
7274 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1
7275 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1
7295 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))
7296 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_NUM(len) (((len)-12)/1)
7298 #define MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 4
7301 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4
7302 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_LEN 4
7304 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_LEN 4
7306 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1
7307 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1
7329 #define MC_CMD_NVRAM_ERASE_IN_TYPE_LEN 4
7332 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4
7333 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_LEN 4
7335 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_LEN 4
7361 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 4
7364 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4
7365 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 4
7374 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 4
7377 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4
7378 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4
7380 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4
7383 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
7385 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_LBN 1
7386 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_WIDTH 1
7389 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_WIDTH 1
7392 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_WIDTH 1
7411 * per-partition nvram lock in firmware is only released after the verification
7414 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4
7417 * the field are marked with a prefix 'Internal-error'.
7420 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4
7421 /* enum: Invalid return code; only non-zero values are defined. Defined as
7433 /* enum: Error in message digest calculated over the reflash-header, payload
7434 * and reflash-trailer.
7451 /* enum: The image contains a test-signed certificate, but the adapter accepts
7457 /* enum: Internal-error. The signed image is missing the 'contents' section,
7461 /* enum: Internal-error. The bundle header is invalid. */
7463 /* enum: Internal-error. The bundle does not have a valid reflash image layout.
7466 /* enum: Internal-error. The bundle has an inconsistent layout of components or
7470 /* enum: Internal-error. The bundle manifest is inconsistent with components in
7474 /* enum: Internal-error. The number of components in a bundle do not match the
7478 /* enum: Internal-error. The bundle contains too many components for the MC
7482 /* enum: Internal-error. The bundle manifest has an invalid/inconsistent
7486 /* enum: Internal-error. The hash of a component does not match the hash stored
7490 /* enum: Internal-error. Component hash calculation failed. */
7492 /* enum: Internal-error. The component does not have a valid reflash image
7500 /* enum: The update operation is in-progress. */
7513 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1,
7519 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1,
7528 #define MC_CMD_REBOOT_IN_LEN 4
7530 #define MC_CMD_REBOOT_IN_FLAGS_LEN 4
7552 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4
7555 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))
7556 #define MC_CMD_SCHEDINFO_OUT_DATA_NUM(len) (((len)-0)/4)
7558 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4
7559 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1
7575 #define MC_CMD_REBOOT_MODE_IN_LEN 4
7577 #define MC_CMD_REBOOT_MODE_IN_VALUE_LEN 4
7580 /* enum: Power-on Reset. */
7588 #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1
7591 #define MC_CMD_REBOOT_MODE_OUT_LEN 4
7593 #define MC_CMD_REBOOT_MODE_OUT_VALUE_LEN 4
7636 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4
7641 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
7644 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 4
7652 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
7655 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_LEN 4
7657 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_OFST 4
7658 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_LEN 4
7659 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_OFST 4
7661 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_WIDTH 1
7664 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4
7667 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))
7668 #define MC_CMD_SENSOR_INFO_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
7670 #define MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4
7681 /* enum: Phy 1 temperature: degC */
7683 /* enum: Phy 1 cooling: bool */
7711 /* enum: Fan 1 speed: RPM */
7717 /* enum: Fan 4 speed: RPM */
7763 /* enum: Port 0 PHY power switch over-current: bool */
7765 /* enum: Port 1 PHY power switch over-current: bool */
7767 /* enum: Mop-up microcontroller reference voltage: mV */
7781 /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */
7783 /* enum: CCOM AVREG 1v2 supply (external ADC): mV */
7785 /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */
7787 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */
7821 /* enum: Temperature of SODIMM 1 (if installed): degC */
7825 /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */
7845 /* enum: Engineering sensor 1 */
7851 /* enum: Engineering sensor 4 */
7864 #define MC_CMD_SENSOR_ENTRY_OFST 4
7866 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4
7867 #define MC_CMD_SENSOR_ENTRY_LO_LEN 4
7871 #define MC_CMD_SENSOR_ENTRY_HI_LEN 4
7879 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4
7882 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))
7883 #define MC_CMD_SENSOR_INFO_EXT_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
7885 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4
7890 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1
7892 /* MC_CMD_SENSOR_ENTRY_OFST 4 */
7894 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */
7895 /* MC_CMD_SENSOR_ENTRY_LO_LEN 4 */
7899 /* MC_CMD_SENSOR_ENTRY_HI_LEN 4 */
7916 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4
7950 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
7958 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LEN 4
7961 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
7962 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_LEN 4
7968 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
7976 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LEN 4
7979 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4
7980 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_LEN 4
7985 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4
7989 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
7997 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LEN 4
8000 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_OFST 4
8001 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_LEN 4
8006 #define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_LEN 4
8009 #define MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_LEN 4
8012 #define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_WIDTH 1
8021 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4
8027 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1
8043 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1
8065 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4
8067 #define MC_CMD_GET_PHY_STATE_OUT_STATE_LEN 4
8076 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to
8103 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4
8105 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 4
8110 * Add a protocol offload to NIC for lights-out state. Locks required: None.
8122 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))
8123 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_NUM(len) (((len)-4)/4)
8125 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
8128 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4
8129 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4
8130 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1
8137 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */
8138 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4
8141 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_LEN 4
8146 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */
8147 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4
8155 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4
8157 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_LEN 4
8162 * Remove a protocol offload from NIC for lights-out state. Locks required:
8173 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
8174 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4
8175 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_LEN 4
8196 * Deliberately trigger an assert-detonation in the firmware for testing
8212 #define MC_CMD_TESTASSERT_V2_IN_LEN 4
8215 #define MC_CMD_TESTASSERT_V2_IN_TYPE_LEN 4
8238 * understand the given workaround number - which should not be treated as a
8240 * workaround, that's between the driver and the mcfw on a per-workaround
8252 #define MC_CMD_WORKAROUND_IN_TYPE_LEN 4
8262 * - before adding code that queries this workaround, remember that there's
8277 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable
8280 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4
8281 #define MC_CMD_WORKAROUND_IN_ENABLED_LEN 4
8289 #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4
8291 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4
8294 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1
8299 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for
8302 * output data, are interpreted on a per-type basis. For SFP+, PAGE=0 or 1
8303 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80.
8304 * For QSFP, PAGE=-1 is the lower (unbanked) page. PAGE=2 is the EEPROM and
8308 * of "0xffff:0xffff" retrieves the lower (unbanked) page. Locks required -
8309 * None. Return code - 0.
8317 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4
8319 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_LEN 4
8331 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))
8332 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_NUM(len) (((len)-4)/1)
8335 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 4
8336 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4
8337 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1
8338 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1
8354 #define MC_CMD_NVRAM_TEST_IN_LEN 4
8356 #define MC_CMD_NVRAM_TEST_IN_TYPE_LEN 4
8361 #define MC_CMD_NVRAM_TEST_OUT_LEN 4
8363 #define MC_CMD_NVRAM_TEST_OUT_RESULT_LEN 4
8382 /* 0-6 low->high de-emph. */
8384 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_LEN 4
8385 /* 0-8 low->high ref.V */
8386 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4
8387 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_LEN 4
8388 /* 0-8 0-8 low->high boost */
8390 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_LEN 4
8391 /* 0-8 low->high ref.V */
8393 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_LEN 4
8402 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_LEN 4
8404 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4
8405 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_LEN 4
8408 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_LEN 4
8417 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns:
8429 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_LEN 4
8432 /* interpretation is is sensor-specific. */
8433 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4
8434 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_LEN 4
8435 /* interpretation is is sensor-specific. */
8437 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_LEN 4
8438 /* interpretation is is sensor-specific. */
8440 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_LEN 4
8441 /* interpretation is is sensor-specific. */
8443 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_LEN 4
8460 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_LEN 4
8461 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4
8462 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_LEN 4
8464 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_LEN 4
8466 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_LEN 4
8483 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4
8486 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))
8487 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_NUM(len) (((len)-4)/4)
8490 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 4
8492 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4
8493 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4
8510 #define MC_CMD_NVRAM_METADATA_IN_LEN 4
8513 #define MC_CMD_NVRAM_METADATA_IN_TYPE_LEN 4
8519 #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num))
8520 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_NUM(len) (((len)-20)/1)
8523 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4
8524 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4
8525 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4
8526 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_OFST 4
8528 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1
8529 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_OFST 4
8530 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1
8531 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1
8532 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_OFST 4
8534 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1
8537 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 4
8538 /* 1st component of W.X.Y.Z version number for content of this partition */
8547 /* 4th component of W.X.Y.Z version number for content of this partition */
8550 /* Zero-terminated string describing the content of this partition */
8552 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1
8580 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 4
8583 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4
8588 * Perform a CLP related operation, see SF-110495-PS for details of CLP
8590 * different manufacturers which are to be found in SF-119187-TC, SF-119186-TC,
8591 * SF-120509-TC and SF-117282-PS.
8599 #define MC_CMD_CLP_IN_LEN 4
8602 #define MC_CMD_CLP_IN_OP_LEN 4
8618 #define MC_CMD_CLP_IN_DEFAULT_LEN 4
8620 /* MC_CMD_CLP_IN_OP_LEN 4 */
8628 /* MC_CMD_CLP_IN_OP_LEN 4 */
8630 * restores the permanent (factory-programmed) MAC address associated with the
8631 * port. A non-zero MAC address persists until a PCIe reset or a power cycle.
8633 #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4
8645 /* MC_CMD_CLP_IN_OP_LEN 4 */
8647 * restores the permanent (factory-programmed) MAC address associated with the
8648 * port. A non-zero MAC address persists until a PCIe reset or a power cycle.
8650 #define MC_CMD_CLP_IN_SET_MAC_V2_ADDR_OFST 4
8656 #define MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_LEN 4
8659 #define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_WIDTH 1
8662 #define MC_CMD_CLP_IN_GET_MAC_LEN 4
8664 /* MC_CMD_CLP_IN_OP_LEN 4 */
8669 /* MC_CMD_CLP_IN_OP_LEN 4 */
8670 #define MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_OFST 4
8671 #define MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_LEN 4
8672 #define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_OFST 4
8674 #define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_WIDTH 1
8688 /* MC_CMD_CLP_IN_OP_LEN 4 */
8690 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4
8691 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1
8697 #define MC_CMD_CLP_IN_GET_BOOT_LEN 4
8699 /* MC_CMD_CLP_IN_OP_LEN 4 */
8702 #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4
8705 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1
8707 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1
8721 #define MC_CMD_MUM_IN_LEN 4
8723 #define MC_CMD_MUM_IN_OP_HDR_LEN 4
8761 #define MC_CMD_MUM_IN_NULL_LEN 4
8764 #define MC_CMD_MUM_IN_CMD_LEN 4
8767 #define MC_CMD_MUM_IN_GET_VERSION_LEN 4
8770 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8776 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8778 #define MC_CMD_MUM_IN_READ_DEVICE_OFST 4
8779 #define MC_CMD_MUM_IN_READ_DEVICE_LEN 4
8782 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */
8784 /* 32-bit address to read from */
8786 #define MC_CMD_MUM_IN_READ_ADDR_LEN 4
8789 #define MC_CMD_MUM_IN_READ_NUMWORDS_LEN 4
8795 #define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num))
8796 #define MC_CMD_MUM_IN_WRITE_BUFFER_NUM(len) (((len)-12)/4)
8799 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8801 #define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4
8802 #define MC_CMD_MUM_IN_WRITE_DEVICE_LEN 4
8805 /* 32-bit address to write to */
8807 #define MC_CMD_MUM_IN_WRITE_ADDR_LEN 4
8810 #define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4
8811 #define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1
8819 #define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num))
8820 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_NUM(len) (((len)-16)/1)
8823 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8825 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4
8826 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_LEN 4
8829 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_LEN 4
8832 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_LEN 4
8835 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1
8836 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1
8844 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8845 #define MC_CMD_MUM_IN_LOG_OP_OFST 4
8846 #define MC_CMD_MUM_IN_LOG_OP_LEN 4
8852 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8853 /* MC_CMD_MUM_IN_LOG_OP_OFST 4 */
8854 /* MC_CMD_MUM_IN_LOG_OP_LEN 4 */
8857 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_LEN 4
8863 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8864 #define MC_CMD_MUM_IN_GPIO_HDR_OFST 4
8865 #define MC_CMD_MUM_IN_GPIO_HDR_LEN 4
8866 #define MC_CMD_MUM_IN_GPIO_OPCODE_OFST 4
8879 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8880 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4
8881 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_LEN 4
8886 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8887 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4
8888 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_LEN 4
8889 /* The first 32-bit word to be written to the GPIO OUT register. */
8891 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_LEN 4
8892 /* The second 32-bit word to be written to the GPIO OUT register. */
8894 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_LEN 4
8899 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8900 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4
8901 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_LEN 4
8906 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8907 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4
8908 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_LEN 4
8909 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */
8911 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_LEN 4
8912 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */
8914 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_LEN 4
8919 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8920 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4
8921 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_LEN 4
8926 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8927 #define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4
8928 #define MC_CMD_MUM_IN_GPIO_OP_HDR_LEN 4
8929 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_OFST 4
8936 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_OFST 4
8943 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8944 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4
8945 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_LEN 4
8950 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8951 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4
8952 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 4
8953 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_OFST 4
8960 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8961 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4
8962 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 4
8963 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_OFST 4
8970 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8971 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4
8972 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 4
8973 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_OFST 4
8981 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8982 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4
8983 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 4
8984 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_OFST 4
8987 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_OFST 4
8995 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8996 /* Bit-mask of clocks to be programmed */
8997 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4
8998 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_LEN 4
9004 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 4
9007 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1
9009 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1
9010 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1
9013 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1
9019 /* MC_CMD_MUM_IN_CMD_LEN 4 */
9021 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4
9022 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_LEN 4
9025 #define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4
9028 /* MC_CMD_MUM_IN_CMD_LEN 4 */
9034 /* MC_CMD_MUM_IN_CMD_LEN 4 */
9035 #define MC_CMD_MUM_IN_QSFP_HDR_OFST 4
9036 #define MC_CMD_MUM_IN_QSFP_HDR_LEN 4
9037 #define MC_CMD_MUM_IN_QSFP_OPCODE_OFST 4
9039 #define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4
9047 #define MC_CMD_MUM_IN_QSFP_IDX_LEN 4
9052 /* MC_CMD_MUM_IN_CMD_LEN 4 */
9053 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4
9054 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_LEN 4
9056 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_LEN 4
9058 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_LEN 4
9063 /* MC_CMD_MUM_IN_CMD_LEN 4 */
9064 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4
9065 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_LEN 4
9067 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_LEN 4
9069 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_LEN 4
9071 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_LEN 4
9073 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_LEN 4
9078 /* MC_CMD_MUM_IN_CMD_LEN 4 */
9079 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4
9080 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_LEN 4
9082 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_LEN 4
9087 /* MC_CMD_MUM_IN_CMD_LEN 4 */
9088 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4
9089 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_LEN 4
9091 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_LEN 4
9093 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_LEN 4
9098 /* MC_CMD_MUM_IN_CMD_LEN 4 */
9099 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4
9100 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_LEN 4
9102 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_LEN 4
9107 /* MC_CMD_MUM_IN_CMD_LEN 4 */
9108 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4
9109 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_LEN 4
9111 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_LEN 4
9114 #define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4
9117 /* MC_CMD_MUM_IN_CMD_LEN 4 */
9128 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_LEN 4
9129 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4
9131 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4
9132 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_LEN 4
9136 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_LEN 4
9141 #define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1
9144 #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num))
9145 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_NUM(len) (((len)-0)/1)
9148 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1
9149 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1
9154 #define MC_CMD_MUM_OUT_READ_LENMIN 4
9157 #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num))
9158 #define MC_CMD_MUM_OUT_READ_BUFFER_NUM(len) (((len)-0)/4)
9160 #define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4
9161 #define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1
9176 /* The first 32-bit word read from the GPIO IN register. */
9178 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_LEN 4
9179 /* The second 32-bit word read from the GPIO IN register. */
9180 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4
9181 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_LEN 4
9188 /* The first 32-bit word read from the GPIO OUT register. */
9190 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_LEN 4
9191 /* The second 32-bit word read from the GPIO OUT register. */
9192 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4
9193 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_LEN 4
9201 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_LEN 4
9202 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4
9203 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_LEN 4
9206 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4
9208 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_LEN 4
9220 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4
9223 #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num))
9224 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_NUM(len) (((len)-0)/4)
9226 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4
9227 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1
9241 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4
9243 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_LEN 4
9249 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4
9251 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_LEN 4
9259 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 4
9260 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4
9261 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 4
9262 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_OFST 4
9264 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1
9265 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_OFST 4
9266 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1
9267 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1
9270 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4
9272 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_LEN 4
9278 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num))
9279 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_NUM(len) (((len)-4)/1)
9282 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 4
9283 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4
9284 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1
9285 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1
9292 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_LEN 4
9293 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4
9294 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_LEN 4
9297 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4
9299 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_LEN 4
9306 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_NUM(len) (((len)-8)/8)
9309 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4
9317 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4
9318 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_LEN 4
9323 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_LEN 4
9327 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_LEN 4
9336 /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */
9347 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4
9350 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4
9355 /* enum: Values 5-15 are reserved for future usage */
9365 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4
9391 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LEN 4
9395 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_OFST 4
9396 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LEN 4
9401 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LEN 4
9406 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LEN 4
9411 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LEN 4
9416 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LEN 4
9429 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LEN 4
9432 /* A human-readable name for the sensor (zero terminated string, max 32 bytes)
9434 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_OFST 4
9442 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LEN 4
9468 #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LEN 4
9472 #define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_OFST 4
9473 #define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LEN 4
9478 #define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LEN 4
9502 * MC_CMD_READ_SENSORS command. On multi-MC systems this may include sensors
9537 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LEN(num) (8+4*(num))
9538 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_NUM(len) (((len)-8)/4)
9543 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_LEN 4
9547 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_OFST 4
9548 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_LEN 4
9551 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_LEN 4
9579 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LEN(num) (0+4*(num))
9580 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_NUM(len) (((len)-0)/4)
9583 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_LEN 4
9593 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_NUM(len) (((len)-0)/64)
9628 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LEN(num) (0+4*(num))
9629 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_NUM(len) (((len)-0)/4)
9632 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_LEN 4
9642 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_NUM(len) (((len)-0)/12)
9665 #define MC_CMD_EVENT_CTRL_IN_LEN(num) (0+4*(num))
9666 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_NUM(len) (((len)-0)/4)
9669 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_LEN 4
9691 #define EVB_PORT_ID_LEN 4
9693 #define EVB_PORT_ID_PORT_ID_LEN 4
9700 /* enum: External network port 1 */
9715 #define EVB_VLAN_TAG_MODE_WIDTH 4
9733 /* the raw 64-bit address field from the SMC, not adjusted for page size */
9734 #define BUFTBL_ENTRY_RAWADDR_OFST 4
9736 #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4
9737 #define BUFTBL_ENTRY_RAWADDR_LO_LEN 4
9741 #define BUFTBL_ENTRY_RAWADDR_HI_LEN 4
9776 /* enum: Expansion ROM configuration data for port 1 */
9782 /* enum: Non-volatile log output partition */
9784 /* enum: Non-volatile log output partition for NMC firmware (this is
9788 /* enum: Non-volatile log output of second core on dual-core device */
9808 /* enum: Non-volatile log output partition for FC */
9810 /* enum: FPGA Stage 1 bitstream */
9832 /* enum: MUM Non-volatile log output partition. */
9834 /* enum: SUC Non-volatile log output partition (this is intentionally an alias
9852 /* enum: Non-volatile log output partition for Expansion ROM (this is
9868 /* enum: Spare partition 4 */
9889 * platforms. See SF-119124-PS. The STATIC_CONFIG partition may contain a
9899 /* enum: Bundle update non-volatile log output partition */
9903 /* enum: Partition to store ASN.1 format Bundle Signature for checking. */
9911 /* enum: System microcontroller access to primary System-on-Chip flash */
9913 /* enum: System microcontroller access to secondary System-on-Chip flash (if
9922 /* enum: System-on-Chip configuration information (see XN-200467-PS). */
9924 /* enum: System-on-Chip update information. */
9932 /* enum: Recovery Flash Partition Table, see SF-122606-TC. (this is
9938 /* enum: Flash Partition Table, see SF-122606-TC. (this is intentionally an
9946 #define LICENSED_APP_ID_LEN 4
9948 #define LICENSED_APP_ID_ID_LEN 4
9973 /* enum: Capture SolarSystem 1G */
9990 #define LICENSED_FEATURES_MASK_LO_LEN 4
9993 #define LICENSED_FEATURES_MASK_HI_OFST 4
9994 #define LICENSED_FEATURES_MASK_HI_LEN 4
9999 #define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1
10001 #define LICENSED_FEATURES_PIO_LBN 1
10002 #define LICENSED_FEATURES_PIO_WIDTH 1
10005 #define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1
10008 #define LICENSED_FEATURES_CLOCK_WIDTH 1
10010 #define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4
10011 #define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1
10014 #define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1
10017 #define LICENSED_FEATURES_RX_SNIFF_WIDTH 1
10020 #define LICENSED_FEATURES_TX_SNIFF_WIDTH 1
10023 #define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1
10026 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
10036 #define LICENSED_V3_APPS_MASK_LO_LEN 4
10039 #define LICENSED_V3_APPS_MASK_HI_OFST 4
10040 #define LICENSED_V3_APPS_MASK_HI_LEN 4
10045 #define LICENSED_V3_APPS_ONLOAD_WIDTH 1
10047 #define LICENSED_V3_APPS_PTP_LBN 1
10048 #define LICENSED_V3_APPS_PTP_WIDTH 1
10051 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1
10054 #define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1
10056 #define LICENSED_V3_APPS_PERF_MONITOR_LBN 4
10057 #define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1
10060 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1
10063 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1
10066 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1
10069 #define LICENSED_V3_APPS_TCP_DIRECT_WIDTH 1
10072 #define LICENSED_V3_APPS_LOW_LATENCY_WIDTH 1
10075 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1
10078 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1
10081 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 1
10084 #define LICENSED_V3_APPS_SCALEOUT_ONLOAD_WIDTH 1
10087 #define LICENSED_V3_APPS_DSHBRD_WIDTH 1
10090 #define LICENSED_V3_APPS_SCATRD_WIDTH 1
10100 #define LICENSED_V3_FEATURES_MASK_LO_LEN 4
10103 #define LICENSED_V3_FEATURES_MASK_HI_OFST 4
10104 #define LICENSED_V3_FEATURES_MASK_HI_LEN 4
10109 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1
10111 #define LICENSED_V3_FEATURES_PIO_LBN 1
10112 #define LICENSED_V3_FEATURES_PIO_WIDTH 1
10115 #define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1
10118 #define LICENSED_V3_FEATURES_CLOCK_WIDTH 1
10120 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4
10121 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1
10124 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1
10127 #define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1
10130 #define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1
10133 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1
10136 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
10150 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1
10172 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4
10178 #define RSS_MODE_LEN 1
10179 /* The RSS mode for a particular packet type is a value from 0 - 15 which can
10180 * be considered as 4 bits selecting which fields are included in the hash. (A
10183 * but only 4 bits are relevant.
10186 #define RSS_MODE_HASH_SELECTOR_LEN 1
10189 #define RSS_MODE_HASH_SRC_ADDR_WIDTH 1
10191 #define RSS_MODE_HASH_DST_ADDR_LBN 1
10192 #define RSS_MODE_HASH_DST_ADDR_WIDTH 1
10195 #define RSS_MODE_HASH_SRC_PORT_WIDTH 1
10198 #define RSS_MODE_HASH_DST_PORT_WIDTH 1
10203 #define CTPIO_STATS_MAP_LEN 4
10233 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr,
10237 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4
10244 * end with an address for each 4k of host memory required to back the EVQ.
10256 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_NUM(len) (((len)-36)/8)
10259 #define MC_CMD_INIT_EVQ_IN_SIZE_LEN 4
10261 * local queue index. The calling client must be the currently-assigned user of
10264 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4
10265 #define MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4
10269 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_LEN 4
10270 /* The reload value is ignored in one-shot modes */
10272 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_LEN 4
10275 #define MC_CMD_INIT_EVQ_IN_FLAGS_LEN 4
10278 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1
10280 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1
10281 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1
10284 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1
10287 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1
10289 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4
10290 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1
10293 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1
10296 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1
10298 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_LEN 4
10305 /* enum: Hold-off */
10309 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_LEN 4
10315 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_LEN 4
10318 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_LEN 4
10329 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_LEN 4
10330 /* 64-bit address of 4k of 4k-aligned host memory buffer */
10334 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_LEN 4
10338 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_LEN 4
10341 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1
10346 #define MC_CMD_INIT_EVQ_OUT_LEN 4
10349 #define MC_CMD_INIT_EVQ_OUT_IRQ_LEN 4
10356 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_NUM(len) (((len)-36)/8)
10359 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4
10361 * local queue index. The calling client must be the currently-assigned user of
10364 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4
10365 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4
10369 #define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_LEN 4
10370 /* The reload value is ignored in one-shot modes */
10372 #define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_LEN 4
10375 #define MC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 4
10378 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1
10380 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1
10381 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1
10384 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1
10387 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1
10389 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4
10390 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1
10393 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1
10396 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1
10399 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4
10403 * over-ridden by firmware based on licenses and firmware variant in order to
10409 * over-ridden by firmware based on licenses and firmware variant in order to
10414 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by
10421 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_WIDTH 1
10423 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 4
10430 /* enum: Hold-off */
10434 #define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_LEN 4
10440 #define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_LEN 4
10443 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_LEN 4
10454 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_LEN 4
10455 /* 64-bit address of 4k of 4k-aligned host memory buffer */
10459 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_LEN 4
10463 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_LEN 4
10466 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1
10474 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_LEN 4
10476 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4
10477 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 4
10478 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_OFST 4
10480 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1
10481 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_OFST 4
10482 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1
10483 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1
10484 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_OFST 4
10486 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1
10487 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_OFST 4
10489 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1
10491 /* MC_CMD_INIT_EVQ_V3_IN msgrequest: Extended request to specify per-queue
10497 #define MC_CMD_INIT_EVQ_V3_IN_SIZE_LEN 4
10499 * local queue index. The calling client must be the currently-assigned user of
10502 #define MC_CMD_INIT_EVQ_V3_IN_INSTANCE_OFST 4
10503 #define MC_CMD_INIT_EVQ_V3_IN_INSTANCE_LEN 4
10507 #define MC_CMD_INIT_EVQ_V3_IN_TMR_LOAD_LEN 4
10508 /* The reload value is ignored in one-shot modes */
10510 #define MC_CMD_INIT_EVQ_V3_IN_TMR_RELOAD_LEN 4
10513 #define MC_CMD_INIT_EVQ_V3_IN_FLAGS_LEN 4
10516 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_INTERRUPTING_WIDTH 1
10518 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_RPTR_DOS_LBN 1
10519 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_RPTR_DOS_WIDTH 1
10522 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_INT_ARMD_WIDTH 1
10525 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_CUT_THRU_WIDTH 1
10527 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_RX_MERGE_LBN 4
10528 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_RX_MERGE_WIDTH 1
10531 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_TX_MERGE_WIDTH 1
10534 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_USE_TIMER_WIDTH 1
10537 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_WIDTH 4
10541 * over-ridden by firmware based on licenses and firmware variant in order to
10547 * over-ridden by firmware based on licenses and firmware variant in order to
10552 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by
10559 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_EXT_WIDTH_WIDTH 1
10561 #define MC_CMD_INIT_EVQ_V3_IN_TMR_MODE_LEN 4
10568 /* enum: Hold-off */
10572 #define MC_CMD_INIT_EVQ_V3_IN_TARGET_EVQ_LEN 4
10578 #define MC_CMD_INIT_EVQ_V3_IN_IRQ_NUM_LEN 4
10581 #define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_LEN 4
10592 #define MC_CMD_INIT_EVQ_V3_IN_COUNT_THRSHLD_LEN 4
10593 /* 64-bit address of 4k of 4k-aligned host memory buffer */
10597 #define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_LO_LEN 4
10601 #define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_HI_LEN 4
10604 #define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_MINNUM 1
10609 * value. This field is ignored and per-queue merging is disabled if
10613 #define MC_CMD_INIT_EVQ_V3_IN_RX_MERGE_TIMEOUT_NS_LEN 4
10616 * value. This field is ignored and per-queue merging is disabled if
10620 #define MC_CMD_INIT_EVQ_V3_IN_TX_MERGE_TIMEOUT_NS_LEN 4
10626 #define MC_CMD_INIT_EVQ_V3_OUT_IRQ_LEN 4
10628 #define MC_CMD_INIT_EVQ_V3_OUT_FLAGS_OFST 4
10629 #define MC_CMD_INIT_EVQ_V3_OUT_FLAGS_LEN 4
10630 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_CUT_THRU_OFST 4
10632 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_CUT_THRU_WIDTH 1
10633 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RX_MERGE_OFST 4
10634 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RX_MERGE_LBN 1
10635 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RX_MERGE_WIDTH 1
10636 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_TX_MERGE_OFST 4
10638 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_TX_MERGE_WIDTH 1
10639 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RXQ_FORCE_EV_MERGING_OFST 4
10641 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1
10644 #define QUEUE_CRC_MODE_LEN 1
10646 #define QUEUE_CRC_MODE_MODE_WIDTH 4
10659 #define QUEUE_CRC_MODE_SPARE_LBN 4
10660 #define QUEUE_CRC_MODE_SPARE_WIDTH 4
10666 * arguments end with an address for each 4k of host memory required to back
10681 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)
10684 #define MC_CMD_INIT_RXQ_IN_SIZE_LEN 4
10687 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4
10688 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_LEN 4
10691 #define MC_CMD_INIT_RXQ_IN_LABEL_LEN 4
10693 * local queue index. The calling client must be the currently-assigned user of
10697 #define MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4
10700 #define MC_CMD_INIT_RXQ_IN_FLAGS_LEN 4
10703 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1
10705 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1
10706 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1
10709 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1
10712 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4
10715 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1
10718 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1
10721 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1
10724 #define MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1
10727 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_LEN 4
10728 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
10730 #define MC_CMD_INIT_RXQ_IN_PORT_ID_LEN 4
10731 /* 64-bit address of 4k of 4k-aligned host memory buffer */
10735 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_LEN 4
10739 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_LEN 4
10742 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1
10752 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 4
10756 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4
10757 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4
10763 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4
10765 * local queue index. The calling client must be the currently-assigned user of
10769 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4
10772 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 4
10775 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
10777 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1
10778 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1
10781 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
10784 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4
10787 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1
10790 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1
10793 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1
10796 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4
10802 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
10803 * multiple fixed-size packet buffers within each bucket. For a full
10804 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
10812 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
10823 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
10826 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
10829 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_WIDTH 1
10832 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4
10833 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
10835 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_LEN 4
10836 /* 64-bit address of 4k of 4k-aligned host memory buffer */
10840 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_LEN 4
10844 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_LEN 4
10852 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 4
10858 #define MC_CMD_INIT_RXQ_V3_IN_SIZE_LEN 4
10862 #define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_OFST 4
10863 #define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_LEN 4
10869 #define MC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 4
10871 * local queue index. The calling client must be the currently-assigned user of
10875 #define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 4
10878 #define MC_CMD_INIT_RXQ_V3_IN_FLAGS_LEN 4
10881 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_WIDTH 1
10883 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_LBN 1
10884 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_WIDTH 1
10887 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_WIDTH 1
10890 #define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_WIDTH 4
10893 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_WIDTH 1
10896 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_WIDTH 1
10899 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_WIDTH 1
10902 #define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 4
10908 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
10909 * multiple fixed-size packet buffers within each bucket. For a full
10910 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
10918 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
10929 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
10932 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
10935 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_WIDTH 1
10938 #define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 4
10939 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
10941 #define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_LEN 4
10942 /* 64-bit address of 4k of 4k-aligned host memory buffer */
10946 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_LEN 4
10950 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_LEN 4
10958 #define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_LEN 4
10964 #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
10971 #define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_LEN 4
10977 #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_LEN 4
10985 #define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
10993 #define MC_CMD_INIT_RXQ_V4_IN_SIZE_LEN 4
10997 #define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_OFST 4
10998 #define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_LEN 4
11004 #define MC_CMD_INIT_RXQ_V4_IN_LABEL_LEN 4
11006 * local queue index. The calling client must be the currently-assigned user of
11010 #define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_LEN 4
11013 #define MC_CMD_INIT_RXQ_V4_IN_FLAGS_LEN 4
11016 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_WIDTH 1
11018 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_LBN 1
11019 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_WIDTH 1
11022 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_WIDTH 1
11025 #define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_WIDTH 4
11028 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_WIDTH 1
11031 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_WIDTH 1
11034 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_WIDTH 1
11037 #define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_WIDTH 4
11043 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
11044 * multiple fixed-size packet buffers within each bucket. For a full
11045 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
11053 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
11064 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
11067 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
11070 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_WIDTH 1
11073 #define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_LEN 4
11074 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
11076 #define MC_CMD_INIT_RXQ_V4_IN_PORT_ID_LEN 4
11077 /* 64-bit address of 4k of 4k-aligned host memory buffer */
11081 #define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_LEN 4
11085 #define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_LEN 4
11093 #define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_LEN 4
11099 #define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
11106 #define MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_LEN 4
11112 #define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_LEN 4
11120 #define MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
11123 #define MC_CMD_INIT_RXQ_V4_IN_V4_DATA_LEN 4
11125 * to zero if using this message on non-QDMA based platforms. Currently in
11127 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a
11133 #define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_LEN 4
11141 #define MC_CMD_INIT_RXQ_V5_IN_SIZE_LEN 4
11145 #define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_OFST 4
11146 #define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_LEN 4
11152 #define MC_CMD_INIT_RXQ_V5_IN_LABEL_LEN 4
11154 * local queue index. The calling client must be the currently-assigned user of
11158 #define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_LEN 4
11161 #define MC_CMD_INIT_RXQ_V5_IN_FLAGS_LEN 4
11164 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_WIDTH 1
11166 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_LBN 1
11167 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_WIDTH 1
11170 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_WIDTH 1
11173 #define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_WIDTH 4
11176 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_WIDTH 1
11179 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_WIDTH 1
11182 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_WIDTH 1
11185 #define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_WIDTH 4
11191 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
11192 * multiple fixed-size packet buffers within each bucket. For a full
11193 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
11201 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
11212 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
11215 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
11218 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_WIDTH 1
11221 #define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_LEN 4
11222 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
11224 #define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_LEN 4
11225 /* 64-bit address of 4k of 4k-aligned host memory buffer */
11229 #define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_LEN 4
11233 #define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_LEN 4
11241 #define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_LEN 4
11247 #define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
11254 #define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_LEN 4
11260 #define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_LEN 4
11268 #define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
11271 #define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_LEN 4
11273 * to zero if using this message on non-QDMA based platforms. Currently in
11275 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a
11281 #define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_LEN 4
11288 #define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_LEN 4
11321 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)
11324 #define MC_CMD_INIT_TXQ_IN_SIZE_LEN 4
11328 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4
11329 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_LEN 4
11332 #define MC_CMD_INIT_TXQ_IN_LABEL_LEN 4
11334 * local queue index. The calling client must be the currently-assigned user of
11338 #define MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4
11341 #define MC_CMD_INIT_TXQ_IN_FLAGS_LEN 4
11344 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1
11346 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1
11347 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1
11350 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
11353 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
11355 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4
11356 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4
11359 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1
11362 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1
11365 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
11368 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
11371 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_LEN 4
11372 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
11374 #define MC_CMD_INIT_TXQ_IN_PORT_ID_LEN 4
11375 /* 64-bit address of 4k of 4k-aligned host memory buffer */
11379 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_LEN 4
11383 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_LEN 4
11386 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1
11396 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_LEN 4
11400 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4
11401 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_LEN 4
11404 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4
11406 * local queue index. The calling client must be the currently-assigned user of
11410 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4
11413 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 4
11416 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
11418 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1
11419 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1
11422 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
11425 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
11427 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4
11428 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4
11431 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
11434 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1
11437 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
11440 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
11443 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1
11446 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1
11449 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_WIDTH 1
11452 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_WIDTH 1
11455 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_WIDTH 1
11458 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_ABS_TARGET_EVQ_WIDTH 1
11461 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 4
11462 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
11464 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_LEN 4
11465 /* 64-bit address of 4k of 4k-aligned host memory buffer */
11469 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_LEN 4
11473 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_LEN 4
11481 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 4
11484 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1
11486 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1
11506 #define MC_CMD_FINI_EVQ_IN_LEN 4
11511 #define MC_CMD_FINI_EVQ_IN_INSTANCE_LEN 4
11527 #define MC_CMD_FINI_RXQ_IN_LEN 4
11530 #define MC_CMD_FINI_RXQ_IN_INSTANCE_LEN 4
11546 #define MC_CMD_FINI_TXQ_IN_LEN 4
11549 #define MC_CMD_FINI_TXQ_IN_INSTANCE_LEN 4
11568 #define MC_CMD_DRIVER_EVENT_IN_EVQ_LEN 4
11569 /* Bits 0 - 63 of event */
11570 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4
11572 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4
11573 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_LEN 4
11577 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_LEN 4
11598 #define MC_CMD_PROXY_CMD_IN_LEN 4
11601 #define MC_CMD_PROXY_CMD_IN_TARGET_LEN 4
11619 #define MC_PROXY_STATUS_BUFFER_HANDLE_LEN 4
11625 #define MC_PROXY_STATUS_BUFFER_PF_OFST 4
11650 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LEN 4
11668 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_LEN 4
11671 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1
11675 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4
11677 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4
11678 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_LEN 4
11682 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_LEN 4
11687 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_LEN 4
11694 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_LEN 4
11698 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_LEN 4
11703 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_LEN 4
11711 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_LEN 4
11715 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_LEN 4
11720 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_LEN 4
11723 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_LEN 4
11731 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_LEN 4
11734 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1
11738 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4
11740 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4
11741 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_LEN 4
11745 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_LEN 4
11750 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_LEN 4
11757 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_LEN 4
11761 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_LEN 4
11766 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_LEN 4
11774 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_LEN 4
11778 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_LEN 4
11783 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_LEN 4
11786 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_LEN 4
11791 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_LEN 4
11812 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_LEN 4
11813 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4
11814 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_LEN 4
11830 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_LEN 4
11851 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_LEN 4
11855 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4
11856 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_LEN 4
11861 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_LEN 4
11862 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4
11863 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_LEN 4
11866 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_LEN 4
11883 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_NUM(len) (((len)-12)/8)
11885 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_LEN 4
11887 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4
11888 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4
11891 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4
11896 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_LEN 4
11900 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_LEN 4
11903 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1
11920 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4
11922 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_LEN 4
11941 #define MC_CMD_FILTER_OP_IN_OP_LEN 4
11942 /* enum: single-recipient filter insert */
11944 /* enum: single-recipient filter remove */
11946 /* enum: multi-recipient filter subscribe */
11948 /* enum: multi-recipient filter unsubscribe */
11950 /* enum: replace one recipient with another (warning - the filter handle may
11955 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
11957 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4
11958 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_LEN 4
11962 #define MC_CMD_FILTER_OP_IN_HANDLE_HI_LEN 4
11965 /* The port ID associated with the v-adaptor which should contain this filter.
11968 #define MC_CMD_FILTER_OP_IN_PORT_ID_LEN 4
11971 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 4
11974 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1
11976 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1
11977 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1
11980 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1
11983 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1
11985 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4
11986 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1
11989 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1
11992 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1
11995 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1
11998 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1
12001 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1
12004 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1
12007 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1
12010 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_WIDTH 1
12013 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
12016 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
12019 #define MC_CMD_FILTER_OP_IN_RX_DEST_LEN 4
12028 /* enum: loop back to TXDP 1 */
12032 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 4
12035 #define MC_CMD_FILTER_OP_IN_RX_MODE_LEN 4
12040 /* enum: receive to multiple queues using .1p mapping */
12045 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
12050 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_LEN 4
12053 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_LEN 4
12059 #define MC_CMD_FILTER_OP_IN_TX_DEST_LEN 4
12064 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1
12066 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1
12067 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1
12094 #define MC_CMD_FILTER_OP_IN_FWDEF0_LEN 4
12095 /* Firmware defined register 1 to match (reserved; set to 0) */
12097 #define MC_CMD_FILTER_OP_IN_FWDEF1_LEN 4
12116 #define MC_CMD_FILTER_OP_EXT_IN_OP_LEN 4
12120 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4
12122 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4
12123 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_LEN 4
12127 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_LEN 4
12130 /* The port ID associated with the v-adaptor which should contain this filter.
12133 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_LEN 4
12136 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 4
12139 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1
12141 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1
12142 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1
12145 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1
12148 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1
12150 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4
12151 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1
12154 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1
12157 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1
12160 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1
12163 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1
12166 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1
12169 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1
12172 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1
12175 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1
12178 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1
12181 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1
12184 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1
12187 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1
12190 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1
12193 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1
12196 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1
12199 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1
12202 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1
12205 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1
12208 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1
12211 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1
12214 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1
12217 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_WIDTH 1
12220 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
12223 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
12226 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 4
12235 /* enum: loop back to TXDP 1 */
12239 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 4
12242 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 4
12247 /* enum: receive to multiple queues using .1p mapping */
12252 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
12257 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_LEN 4
12260 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_LEN 4
12266 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4
12271 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1
12273 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1
12274 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1
12301 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_LEN 4
12304 * VXLAN/NVGRE, or 1 for Geneve)
12307 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 4
12377 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_LEN 4
12378 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set
12382 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_LEN 4
12404 #define MC_CMD_FILTER_OP_V3_IN_OP_LEN 4
12408 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 4
12410 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 4
12411 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_LEN 4
12415 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_LEN 4
12418 /* The port ID associated with the v-adaptor which should contain this filter.
12421 #define MC_CMD_FILTER_OP_V3_IN_PORT_ID_LEN 4
12424 #define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_LEN 4
12427 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_WIDTH 1
12429 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_LBN 1
12430 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_WIDTH 1
12433 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_WIDTH 1
12436 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_WIDTH 1
12438 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_LBN 4
12439 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_WIDTH 1
12442 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_WIDTH 1
12445 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_WIDTH 1
12448 #define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_WIDTH 1
12451 #define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_WIDTH 1
12454 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_WIDTH 1
12457 #define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_WIDTH 1
12460 #define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_WIDTH 1
12463 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_WIDTH 1
12466 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_WIDTH 1
12469 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_WIDTH 1
12472 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_WIDTH 1
12475 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_WIDTH 1
12478 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_WIDTH 1
12481 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1
12484 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1
12487 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1
12490 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_WIDTH 1
12493 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_WIDTH 1
12496 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_WIDTH 1
12499 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1
12502 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1
12505 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_WIDTH 1
12508 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
12511 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
12514 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_LEN 4
12523 /* enum: loop back to TXDP 1 */
12527 #define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_LEN 4
12530 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_LEN 4
12535 /* enum: receive to multiple queues using .1p mapping */
12540 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
12545 #define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_LEN 4
12548 #define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_LEN 4
12554 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 4
12559 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_WIDTH 1
12561 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_LBN 1
12562 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_WIDTH 1
12589 #define MC_CMD_FILTER_OP_V3_IN_FWDEF0_LEN 4
12592 * VXLAN/NVGRE, or 1 for Geneve)
12595 #define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_LEN 4
12665 #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_LEN 4
12666 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set
12670 #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_LEN 4
12683 * (req.MATCH_BITOR_FLAG == 1) user_flag = req.MATCH_SET_FLAG bit_or user_flag;
12685 * = 0; else if (req.MATCH_BITOR_MARK == 1) user_mark = req.MATCH_SET_MARK
12692 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAGS_LEN 4
12695 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_FLAG_WIDTH 1
12697 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_MARK_LBN 1
12698 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_MARK_WIDTH 1
12701 #define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_FLAG_WIDTH 1
12704 #define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_WIDTH 1
12706 #define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_LBN 4
12707 #define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_WIDTH 1
12709 * functionality of this field in an ABI-backwards-compatible manner, and
12714 * Firmware Driver Interface (SF-119419-TC). Requesting anything other than
12719 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_LEN 4
12737 #define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_LEN 4
12743 #define MC_CMD_FILTER_OP_OUT_OP_LEN 4
12750 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4
12752 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4
12753 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_LEN 4
12757 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_LEN 4
12769 #define MC_CMD_FILTER_OP_EXT_OUT_OP_LEN 4
12776 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4
12778 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4
12779 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_LEN 4
12783 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_LEN 4
12792 * Get information related to the parser-dispatcher subsystem
12800 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4
12803 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 4
12810 /* enum: read properties relating to security rules (Medford-only; for use by
12811 * SolarSecure apps, not directly by drivers. See SF-114946-SW.)
12830 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num))
12831 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)
12834 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 4
12838 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4
12839 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_LEN 4
12844 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4
12853 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_LEN 4
12857 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4
12858 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 4
12859 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_OFST 4
12861 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1
12872 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LEN(num) (8+4*(num))
12873 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)
12876 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_LEN 4
12880 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_OFST 4
12881 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_LEN 4
12886 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_LEN 4
12897 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_OP_LEN 4
12900 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPES_SUPPORTED_OFST 4
12901 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPES_SUPPORTED_LEN 4
12902 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_VXLAN_OFST 4
12904 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_VXLAN_WIDTH 1
12905 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_NVGRE_OFST 4
12906 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_NVGRE_LBN 1
12907 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_NVGRE_WIDTH 1
12908 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_GENEVE_OFST 4
12910 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_GENEVE_WIDTH 1
12911 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_L2GRE_OFST 4
12913 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_L2GRE_WIDTH 1
12918 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging.
12934 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_LEN 4
12954 #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4
12955 #define MC_CMD_PARSER_DISP_RW_IN_OP_LEN 4
12962 /* enum: Read-modify-write a word of DICPU DMEM (not valid for LUE). Not
12968 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_LEN 4
12971 #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_LEN 4
12976 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_LEN 4
12977 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */
12979 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_LEN 4
12980 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */
12982 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_LEN 4
12985 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_LEN 4
12994 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_LEN 4
12998 /* up to 8 32-bit words of additional soft state from the LUE manager (the
12999 * exact content is firmware-dependent and intended only for debug use)
13005 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4
13006 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4
13024 #define MC_CMD_GET_PF_COUNT_OUT_LEN 1
13027 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1
13037 #define MC_CMD_SET_PF_COUNT_IN_LEN 4
13040 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_LEN 4
13059 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4
13063 * sense - e.g. virtio-blk), in which case the return value is NULL_PORT.
13066 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4
13081 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4
13084 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_LEN 4
13103 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_LEN 4
13105 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4
13106 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_LEN 4
13108 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request.
13114 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_LEN 4
13118 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4
13119 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_LEN 4
13125 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_LEN 4
13129 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4
13130 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_LEN 4
13133 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 4
13169 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_LEN 4
13171 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4
13172 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 4
13174 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 4
13177 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1
13180 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_LEN 4
13183 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 4
13199 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_LEN 4
13201 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4
13202 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 4
13204 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 4
13207 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1
13212 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_LEN 4
13217 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_LEN 4
13241 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_LEN 4
13245 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4
13246 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_LEN 4
13249 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_LEN 4
13264 #define MC_CMD_DUMP_VI_STATE_IN_LEN 4
13267 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4
13278 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4
13293 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_LEN 4
13297 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_LEN 4
13304 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_LEN 4
13308 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_LEN 4
13313 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4
13327 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_LEN 4
13331 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_LEN 4
13338 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_LEN 4
13342 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_LEN 4
13349 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_LEN 4
13353 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_LEN 4
13360 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_LEN 4
13364 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_LEN 4
13386 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_LEN 4
13390 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_LEN 4
13397 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_LEN 4
13401 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_LEN 4
13408 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_LEN 4
13412 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_LEN 4
13419 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_LEN 4
13423 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_LEN 4
13440 #define MC_CMD_DUMP_VI_STATE_OUT_USER_CLIENT_ID_LEN 4
13456 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4
13459 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_LEN 4
13472 #define MC_CMD_FREE_PIOBUF_IN_LEN 4
13475 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
13484 * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or
13493 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4
13496 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4
13499 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4
13500 /* Transaction processing steering hint 1 for use with the Rx Queue. */
13502 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1
13504 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1
13505 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1
13508 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1
13511 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1
13514 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1
13517 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1
13519 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_LEN 4
13525 * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or
13537 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4
13538 /* Transaction processing steering hint 1 for use with the Rx Queue. */
13539 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4
13540 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1
13543 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1
13546 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1
13549 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1
13552 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1
13555 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1
13556 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4
13557 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_LEN 4
13573 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4
13575 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4
13588 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_LEN 4
13592 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4
13593 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_LEN 4
13594 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_OFST 4
13596 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1
13597 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_OFST 4
13598 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1
13600 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_OFST 4
13602 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1
13603 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_OFST 4
13604 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1
13605 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1
13606 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_OFST 4
13608 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1
13609 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_OFST 4
13611 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1
13612 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_OFST 4
13613 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4
13615 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_OFST 4
13617 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1
13618 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_OFST 4
13619 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1
13620 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1
13621 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_OFST 4
13623 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1
13624 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_OFST 4
13627 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_OFST 4
13630 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_OFST 4
13633 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_OFST 4
13634 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4
13636 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_OFST 4
13639 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_OFST 4
13642 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_OFST 4
13659 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4
13663 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4
13664 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_LEN 4
13665 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_OFST 4
13667 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1
13668 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_OFST 4
13670 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1
13671 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_OFST 4
13672 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1
13673 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1
13674 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_OFST 4
13676 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1
13677 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_OFST 4
13679 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1
13680 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_OFST 4
13682 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1
13683 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_OFST 4
13684 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1
13685 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1
13686 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_OFST 4
13688 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1
13689 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_OFST 4
13692 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_OFST 4
13695 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_OFST 4
13696 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4
13698 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_OFST 4
13701 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_OFST 4
13704 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_OFST 4
13724 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0.
13726 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download
13728 * be a checksum (a simple 32-bit sum) of the transferred data. An individual
13731 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15),
13734 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0.
13742 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num))
13743 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_NUM(len) (((len)-16)/4)
13748 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_LEN 4
13757 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4
13758 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_LEN 4
13791 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */
13795 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LEN 4
13802 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_LEN 4
13805 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4
13806 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1
13814 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_LEN 4
13816 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4
13817 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_LEN 4
13855 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 4
13858 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1
13860 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4
13861 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1
13864 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1
13867 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
13870 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
13873 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
13876 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1
13879 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
13882 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
13885 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
13888 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
13891 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1
13894 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
13897 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1
13900 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1
13903 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1
13906 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1
13909 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1
13912 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1
13915 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1
13918 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1
13921 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1
13924 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1
13927 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1
13930 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
13933 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1
13936 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
13939 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1
13942 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1
13944 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4
13958 /* enum: RXDP Test firmware image 1 */
13964 /* enum: RXDP Test firmware image 4 */
13993 /* enum: TXDP Test firmware image 1 */
14006 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14007 /* enum: reserved value - do not use (may indicate alternative interpretation
14018 /* enum: RX PD firmware with approximately Siena-compatible behaviour
14040 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14057 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14058 /* enum: reserved value - do not use (may indicate alternative interpretation
14069 /* enum: TX PD firmware with approximately Siena-compatible behaviour
14088 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14096 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_LEN 4
14099 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_LEN 4
14108 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 4
14111 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1
14113 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4
14114 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1
14117 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1
14120 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
14123 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
14126 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
14129 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1
14132 …efine MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
14135 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
14138 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
14141 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
14144 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1
14147 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
14150 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1
14153 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1
14156 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1
14159 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1
14162 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1
14165 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1
14168 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1
14171 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1
14174 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1
14177 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1
14180 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1
14183 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
14186 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1
14189 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
14192 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1
14195 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1
14197 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4
14211 /* enum: RXDP Test firmware image 1 */
14217 /* enum: RXDP Test firmware image 4 */
14246 /* enum: TXDP Test firmware image 1 */
14259 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14260 /* enum: reserved value - do not use (may indicate alternative interpretation
14271 /* enum: RX PD firmware with approximately Siena-compatible behaviour
14293 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14310 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14311 /* enum: reserved value - do not use (may indicate alternative interpretation
14322 /* enum: TX PD firmware with approximately Siena-compatible behaviour
14341 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14349 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_LEN 4
14352 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_LEN 4
14355 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 4
14358 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1
14360 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1
14361 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1
14364 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1
14367 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1
14369 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4
14370 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1
14373 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
14376 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
14379 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
14382 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1
14385 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
14388 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 1
14391 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 1
14394 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 1
14397 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
14400 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_WIDTH 1
14403 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 1
14406 #define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_WIDTH 1
14409 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_WIDTH 1
14412 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_WIDTH 1
14415 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
14418 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_WIDTH 1
14421 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_WIDTH 1
14424 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
14427 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
14430 #define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_WIDTH 1
14433 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
14436 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_WIDTH 1
14439 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_WIDTH 1
14442 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
14445 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
14448 #define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_WIDTH 1
14451 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_WIDTH 1
14454 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_WIDTH 1
14457 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
14459 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
14468 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
14487 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1
14496 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4
14501 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1
14506 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1
14518 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 4
14521 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1
14523 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4
14524 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 1
14527 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 1
14530 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
14533 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
14536 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
14539 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 1
14542 …efine MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
14545 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
14548 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
14551 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
14554 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 1
14557 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
14560 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 1
14563 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 1
14566 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 1
14569 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 1
14572 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 1
14575 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 1
14578 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 1
14581 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 1
14584 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 1
14587 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 1
14590 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 1
14593 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
14596 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 1
14599 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
14602 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 1
14605 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 1
14607 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4
14621 /* enum: RXDP Test firmware image 1 */
14627 /* enum: RXDP Test firmware image 4 */
14656 /* enum: TXDP Test firmware image 1 */
14669 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14670 /* enum: reserved value - do not use (may indicate alternative interpretation
14681 /* enum: RX PD firmware with approximately Siena-compatible behaviour
14703 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14720 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14721 /* enum: reserved value - do not use (may indicate alternative interpretation
14732 /* enum: TX PD firmware with approximately Siena-compatible behaviour
14751 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14759 #define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_LEN 4
14762 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_LEN 4
14765 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 4
14768 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1
14770 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1
14771 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 1
14774 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 1
14777 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 1
14779 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4
14780 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 1
14783 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
14786 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
14789 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
14792 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 1
14795 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
14798 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 1
14801 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 1
14804 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 1
14807 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
14810 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_WIDTH 1
14813 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 1
14816 #define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_WIDTH 1
14819 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_WIDTH 1
14822 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_WIDTH 1
14825 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
14828 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_WIDTH 1
14831 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_WIDTH 1
14834 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
14837 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
14840 #define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_WIDTH 1
14843 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
14846 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_WIDTH 1
14849 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_WIDTH 1
14852 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
14855 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
14858 #define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_WIDTH 1
14861 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_WIDTH 1
14864 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_WIDTH 1
14867 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
14869 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
14878 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
14897 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 1
14906 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4
14911 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_LEN 1
14916 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_LEN 1
14925 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
14929 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_LEN 1
14930 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
14934 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
14936 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
14939 * (SF-115995-SW) in the present configuration of firmware and port mode.
14942 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
14944 * (SF-115995-SW) in the present configuration of firmware and port mode.
14953 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 4
14956 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_WIDTH 1
14958 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 4
14959 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_WIDTH 1
14962 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_WIDTH 1
14965 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
14968 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
14971 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
14974 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_WIDTH 1
14977 …efine MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
14980 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
14983 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
14986 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
14989 #define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_WIDTH 1
14992 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
14995 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_WIDTH 1
14998 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_WIDTH 1
15001 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_WIDTH 1
15004 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_WIDTH 1
15007 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_WIDTH 1
15010 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_WIDTH 1
15013 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_WIDTH 1
15016 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_WIDTH 1
15019 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_WIDTH 1
15022 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_WIDTH 1
15025 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_WIDTH 1
15028 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
15031 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_WIDTH 1
15034 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
15037 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_WIDTH 1
15040 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_WIDTH 1
15042 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_OFST 4
15056 /* enum: RXDP Test firmware image 1 */
15062 /* enum: RXDP Test firmware image 4 */
15091 /* enum: TXDP Test firmware image 1 */
15104 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
15105 /* enum: reserved value - do not use (may indicate alternative interpretation
15116 /* enum: RX PD firmware with approximately Siena-compatible behaviour
15138 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15155 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
15156 /* enum: reserved value - do not use (may indicate alternative interpretation
15167 /* enum: TX PD firmware with approximately Siena-compatible behaviour
15186 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15194 #define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_LEN 4
15197 #define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_LEN 4
15200 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 4
15203 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_WIDTH 1
15205 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_LBN 1
15206 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_WIDTH 1
15209 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_WIDTH 1
15212 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_WIDTH 1
15214 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 4
15215 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_WIDTH 1
15218 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
15221 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
15224 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
15227 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_WIDTH 1
15230 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
15233 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_WIDTH 1
15236 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_WIDTH 1
15239 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_WIDTH 1
15242 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
15245 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_WIDTH 1
15248 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_WIDTH 1
15251 #define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_WIDTH 1
15254 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_WIDTH 1
15257 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_WIDTH 1
15260 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
15263 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_WIDTH 1
15266 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_WIDTH 1
15269 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
15272 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
15275 #define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_WIDTH 1
15278 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
15281 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_WIDTH 1
15284 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_WIDTH 1
15287 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
15290 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
15293 #define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_WIDTH 1
15296 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_WIDTH 1
15299 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_WIDTH 1
15302 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
15304 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
15313 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
15332 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_LEN 1
15341 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 4
15346 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_LEN 1
15351 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_LEN 1
15360 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
15364 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_LEN 1
15365 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
15369 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
15371 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
15374 * (SF-115995-SW) in the present configuration of firmware and port mode.
15377 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
15379 * (SF-115995-SW) in the present configuration of firmware and port mode.
15385 * hold at least this many 64-bit stats values, if they wish to receive all
15396 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_LEN 4
15399 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_WIDTH 1
15401 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_LBN 4
15402 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_WIDTH 1
15405 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_WIDTH 1
15408 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
15411 #define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
15414 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
15417 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_WIDTH 1
15420 …efine MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
15423 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
15426 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
15429 #define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
15432 #define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_WIDTH 1
15435 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
15438 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_WIDTH 1
15441 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_WIDTH 1
15444 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_WIDTH 1
15447 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_WIDTH 1
15450 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_WIDTH 1
15453 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_WIDTH 1
15456 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_WIDTH 1
15459 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_WIDTH 1
15462 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_WIDTH 1
15465 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_WIDTH 1
15468 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_WIDTH 1
15471 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
15474 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_WIDTH 1
15477 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
15480 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_WIDTH 1
15483 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_WIDTH 1
15485 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_OFST 4
15499 /* enum: RXDP Test firmware image 1 */
15505 /* enum: RXDP Test firmware image 4 */
15534 /* enum: TXDP Test firmware image 1 */
15547 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
15548 /* enum: reserved value - do not use (may indicate alternative interpretation
15559 /* enum: RX PD firmware with approximately Siena-compatible behaviour
15581 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15598 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
15599 /* enum: reserved value - do not use (may indicate alternative interpretation
15610 /* enum: TX PD firmware with approximately Siena-compatible behaviour
15629 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15637 #define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_LEN 4
15640 #define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_LEN 4
15643 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_LEN 4
15646 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_WIDTH 1
15648 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_LBN 1
15649 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_WIDTH 1
15652 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_WIDTH 1
15655 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_WIDTH 1
15657 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_LBN 4
15658 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_WIDTH 1
15661 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
15664 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
15667 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
15670 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_WIDTH 1
15673 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
15676 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_WIDTH 1
15679 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_WIDTH 1
15682 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_WIDTH 1
15685 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
15688 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_WIDTH 1
15691 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_WIDTH 1
15694 #define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_WIDTH 1
15697 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_WIDTH 1
15700 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_WIDTH 1
15703 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
15706 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_WIDTH 1
15709 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_WIDTH 1
15712 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
15715 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
15718 #define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_WIDTH 1
15721 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
15724 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_WIDTH 1
15727 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_WIDTH 1
15730 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
15733 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
15736 #define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_WIDTH 1
15739 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_WIDTH 1
15742 #define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_WIDTH 1
15745 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
15747 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
15756 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
15775 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_LEN 1
15784 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_NUM 4
15789 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DESC_CACHE_SIZE_LEN 1
15794 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DESC_CACHE_SIZE_LEN 1
15803 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
15807 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_LEN 1
15808 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
15812 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
15814 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
15817 * (SF-115995-SW) in the present configuration of firmware and port mode.
15820 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
15822 * (SF-115995-SW) in the present configuration of firmware and port mode.
15828 * hold at least this many 64-bit stats values, if they wish to receive all
15835 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
15838 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_LEN 4
15844 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_LEN 4
15847 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_WIDTH 1
15849 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_LBN 4
15850 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_WIDTH 1
15853 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_WIDTH 1
15856 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
15859 #define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
15862 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
15865 #define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_WIDTH 1
15868 …efine MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
15871 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
15874 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
15877 #define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
15880 #define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_WIDTH 1
15883 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
15886 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_WIDTH 1
15889 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_WIDTH 1
15892 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_WIDTH 1
15895 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_WIDTH 1
15898 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_WIDTH 1
15901 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_WIDTH 1
15904 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_WIDTH 1
15907 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_WIDTH 1
15910 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_WIDTH 1
15913 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_WIDTH 1
15916 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_WIDTH 1
15919 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
15922 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_WIDTH 1
15925 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
15928 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_WIDTH 1
15931 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_WIDTH 1
15933 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_OFST 4
15947 /* enum: RXDP Test firmware image 1 */
15953 /* enum: RXDP Test firmware image 4 */
15982 /* enum: TXDP Test firmware image 1 */
15995 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
15996 /* enum: reserved value - do not use (may indicate alternative interpretation
16007 /* enum: RX PD firmware with approximately Siena-compatible behaviour
16029 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16046 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
16047 /* enum: reserved value - do not use (may indicate alternative interpretation
16058 /* enum: TX PD firmware with approximately Siena-compatible behaviour
16077 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16085 #define MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_LEN 4
16088 #define MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_LEN 4
16091 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_LEN 4
16094 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_WIDTH 1
16096 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_LBN 1
16097 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_WIDTH 1
16100 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_WIDTH 1
16103 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_WIDTH 1
16105 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_LBN 4
16106 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_WIDTH 1
16109 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
16112 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
16115 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
16118 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_WIDTH 1
16121 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
16124 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_WIDTH 1
16127 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_WIDTH 1
16130 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_WIDTH 1
16133 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
16136 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_WIDTH 1
16139 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_WIDTH 1
16142 #define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_WIDTH 1
16145 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_WIDTH 1
16148 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_WIDTH 1
16151 #define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
16154 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_WIDTH 1
16157 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_WIDTH 1
16160 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
16163 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
16166 #define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_WIDTH 1
16169 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
16172 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_WIDTH 1
16175 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_WIDTH 1
16178 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
16181 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
16184 #define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_WIDTH 1
16187 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_WIDTH 1
16190 #define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_WIDTH 1
16193 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
16195 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
16204 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
16223 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_LEN 1
16232 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_NUM 4
16237 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DESC_CACHE_SIZE_LEN 1
16242 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DESC_CACHE_SIZE_LEN 1
16251 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
16255 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_LEN 1
16256 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
16260 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
16262 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
16265 * (SF-115995-SW) in the present configuration of firmware and port mode.
16268 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
16270 * (SF-115995-SW) in the present configuration of firmware and port mode.
16276 * hold at least this many 64-bit stats values, if they wish to receive all
16283 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
16286 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_LEN 4
16296 #define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
16303 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_LEN 4
16306 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_WIDTH 1
16308 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_LBN 4
16309 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_WIDTH 1
16312 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_WIDTH 1
16315 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
16318 #define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
16321 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
16324 #define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_WIDTH 1
16327 …efine MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
16330 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
16333 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
16336 #define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
16339 #define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_WIDTH 1
16342 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
16345 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_WIDTH 1
16348 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_WIDTH 1
16351 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_WIDTH 1
16354 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_WIDTH 1
16357 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_WIDTH 1
16360 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_WIDTH 1
16363 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_WIDTH 1
16366 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_WIDTH 1
16369 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_WIDTH 1
16372 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_WIDTH 1
16375 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_WIDTH 1
16378 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
16381 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_WIDTH 1
16384 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
16387 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_WIDTH 1
16390 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_WIDTH 1
16392 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_OFST 4
16406 /* enum: RXDP Test firmware image 1 */
16412 /* enum: RXDP Test firmware image 4 */
16441 /* enum: TXDP Test firmware image 1 */
16454 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
16455 /* enum: reserved value - do not use (may indicate alternative interpretation
16466 /* enum: RX PD firmware with approximately Siena-compatible behaviour
16488 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16505 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
16506 /* enum: reserved value - do not use (may indicate alternative interpretation
16517 /* enum: TX PD firmware with approximately Siena-compatible behaviour
16536 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16544 #define MC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_LEN 4
16547 #define MC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_LEN 4
16550 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_LEN 4
16553 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_WIDTH 1
16555 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_LBN 1
16556 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_WIDTH 1
16559 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_WIDTH 1
16562 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_WIDTH 1
16564 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_LBN 4
16565 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_WIDTH 1
16568 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
16571 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
16574 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
16577 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_WIDTH 1
16580 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
16583 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_WIDTH 1
16586 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_WIDTH 1
16589 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_WIDTH 1
16592 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
16595 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_WIDTH 1
16598 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_WIDTH 1
16601 #define MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_WIDTH 1
16604 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_WIDTH 1
16607 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_WIDTH 1
16610 #define MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
16613 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_WIDTH 1
16616 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_WIDTH 1
16619 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
16622 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
16625 #define MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_WIDTH 1
16628 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
16631 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_WIDTH 1
16634 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_WIDTH 1
16637 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
16640 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
16643 #define MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_WIDTH 1
16646 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_WIDTH 1
16649 #define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_WIDTH 1
16652 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
16654 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
16663 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
16682 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_LEN 1
16691 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_NUM 4
16696 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DESC_CACHE_SIZE_LEN 1
16701 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DESC_CACHE_SIZE_LEN 1
16710 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
16714 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_LEN 1
16715 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
16719 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
16721 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
16724 * (SF-115995-SW) in the present configuration of firmware and port mode.
16727 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
16729 * (SF-115995-SW) in the present configuration of firmware and port mode.
16735 * hold at least this many 64-bit stats values, if they wish to receive all
16742 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
16745 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_LEN 4
16755 #define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
16759 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_LEN 4
16762 #define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_WIDTH 1
16764 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_LBN 1
16765 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_WIDTH 1
16768 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
16771 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_WIDTH 1
16773 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_LBN 4
16774 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_WIDTH 1
16777 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
16780 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
16783 #define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
16786 #define MC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
16789 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
16792 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
16795 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
16798 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1
16801 #define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1
16807 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_LEN 4
16810 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_WIDTH 1
16812 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_LBN 4
16813 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_WIDTH 1
16816 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_WIDTH 1
16819 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
16822 #define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
16825 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
16828 #define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_WIDTH 1
16831 …efine MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
16834 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
16837 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
16840 #define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
16843 #define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_WIDTH 1
16846 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
16849 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_WIDTH 1
16852 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_WIDTH 1
16855 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_WIDTH 1
16858 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_WIDTH 1
16861 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_WIDTH 1
16864 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_WIDTH 1
16867 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_WIDTH 1
16870 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_WIDTH 1
16873 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_WIDTH 1
16876 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_WIDTH 1
16879 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_WIDTH 1
16882 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
16885 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_WIDTH 1
16888 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
16891 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_WIDTH 1
16894 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_WIDTH 1
16896 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_OFST 4
16910 /* enum: RXDP Test firmware image 1 */
16916 /* enum: RXDP Test firmware image 4 */
16945 /* enum: TXDP Test firmware image 1 */
16958 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
16959 /* enum: reserved value - do not use (may indicate alternative interpretation
16970 /* enum: RX PD firmware with approximately Siena-compatible behaviour
16992 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
17009 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
17010 /* enum: reserved value - do not use (may indicate alternative interpretation
17021 /* enum: TX PD firmware with approximately Siena-compatible behaviour
17040 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
17048 #define MC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_LEN 4
17051 #define MC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_LEN 4
17054 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_LEN 4
17057 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_WIDTH 1
17059 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_LBN 1
17060 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_WIDTH 1
17063 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_WIDTH 1
17066 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_WIDTH 1
17068 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_LBN 4
17069 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_WIDTH 1
17072 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
17075 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
17078 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
17081 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_WIDTH 1
17084 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
17087 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_WIDTH 1
17090 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_WIDTH 1
17093 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_WIDTH 1
17096 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
17099 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_WIDTH 1
17102 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_WIDTH 1
17105 #define MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_WIDTH 1
17108 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_WIDTH 1
17111 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_WIDTH 1
17114 #define MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
17117 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_WIDTH 1
17120 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_WIDTH 1
17123 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
17126 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
17129 #define MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_WIDTH 1
17132 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
17135 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_WIDTH 1
17138 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_WIDTH 1
17141 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
17144 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
17147 #define MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_WIDTH 1
17150 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_WIDTH 1
17153 #define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_WIDTH 1
17156 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
17158 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
17167 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
17186 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_LEN 1
17195 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_NUM 4
17200 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DESC_CACHE_SIZE_LEN 1
17205 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DESC_CACHE_SIZE_LEN 1
17214 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
17218 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_LEN 1
17219 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
17223 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
17225 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
17228 * (SF-115995-SW) in the present configuration of firmware and port mode.
17231 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
17233 * (SF-115995-SW) in the present configuration of firmware and port mode.
17239 * hold at least this many 64-bit stats values, if they wish to receive all
17246 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
17249 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_LEN 4
17259 #define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
17263 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_LEN 4
17266 #define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_WIDTH 1
17268 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_LBN 1
17269 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_WIDTH 1
17272 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
17275 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_WIDTH 1
17277 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_LBN 4
17278 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_WIDTH 1
17281 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
17284 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
17287 #define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
17290 #define MC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
17293 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
17296 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
17299 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
17302 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1
17305 #define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1
17306 /* These bits are reserved for communicating test-specific capabilities to
17307 * host-side test software. All production drivers should treat this field as
17313 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_LEN 4
17317 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_LEN 4
17325 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_LEN 4
17328 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_WIDTH 1
17330 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_LBN 4
17331 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_WIDTH 1
17334 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_WIDTH 1
17337 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
17340 #define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
17343 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
17346 #define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_WIDTH 1
17349 …efine MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
17352 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
17355 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
17358 #define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
17361 #define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_WIDTH 1
17364 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
17367 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_WIDTH 1
17370 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_WIDTH 1
17373 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_WIDTH 1
17376 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_WIDTH 1
17379 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_WIDTH 1
17382 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_WIDTH 1
17385 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_WIDTH 1
17388 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_WIDTH 1
17391 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_WIDTH 1
17394 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_WIDTH 1
17397 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_WIDTH 1
17400 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
17403 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_WIDTH 1
17406 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
17409 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_WIDTH 1
17412 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_WIDTH 1
17414 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_OFST 4
17428 /* enum: RXDP Test firmware image 1 */
17434 /* enum: RXDP Test firmware image 4 */
17463 /* enum: TXDP Test firmware image 1 */
17476 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
17477 /* enum: reserved value - do not use (may indicate alternative interpretation
17488 /* enum: RX PD firmware with approximately Siena-compatible behaviour
17510 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
17527 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
17528 /* enum: reserved value - do not use (may indicate alternative interpretation
17539 /* enum: TX PD firmware with approximately Siena-compatible behaviour
17558 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
17566 #define MC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_LEN 4
17569 #define MC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_LEN 4
17572 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_LEN 4
17575 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_WIDTH 1
17577 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_LBN 1
17578 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_WIDTH 1
17581 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_WIDTH 1
17584 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_WIDTH 1
17586 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_LBN 4
17587 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_WIDTH 1
17590 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
17593 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
17596 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
17599 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_WIDTH 1
17602 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
17605 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_WIDTH 1
17608 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_WIDTH 1
17611 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_WIDTH 1
17614 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
17617 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_WIDTH 1
17620 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_WIDTH 1
17623 #define MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_WIDTH 1
17626 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_WIDTH 1
17629 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_WIDTH 1
17632 #define MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
17635 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_WIDTH 1
17638 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_WIDTH 1
17641 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
17644 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
17647 #define MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_WIDTH 1
17650 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
17653 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_WIDTH 1
17656 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_WIDTH 1
17659 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
17662 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
17665 #define MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_WIDTH 1
17668 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_WIDTH 1
17671 #define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_WIDTH 1
17674 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
17676 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
17685 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
17704 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_LEN 1
17713 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_NUM 4
17718 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DESC_CACHE_SIZE_LEN 1
17723 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DESC_CACHE_SIZE_LEN 1
17732 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
17736 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_LEN 1
17737 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
17741 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
17743 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
17746 * (SF-115995-SW) in the present configuration of firmware and port mode.
17749 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
17751 * (SF-115995-SW) in the present configuration of firmware and port mode.
17757 * hold at least this many 64-bit stats values, if they wish to receive all
17764 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
17767 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_LEN 4
17777 #define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
17781 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_LEN 4
17784 #define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_WIDTH 1
17786 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_LBN 1
17787 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_WIDTH 1
17790 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
17793 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_WIDTH 1
17795 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_LBN 4
17796 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_WIDTH 1
17799 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
17802 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
17805 #define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
17808 #define MC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
17811 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
17814 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
17817 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
17820 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1
17823 #define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1
17824 /* These bits are reserved for communicating test-specific capabilities to
17825 * host-side test software. All production drivers should treat this field as
17831 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_LEN 4
17835 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_LEN 4
17843 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
17849 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
17855 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
17856 /* The maximum number of queues that can be used by an RSS context in even-
17857 * spreading mode. In even-spreading mode the context has no indirection table
17861 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
17867 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_LEN 4
17872 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_LEN 4
17878 #define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS1_LEN 4
17881 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VPORT_RECONFIGURE_WIDTH 1
17883 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_STRIPING_LBN 4
17884 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_STRIPING_WIDTH 1
17887 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_QUERY_WIDTH 1
17890 #define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
17893 #define MC_CMD_GET_CAPABILITIES_V10_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
17896 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
17899 #define MC_CMD_GET_CAPABILITIES_V10_OUT_SET_MAC_ENHANCED_WIDTH 1
17902 …fine MC_CMD_GET_CAPABILITIES_V10_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
17905 …efine MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
17908 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
17911 #define MC_CMD_GET_CAPABILITIES_V10_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
17914 #define MC_CMD_GET_CAPABILITIES_V10_OUT_QBB_WIDTH 1
17917 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
17920 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_RSS_LIMITED_WIDTH 1
17923 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_WIDTH 1
17926 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_INCLUDE_FCS_WIDTH 1
17929 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VLAN_INSERTION_WIDTH 1
17932 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_WIDTH 1
17935 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_WIDTH 1
17938 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_0_WIDTH 1
17941 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_14_WIDTH 1
17944 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_TIMESTAMP_WIDTH 1
17947 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_BATCHING_WIDTH 1
17950 #define MC_CMD_GET_CAPABILITIES_V10_OUT_MCAST_FILTER_CHAINING_WIDTH 1
17953 #define MC_CMD_GET_CAPABILITIES_V10_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
17956 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DISABLE_SCATTER_WIDTH 1
17959 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
17962 #define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_WIDTH 1
17965 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VXLAN_NVGRE_WIDTH 1
17967 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DPCPU_FW_ID_OFST 4
17981 /* enum: RXDP Test firmware image 1 */
17987 /* enum: RXDP Test firmware image 4 */
18016 /* enum: TXDP Test firmware image 1 */
18029 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
18030 /* enum: reserved value - do not use (may indicate alternative interpretation
18041 /* enum: RX PD firmware with approximately Siena-compatible behaviour
18063 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
18080 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
18081 /* enum: reserved value - do not use (may indicate alternative interpretation
18092 /* enum: TX PD firmware with approximately Siena-compatible behaviour
18111 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
18119 #define MC_CMD_GET_CAPABILITIES_V10_OUT_HW_CAPABILITIES_LEN 4
18122 #define MC_CMD_GET_CAPABILITIES_V10_OUT_LICENSE_CAPABILITIES_LEN 4
18125 #define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS2_LEN 4
18128 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_WIDTH 1
18130 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_ENCAP_LBN 1
18131 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_ENCAP_WIDTH 1
18134 #define MC_CMD_GET_CAPABILITIES_V10_OUT_EVQ_TIMER_CTRL_WIDTH 1
18137 #define MC_CMD_GET_CAPABILITIES_V10_OUT_EVENT_CUT_THROUGH_WIDTH 1
18139 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_CUT_THROUGH_LBN 4
18140 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_CUT_THROUGH_WIDTH 1
18143 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
18146 #define MC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
18149 #define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
18152 #define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_V2_WIDTH 1
18155 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
18158 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TIMESTAMP_WIDTH 1
18161 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_SNIFF_WIDTH 1
18164 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_SNIFF_WIDTH 1
18167 #define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
18170 #define MC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_BACKGROUND_WIDTH 1
18173 #define MC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_DB_RETURN_WIDTH 1
18176 #define MC_CMD_GET_CAPABILITIES_V10_OUT_CTPIO_WIDTH 1
18179 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TSA_SUPPORT_WIDTH 1
18182 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TSA_BOUND_WIDTH 1
18185 #define MC_CMD_GET_CAPABILITIES_V10_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
18188 #define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_FLAG_WIDTH 1
18191 #define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_WIDTH 1
18194 #define MC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
18197 #define MC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
18200 #define MC_CMD_GET_CAPABILITIES_V10_OUT_L3XUDP_SUPPORT_WIDTH 1
18203 #define MC_CMD_GET_CAPABILITIES_V10_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
18206 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_SPREADING_WIDTH 1
18209 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_HLB_IDLE_WIDTH 1
18212 #define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
18215 #define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
18218 #define MC_CMD_GET_CAPABILITIES_V10_OUT_BUNDLE_UPDATE_WIDTH 1
18221 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V3_WIDTH 1
18224 #define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_SENSORS_WIDTH 1
18227 #define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
18229 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
18238 #define MC_CMD_GET_CAPABILITIES_V10_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
18257 #define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VFS_PER_PF_LEN 1
18266 #define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_NUM 4
18271 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DESC_CACHE_SIZE_LEN 1
18276 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_DESC_CACHE_SIZE_LEN 1
18285 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
18289 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_LEN 1
18290 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
18294 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
18296 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
18299 * (SF-115995-SW) in the present configuration of firmware and port mode.
18302 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
18304 * (SF-115995-SW) in the present configuration of firmware and port mode.
18310 * hold at least this many 64-bit stats values, if they wish to receive all
18317 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
18320 #define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_MAX_LEN 4
18330 #define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
18334 #define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS3_LEN 4
18337 #define MC_CMD_GET_CAPABILITIES_V10_OUT_WOL_ETHERWAKE_WIDTH 1
18339 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_EVEN_SPREADING_LBN 1
18340 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_EVEN_SPREADING_WIDTH 1
18343 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
18346 #define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_SUPPORTED_WIDTH 1
18348 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VDPA_SUPPORTED_LBN 4
18349 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VDPA_SUPPORTED_WIDTH 1
18352 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
18355 #define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
18358 #define MC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
18361 #define MC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
18364 #define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
18367 #define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
18370 #define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
18373 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1
18376 #define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1
18377 /* These bits are reserved for communicating test-specific capabilities to
18378 * host-side test software. All production drivers should treat this field as
18384 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_LEN 4
18388 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_LEN 4
18396 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
18402 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
18408 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
18409 /* The maximum number of queues that can be used by an RSS context in even-
18410 * spreading mode. In even-spreading mode the context has no indirection table
18414 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
18420 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_NUM_CONTEXTS_LEN 4
18425 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_TABLE_POOL_SIZE_LEN 4
18433 #define MC_CMD_GET_CAPABILITIES_V10_OUT_SUPPORTED_QUEUE_SIZES_LEN 4
18439 #define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_QUEUE_SIZES_LEN 4
18449 #define MC_CMD_V2_EXTN_IN_LEN 4
18454 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1
18464 #define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4
18486 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4
18489 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_LEN 4
18502 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4
18505 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_LEN 4
18524 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_LEN 4
18526 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4
18527 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_LEN 4
18533 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_LEN 4
18535 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4
18536 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_LEN 4
18539 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_LEN 4
18558 #define MC_CMD_TCM_TXQ_INIT_IN_QID_LEN 4
18560 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4
18561 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_LEN 4
18564 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_LEN 4
18567 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1
18569 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1
18570 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1
18573 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1
18576 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_LEN 4
18581 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_LEN 4
18586 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_LEN 4
18589 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_LEN 4
18595 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_LEN 4
18597 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4
18598 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_LEN 4
18601 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_LEN 4
18604 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1
18606 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1
18607 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1
18610 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1
18613 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_LEN 4
18618 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_LEN 4
18623 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_LEN 4
18626 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_LEN 4
18629 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_LEN 4
18648 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
18650 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4
18651 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
18667 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4
18670 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
18678 * allocate and initialise a v-switch.
18687 /* The port to connect to the v-switch's upstream port. */
18689 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
18690 /* The type of v-switch to create. */
18691 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4
18692 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_LEN 4
18703 /* Flags controlling v-port creation */
18705 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 4
18708 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
18709 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators,
18710 * this must be one or greated, and the attached v-ports must have exactly this
18711 * number of tags. For other v-switch types, this must be zero of greater, and
18712 * is an upper limit on the number of VLAN tags for attached v-ports. An error
18714 * v-ports with this number of tags.
18717 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
18725 * de-allocate a v-switch.
18733 #define MC_CMD_VSWITCH_FREE_IN_LEN 4
18734 /* The port to which the v-switch is connected. */
18736 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_LEN 4
18744 * read some config of v-switch. For now this command is an empty placeholder.
18745 * It may be used to check if a v-switch is connected to a given EVB port (if
18754 #define MC_CMD_VSWITCH_QUERY_IN_LEN 4
18755 /* The port to which the v-switch is connected. */
18757 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_LEN 4
18765 * allocate a v-port.
18774 /* The port to which the v-switch is connected. */
18776 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
18777 /* The type of the new v-port. */
18778 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4
18779 #define MC_CMD_VPORT_ALLOC_IN_TYPE_LEN 4
18786 /* enum: A normal v-port receives packets which match a specified MAC and/or
18790 /* enum: An expansion v-port packets traffic which don't match any other
18791 * v-port.
18794 /* enum: An test v-port receives packets which match any filters installed by
18798 /* Flags controlling v-port creation */
18800 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 4
18803 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
18805 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1
18806 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1
18809 * v-switch.
18812 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
18815 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 4
18824 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4
18825 /* The handle of the new v-port */
18827 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_LEN 4
18832 * de-allocate a v-port.
18840 #define MC_CMD_VPORT_FREE_IN_LEN 4
18841 /* The handle of the v-port */
18843 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_LEN 4
18851 * allocate a v-adaptor.
18860 /* The port to connect to the v-adaptor's port. */
18862 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
18863 /* Flags controlling v-adaptor creation */
18865 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 4
18868 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1
18870 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1
18871 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
18874 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_LEN 4
18877 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
18880 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 4
18887 /* The MAC address to assign to this v-adaptor */
18899 * de-allocate a v-adaptor.
18907 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4
18908 /* The port to which the v-adaptor is connected. */
18910 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_LEN 4
18918 * assign a new MAC address to a v-adaptor.
18927 /* The port to which the v-adaptor is connected. */
18929 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_LEN 4
18930 /* The new MAC address to assign to this v-adaptor */
18931 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4
18940 * read the MAC address assigned to a v-adaptor.
18948 #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4
18949 /* The port to which the v-adaptor is connected. */
18951 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_LEN 4
18955 /* The MAC address assigned to this v-adaptor */
18962 * read some config of v-adaptor.
18970 #define MC_CMD_VADAPTOR_QUERY_IN_LEN 4
18971 /* The port to which the v-adaptor is connected. */
18973 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_LEN 4
18979 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_LEN 4
18980 /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */
18981 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4
18982 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_LEN 4
18985 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4
19001 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_LEN 4
19003 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4
19004 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 4
19005 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_OFST 4
19008 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_OFST 4
19028 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_LEN 4
19029 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4
19030 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_LEN 4
19032 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_LEN 4
19034 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_LEN 4
19035 /* Write enable bits 0-3, set to write, clear to read. */
19037 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4
19039 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1
19046 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_LEN 4
19047 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4
19048 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_LEN 4
19050 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_LEN 4
19052 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_LEN 4
19065 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4
19068 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
19071 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4
19074 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_LEN 4
19087 #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4
19090 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_LEN 4
19109 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
19111 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4
19112 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_LEN 4
19118 * queues, but the key and indirection table are pre-configured and may not be
19119 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
19128 * be in the range 1 to RSS_MAX_INDIRECTION_QUEUES, where
19131 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-
19132 * spreading contexts this must be in the range 1 to
19134 * that specifying NUM_QUEUES = 1 will not perform any spreading but may still
19138 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 4
19144 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_LEN 4
19146 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_OFST 4
19147 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_LEN 4
19153 * queues, but the key and indirection table are pre-configured and may not be
19154 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
19163 * be in the range 1 to RSS_MAX_INDIRECTION_QUEUES, where
19166 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-
19167 * spreading contexts this must be in the range 1 to
19169 * that specifying NUM_QUEUES = 1 will not perform any spreading but may still
19173 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_LEN 4
19182 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_LEN 4
19185 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4
19191 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_LEN 4
19206 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4
19209 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_LEN 4
19228 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_LEN 4
19229 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */
19230 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4
19247 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4
19250 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_LEN 4
19254 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */
19255 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4
19274 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
19275 /* The 128-byte indirection table (1 byte per entry) */
19276 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4
19295 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4
19298 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
19302 /* The 128-byte indirection table (1 byte per entry) */
19303 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4
19309 * Write a portion of a selectable-size indirection table for an RSS context.
19322 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LEN(num) (4+4*(num))
19323 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_NUM(len) (((len)-4)/4)
19326 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_LEN 4
19327 /* An array of index-value pairs to be written to the table. Structure is
19330 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_OFST 4
19331 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_LEN 4
19332 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MINNUM 1
19340 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_LEN 4
19355 * Read a portion of a selectable-size indirection table for an RSS context.
19368 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LEN(num) (4+2*(num))
19369 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_NUM(len) (((len)-4)/2)
19372 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_LEN 4
19374 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_OFST 4
19376 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MINNUM 1
19385 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_NUM(len) (((len)-0)/2)
19389 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MINNUM 1
19407 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
19410 * in this case, the MODE fields may be set to non-zero values, and will take
19420 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4
19421 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 4
19422 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_OFST 4
19424 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1
19425 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_OFST 4
19426 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1
19427 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1
19428 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_OFST 4
19430 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1
19431 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_OFST 4
19433 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1
19434 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_OFST 4
19435 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4
19436 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4
19437 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_OFST 4
19439 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4
19440 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_OFST 4
19442 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4
19443 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_OFST 4
19445 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4
19446 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_OFST 4
19448 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4
19449 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_OFST 4
19451 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4
19452 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_OFST 4
19454 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4
19470 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4
19473 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
19479 * capability), the _EN bits report the state. If any _MODE bits are non-zero
19482 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS
19490 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4
19491 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_LEN 4
19492 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_OFST 4
19494 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1
19495 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_OFST 4
19496 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1
19497 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1
19498 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_OFST 4
19500 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1
19501 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_OFST 4
19503 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1
19504 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_OFST 4
19505 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4
19506 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4
19507 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_OFST 4
19509 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4
19510 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_OFST 4
19512 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4
19513 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_OFST 4
19515 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4
19516 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_OFST 4
19518 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4
19519 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_OFST 4
19521 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4
19522 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_OFST 4
19524 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4
19529 * Allocate a .1p mapping.
19540 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
19541 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed
19542 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and
19545 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4
19546 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_LEN 4
19549 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4
19550 /* The handle of the new .1p mapping. This should be considered opaque to the
19555 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_LEN 4
19556 /* enum: guaranteed invalid .1p mapping handle value */
19562 * Free a .1p mapping.
19570 #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4
19571 /* The handle of the .1p mapping */
19573 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_LEN 4
19581 * Set the mapping table for a .1p mapping.
19590 /* The handle of the .1p mapping */
19592 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4
19593 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context
19596 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4
19605 * Get the mapping table for a .1p mapping.
19613 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4
19614 /* The handle of the .1p mapping */
19616 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4
19620 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context
19623 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4
19643 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_LEN 4
19645 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4
19646 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_LEN 4
19649 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_LEN 4
19667 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_LEN 4
19669 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4
19670 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_LEN 4
19673 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_LEN 4
19681 * Add a MAC address to a v-port
19690 /* The handle of the v-port */
19692 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_LEN 4
19694 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4
19703 * Delete a MAC address from a v-port
19712 /* The handle of the v-port */
19714 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_LEN 4
19716 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4
19725 * Delete a MAC address from a v-port
19733 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4
19734 /* The handle of the v-port */
19736 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_LEN 4
19739 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4
19742 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num))
19743 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_NUM(len) (((len)-4)/6)
19746 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_LEN 4
19748 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4
19757 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port
19758 * has already been passed to another function (v-port's user), then that
19768 /* The handle of the v-port */
19770 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_LEN 4
19772 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4
19773 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_LEN 4
19774 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_OFST 4
19776 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1
19777 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_OFST 4
19778 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1
19779 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1
19782 * v-switch.
19785 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_LEN 4
19788 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_LEN 4
19797 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_LEN 4
19801 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4
19804 #define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4
19806 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_LEN 4
19809 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1
19814 * read some config of v-port.
19822 #define MC_CMD_EVB_PORT_QUERY_IN_LEN 4
19823 /* The handle of the v-port */
19825 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_LEN 4
19831 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_LEN 4
19832 /* The number of VLAN tags that may be used on a v-adaptor connected to this
19835 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4
19836 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4
19855 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4
19857 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4
19858 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4
19865 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_NUM(len) (((len)-0)/12)
19869 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1
19884 #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4
19886 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_LEN 4
19889 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1
19891 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1
19917 #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4
19919 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_LEN 4
19922 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1
19924 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1
19946 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_LEN 4
19948 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4
19949 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_LEN 4
19965 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_LEN 4
19968 /* Requested frequency in MHz for inter-core clock domain */
19969 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4
19970 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_LEN 4
19971 /* enum: Leave the inter-core clock domain frequency unchanged */
19975 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_LEN 4
19980 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_LEN 4
19985 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_LEN 4
19990 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_LEN 4
19995 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_LEN 4
20003 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_LEN 4
20006 /* Resulting inter-core frequency in MHz */
20007 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4
20008 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_LEN 4
20009 /* enum: The inter-core clock domain doesn't exist / isn't used */
20013 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_LEN 4
20018 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_LEN 4
20023 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_LEN 4
20028 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_LEN 4
20033 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_LEN 4
20050 #define MC_CMD_DPCPU_RPC_IN_CPU_LEN 4
20067 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be
20070 #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4
20072 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_OFST 4
20084 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_OFST 4
20087 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_OFST 4
20090 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_OFST 4
20093 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_OFST 4
20096 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_OFST 4
20104 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_OFST 4
20107 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_OFST 4
20110 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_OFST 4
20113 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_OFST 4
20119 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_OFST 4
20124 /* Register data to write. Only valid in write/write-read. */
20126 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_LEN 4
20129 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_LEN 4
20134 #define MC_CMD_DPCPU_RPC_OUT_RC_LEN 4
20136 #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4
20138 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_OFST 4
20141 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_OFST 4
20147 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_LEN 4
20149 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_LEN 4
20151 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_LEN 4
20153 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_LEN 4
20166 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4
20169 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_LEN 4
20185 #define MC_CMD_SHMBOOT_OP_IN_LEN 4
20188 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_LEN 4
20208 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_LEN 4
20209 #define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4
20210 #define MC_CMD_CAP_BLK_READ_IN_ADDR_LEN 4
20212 #define MC_CMD_CAP_BLK_READ_IN_COUNT_LEN 4
20219 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_NUM(len) (((len)-0)/8)
20223 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_LEN 4
20226 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4
20227 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_LEN 4
20230 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1
20247 #define MC_CMD_DUMP_DO_IN_PADDING_LEN 4
20248 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4
20249 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_LEN 4
20253 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4
20259 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
20261 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4
20263 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
20265 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
20267 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
20270 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
20272 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
20275 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4
20281 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4
20283 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_LEN 4
20287 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4
20291 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
20293 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4
20295 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
20297 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
20299 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
20301 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
20303 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
20305 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4
20307 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4
20310 #define MC_CMD_DUMP_DO_OUT_LEN 4
20312 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_LEN 4
20327 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_LEN 4
20328 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4
20329 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_LEN 4
20333 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4
20337 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
20339 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4
20341 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
20343 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
20345 …e MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
20347 …e MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
20349 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
20351 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4
20353 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4
20355 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_LEN 4
20359 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4
20363 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
20365 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4
20367 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
20369 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
20371 …e MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
20373 …e MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
20375 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
20377 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4
20379 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4
20384 * Adjusts power supply parameters. This is a warranty-voiding operation.
20396 #define MC_CMD_SET_PSU_IN_PARAM_LEN 4
20398 #define MC_CMD_SET_PSU_IN_RAIL_OFST 4
20399 #define MC_CMD_SET_PSU_IN_RAIL_LEN 4
20404 #define MC_CMD_SET_PSU_IN_VALUE_LEN 4
20425 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_LEN 4
20426 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4
20427 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_LEN 4
20432 #define MC_CMD_GET_FUNCTION_INFO_OUT_V2_PF_LEN 4
20433 #define MC_CMD_GET_FUNCTION_INFO_OUT_V2_VF_OFST 4
20434 #define MC_CMD_GET_FUNCTION_INFO_OUT_V2_VF_LEN 4
20439 #define MC_CMD_GET_FUNCTION_INFO_OUT_V2_INTF_LEN 4
20463 * should we wish to make this reliable; currently requests are fire-and-
20475 #define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num))
20476 #define MC_CMD_UART_SEND_DATA_OUT_DATA_NUM(len) (((len)-16)/1)
20479 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_LEN 4
20481 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4
20482 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_LEN 4
20485 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_LEN 4
20488 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_LEN 4
20490 #define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1
20513 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_LEN 4
20515 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4
20516 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_LEN 4
20519 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_LEN 4
20522 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_LEN 4
20528 #define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num))
20529 #define MC_CMD_UART_RECV_DATA_IN_DATA_NUM(len) (((len)-16)/1)
20532 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_LEN 4
20534 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4
20535 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_LEN 4
20538 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_LEN 4
20541 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_LEN 4
20543 #define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1
20551 * Read data programmed into the device One-Time-Programmable (OTP) Fuses
20562 #define MC_CMD_READ_FUSES_IN_OFFSET_LEN 4
20564 #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4
20565 #define MC_CMD_READ_FUSES_IN_LENGTH_LEN 4
20568 #define MC_CMD_READ_FUSES_OUT_LENMIN 4
20571 #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num))
20572 #define MC_CMD_READ_FUSES_OUT_DATA_NUM(len) (((len)-4)/1)
20575 #define MC_CMD_READ_FUSES_OUT_LENGTH_LEN 4
20577 #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4
20578 #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1
20594 #define MC_CMD_KR_TUNE_IN_LENMIN 4
20597 #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num))
20598 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_NUM(len) (((len)-4)/4)
20601 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1
20628 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1
20631 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4
20632 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4
20641 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4
20644 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1
20646 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1
20650 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4
20653 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
20654 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
20657 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
20658 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
20664 /* enum: Attenuation (0-15, Huntington) */
20666 /* enum: CTLE Boost (0-15, Huntington) */
20668 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max
20669 * positive, Medford - 0-31)
20672 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max
20673 * positive, Medford - 0-31)
20676 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max
20677 * positive, Medford - 0-16)
20680 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max
20681 * positive, Medford - 0-16)
20684 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max
20685 * positive, Medford - 0-16)
20688 /* enum: Edge DFE DLEV (0-128 for Medford) */
20690 /* enum: Variable Gain Amplifier (0-15, Medford) */
20692 /* enum: CTLE EQ Capacitor (0-15, Medford) */
20694 /* enum: CTLE EQ Resistor (0-7, Medford) */
20696 /* enum: CTLE gain (0-31, Medford2) */
20698 /* enum: CTLE pole (0-31, Medford2) */
20700 /* enum: CTLE peaking (0-31, Medford2) */
20702 /* enum: DFE Tap1 - even path (Medford2 - 6 bit signed (-29 - +29)) */
20704 /* enum: DFE Tap1 - odd path (Medford2 - 6 bit signed (-29 - +29)) */
20706 /* enum: DFE Tap2 (Medford2 - 6 bit signed (-20 - +20)) */
20708 /* enum: DFE Tap3 (Medford2 - 6 bit signed (-20 - +20)) */
20710 /* enum: DFE Tap4 (Medford2 - 6 bit signed (-20 - +20)) */
20712 /* enum: DFE Tap5 (Medford2 - 6 bit signed (-24 - +24)) */
20714 /* enum: DFE Tap6 (Medford2 - 6 bit signed (-24 - +24)) */
20716 /* enum: DFE Tap7 (Medford2 - 6 bit signed (-24 - +24)) */
20718 /* enum: DFE Tap8 (Medford2 - 6 bit signed (-24 - +24)) */
20720 /* enum: DFE Tap9 (Medford2 - 6 bit signed (-24 - +24)) */
20722 /* enum: DFE Tap10 (Medford2 - 6 bit signed (-24 - +24)) */
20724 /* enum: DFE Tap11 (Medford2 - 6 bit signed (-24 - +24)) */
20726 /* enum: DFE Tap12 (Medford2 - 6 bit signed (-24 - +24)) */
20728 /* enum: I/Q clk offset (Medford2 - 4 bit signed (-5 - +5))) */
20731 * (Medford2 - 6 bit signed (-29 - +29)))
20735 * (Medford2 - 6 bit signed (-29 - +29)))
20739 * (Medford2 - 6 bit signed (-29 - +29)))
20743 * (Medford2 - 6 bit signed (-29 - +29)))
20750 /* enum: CTLE Boost stages - retimer lineside (Medford2 with DS250x retimer - 4
20754 /* enum: DFE Tap1 - retimer lineside (Medford2 with DS250x retimer (-31 - 31))
20757 /* enum: DFE Tap2 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
20760 /* enum: DFE Tap3 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
20763 /* enum: DFE Tap4 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
20766 /* enum: DFE Tap5 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
20769 /* enum: CTLE Boost stages - retimer hostside (Medford2 with DS250x retimer - 4
20773 /* enum: DFE Tap1 - retimer hostside (Medford2 with DS250x retimer (-31 - 31))
20776 /* enum: DFE Tap2 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
20779 /* enum: DFE Tap3 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
20782 /* enum: DFE Tap4 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
20785 /* enum: DFE Tap5 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
20798 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
20801 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4
20813 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
20814 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
20817 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1
20819 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1
20822 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4
20823 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4
20824 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1
20827 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_OFST 4
20832 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_OFST 4
20837 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_OFST 4
20839 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1
20840 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_OFST 4
20842 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4
20843 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_OFST 4
20846 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_OFST 4
20854 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4
20857 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1
20859 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1
20863 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4
20866 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
20867 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
20870 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
20871 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1
20879 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */
20881 /* enum: De-Emphasis Tap1 Fine */
20883 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */
20885 /* enum: De-Emphasis Tap2 Fine (Huntington) */
20887 /* enum: Pre-Emphasis Magnitude (Huntington) */
20889 /* enum: Pre-Emphasis Fine (Huntington) */
20899 /* enum: Pre-cursor Tap (Medford, Medford2) */
20901 /* enum: Post-cursor Tap (Medford, Medford2) */
20905 /* enum: Pre-cursor Tap (Retimer Lineside) */
20907 /* enum: Post-cursor Tap (Retimer Lineside) */
20911 /* enum: Pre-cursor Tap (Retimer Hostside) */
20913 /* enum: Post-cursor Tap (Retimer Hostside) */
20937 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num))
20938 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
20941 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1
20943 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1
20946 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4
20947 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4
20948 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1
20951 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_OFST 4
20956 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_OFST 4
20961 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_OFST 4
20964 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_OFST 4
20967 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_OFST 4
20975 #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4
20978 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1
20980 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1
20990 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1
20992 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1
20994 /* Port-relative lane to scan eye on */
20995 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4
20996 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_LEN 4
21002 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_LEN 1
21004 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_OFST 1
21006 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_OFST 4
21007 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_LEN 4
21008 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_OFST 4
21011 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_OFST 4
21013 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_WIDTH 1
21016 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_LEN 4
21022 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4
21025 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1
21027 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1
21035 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_NUM(len) (((len)-0)/2)
21046 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1
21048 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1
21050 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4
21051 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_LEN 4
21052 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_OFST 4
21055 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_OFST 4
21057 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_WIDTH 1
21060 #define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4
21062 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_LEN 4
21068 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_LEN 1
21070 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_OFST 1
21072 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_OFST 4
21073 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_LEN 4
21081 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_LEN 1
21083 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_RSVD_OFST 1
21085 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_OFST 4
21086 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_LEN 4
21089 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_LEN 4
21092 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_LEN 4
21093 /* C(-1) request */
21095 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_LEN 4
21101 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_LEN 4
21104 /* C(+1) request */
21106 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_LEN 4
21112 /* C(-1) status */
21114 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_LEN 4
21120 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_OFST 4
21121 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_LEN 4
21124 /* C(+1) status */
21126 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_LEN 4
21129 /* C(-1) value */
21131 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_LEN 4
21134 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_LEN 4
21135 /* C(+1) status */
21137 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_LEN 4
21150 #define MC_CMD_PCIE_TUNE_IN_LENMIN 4
21153 #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num))
21154 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_NUM(len) (((len)-4)/4)
21157 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1
21176 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1
21179 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4
21180 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4
21189 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4
21192 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1
21194 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1
21198 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4
21201 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
21202 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
21205 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
21206 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
21212 /* enum: Attenuation (0-15) */
21214 /* enum: CTLE Boost (0-15) */
21216 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */
21218 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */
21220 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */
21222 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */
21224 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */
21256 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
21268 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
21269 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
21272 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1
21274 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1
21277 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4
21278 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4
21279 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1
21282 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_OFST 4
21287 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_OFST 4
21292 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_OFST 4
21294 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1
21295 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_OFST 4
21298 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_OFST 4
21301 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_OFST 4
21309 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4
21312 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1
21314 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1
21318 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4
21321 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
21322 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
21325 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
21326 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1
21336 /* enum: De-emphasis coefficient C(-1) (PIPE) */
21338 /* enum: De-emphasis coefficient C(0) (PIPE) */
21340 /* enum: De-emphasis coefficient C(+1) (PIPE) */
21344 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4
21358 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1
21360 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1
21362 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4
21363 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_LEN 4
21369 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4
21372 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1
21374 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1
21382 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_NUM(len) (((len)-0)/2)
21399 * - not used for V3 licensing
21407 #define MC_CMD_LICENSING_IN_LEN 4
21410 #define MC_CMD_LICENSING_IN_OP_LEN 4
21411 /* enum: re-read and apply licenses after a license key partition update; note
21412 * that this operation returns a zero-length response
21422 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_LEN 4
21426 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4
21427 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_LEN 4
21430 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_LEN 4
21433 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_LEN 4
21437 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_LEN 4
21442 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_LEN 4
21443 /* licensing subsystem self-test report (for manftest) */
21445 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_LEN 4
21446 /* enum: licensing subsystem self-test failed */
21448 /* enum: licensing subsystem self-test passed */
21455 * - V3 licensing (Medford)
21463 #define MC_CMD_LICENSING_V3_IN_LEN 4
21466 #define MC_CMD_LICENSING_V3_IN_OP_LEN 4
21467 /* enum: re-read and apply licenses after a license key partition update; note
21468 * that this operation returns a zero-length response
21480 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_LEN 4
21484 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4
21485 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_LEN 4
21488 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_LEN 4
21491 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_LEN 4
21496 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_LEN 4
21497 /* licensing subsystem self-test report (for manftest) */
21499 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_LEN 4
21500 /* enum: licensing subsystem self-test failed */
21502 /* enum: licensing subsystem self-test passed */
21508 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_LEN 4
21512 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_LEN 4
21522 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_LEN 4
21526 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_LEN 4
21537 * partition - V3 licensing (Medford)
21551 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num))
21552 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_NUM(len) (((len)-8)/1)
21555 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_LEN 4
21557 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4
21558 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_LEN 4
21561 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1
21569 * Execute an arbitrary MCDI command on the slave MC of a dual-core device.
21570 * This will fail on a single-core system.
21596 #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4
21599 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_LEN 4
21602 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4
21605 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_LEN 4
21631 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_LEN 4
21634 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4
21635 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_LEN 4
21640 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4
21643 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_LEN 4
21669 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_LEN 4
21672 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4
21673 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_LEN 4
21679 /* states of these features - bit set for licensed, clear for not licensed */
21683 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_LEN 4
21686 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4
21687 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_LEN 4
21694 * Perform an action for an individual licensed application - not used for V3
21706 #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num))
21707 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_NUM(len) (((len)-8)/4)
21710 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_LEN 4
21712 #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4
21713 #define MC_CMD_LICENSED_APP_OP_IN_OP_LEN 4
21720 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4
21729 #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num))
21730 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_NUM(len) (((len)-0)/4)
21733 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4
21742 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_LEN 4
21744 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4
21745 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_LEN 4
21754 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_LEN 4
21756 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4
21763 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_LEN 4
21765 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4
21766 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_LEN 4
21769 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_LEN 4
21777 * Perform validation for an individual licensed application - V3 licensing
21794 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_LEN 4
21798 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_LEN 4
21805 * of two 384-bit integers, r and s, in big-endian order. The signature signs a
21806 * SHA-384 digest of a message constructed from the concatenation of the input
21808 * bytes] ... expiry_time[4 bytes] ...
21814 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_LEN 4
21817 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_LEN 4
21828 /* MAC address of v-adaptor associated with the client. If no such v-adapator
21837 * Mask features - V3 licensing (Medford)
21850 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_LEN 4
21853 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4
21854 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_LEN 4
21859 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4
21873 * SF-116124-SW for an overview of how this could be used. The license is
21883 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4
21886 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_LEN 4
21904 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_LEN 4
21906 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4
21910 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4
21912 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_LEN 4
21915 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4
21917 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_LEN 4
21923 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_LEN 4
21933 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4
21935 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4
21936 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_LEN 4
21940 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_LEN 4
21949 * configuration. A copy of all traffic delivered to the host (non-promiscuous
21962 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4
21965 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1
21967 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1
21968 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1
21970 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4
21971 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4
21974 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4
21984 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4
22008 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4
22011 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1
22013 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1
22014 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1
22016 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4
22017 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4
22020 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4
22027 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4
22032 * Change configuration related to the parser-dispatcher subsystem.
22043 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num))
22044 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_NUM(len) (((len)-8)/4)
22047 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
22048 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible
22052 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the
22060 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
22061 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4
22066 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4
22067 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1
22077 * Read configuration related to the parser-dispatcher subsystem.
22088 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
22094 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
22095 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4
22098 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4
22101 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num))
22102 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_NUM(len) (((len)-0)/4)
22107 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4
22108 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1
22132 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4
22135 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1
22137 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4
22138 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4
22141 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4
22151 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4
22175 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4
22178 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1
22180 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4
22181 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4
22184 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4
22191 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4
22207 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_LEN 4
22208 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4
22209 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_LEN 4
22210 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_OFST 4
22212 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1
22217 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_LEN 4
22218 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4
22219 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_LEN 4
22221 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_LEN 4
22223 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_LEN 4
22242 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_LEN 4
22244 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4
22245 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_LEN 4
22246 /* The maximum number of MSI-X vectors the device can provide in total */
22248 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_LEN 4
22249 /* the number of MSI-X vectors the device will allocate by default to each PF
22252 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_LEN 4
22253 /* the number of MSI-X vectors the device will allocate by default to each VF
22256 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_LEN 4
22257 /* the maximum number of MSI-X vectors the device can allocate to any one PF */
22259 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_LEN 4
22260 /* the maximum number of MSI-X vectors the device can allocate to any one VF */
22262 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_LEN 4
22283 #define MC_CMD_GET_PORT_MODES_OUT_MODES_LEN 4
22285 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4
22286 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_LEN 4
22289 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_LEN 4
22297 #define MC_CMD_GET_PORT_MODES_OUT_V2_MODES_LEN 4
22299 #define MC_CMD_GET_PORT_MODES_OUT_V2_DEFAULT_MODE_OFST 4
22300 #define MC_CMD_GET_PORT_MODES_OUT_V2_DEFAULT_MODE_LEN 4
22303 #define MC_CMD_GET_PORT_MODES_OUT_V2_CURRENT_MODE_LEN 4
22314 #define MC_CMD_GET_PORT_MODES_OUT_V2_ENGINEERING_MODES_LEN 4
22333 #define MC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_LEN 4
22336 #define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_WIDTH 1
22338 #define MC_CMD_OVERRIDE_PORT_MODE_IN_MODE_OFST 4
22339 #define MC_CMD_OVERRIDE_PORT_MODE_IN_MODE_LEN 4
22357 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_LEN 4
22361 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4
22362 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_LEN 4
22364 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_LEN 4
22366 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_LEN 4
22369 #define MC_CMD_READ_ATB_OUT_LEN 4
22371 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_LEN 4
22389 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_LEN 4
22390 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4
22391 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_LEN 4
22401 * - before adding code that queries this workaround, remember that there's
22424 * 1,3 = 0x00030001
22427 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_LEN 4
22436 * set to 1.
22438 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4
22439 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_LEN 4
22471 * administrator-level operations that are not allowed from the local host once
22473 * SF-117064-DG for background).
22476 /* enum: Control the Match-Action Engine if present. See mcdi_mae.yml. */
22487 * the device and to on-device DDR. It allows clients to use TX-DESC2CMPT-DESC
22488 * descriptors, and to use TX-SEG-DESC and TX-MEM2MEM-DESC with an address
22498 #define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4
22501 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_LEN 4
22516 * e.g. VF 1,3 = 0x00030001
22519 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_LEN 4
22527 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4
22528 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_LEN 4
22537 #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4
22539 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_LEN 4
22559 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_LEN 4
22561 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4
22562 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_LEN 4
22581 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_LEN 4
22583 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4
22584 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_LEN 4
22587 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_LEN 4
22590 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_LEN 4
22591 /* Total number of mismatched bits between pairs in area 1 */
22593 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_LEN 4
22594 /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */
22596 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_LEN 4
22597 /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */
22599 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_LEN 4
22600 /* Checksum of data after logical OR of pairs in area 1 */
22602 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_LEN 4
22605 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_LEN 4
22608 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_LEN 4
22611 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_LEN 4
22614 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_LEN 4
22620 * only effects non-admin functions unless the admin privilege itself is
22632 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_LEN 4
22640 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4
22641 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_LEN 4
22642 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_OFST 4
22645 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_OFST 4
22652 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_LEN 4
22657 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_LEN 4
22676 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_LEN 4
22678 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4
22679 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_LEN 4
22685 #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num))
22686 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_NUM(len) (((len)-0)/1)
22689 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1
22708 #define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num))
22709 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_NUM(len) (((len)-8)/1)
22712 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_LEN 4
22714 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4
22715 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_LEN 4
22718 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1
22740 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_LEN 4
22742 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4
22743 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_LEN 4
22746 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4
22749 #define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num))
22750 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_NUM(len) (((len)-4)/1)
22753 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_LEN 4
22760 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4
22761 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1
22780 #define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num))
22781 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_NUM(len) (((len)-12)/1)
22784 * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair
22788 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1
22789 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1
22792 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4
22793 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_LEN 4
22798 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_LEN 4
22801 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1
22807 #define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4
22810 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_LEN 4
22823 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4
22826 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_LEN 4
22834 * Blank-check XPM memory and report bad locations
22845 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_LEN 4
22847 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4
22848 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_LEN 4
22851 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4
22854 #define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num))
22855 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_NUM(len) (((len)-4)/2)
22856 /* Total number of bad (non-blank) locations */
22858 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_LEN 4
22862 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4
22871 * Blank-check and repair XPM memory
22882 #define MC_CMD_XPM_REPAIR_IN_ADDR_LEN 4
22884 #define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4
22885 #define MC_CMD_XPM_REPAIR_IN_COUNT_LEN 4
22946 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_LEN 4
22948 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4
22949 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_LEN 4
22952 #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_LEN 4
22973 #define MC_CMD_PREPARE_SIGNED_IN_LEN 4
22976 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_LEN 4
22983 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4
23007 * parser-dispatcher will attempt to parse traffic on these ports as tunnel
23018 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4
23021 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num))
23022 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_NUM(len) (((len)-4)/4)
23028 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1
23035 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4
23036 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4
23048 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1
23067 #define MC_CMD_RX_BALANCING_IN_PORT_LEN 4
23069 #define MC_CMD_RX_BALANCING_IN_PRIORITY_OFST 4
23070 #define MC_CMD_RX_BALANCING_IN_PRIORITY_LEN 4
23073 #define MC_CMD_RX_BALANCING_IN_SRC_DST_LEN 4
23076 #define MC_CMD_RX_BALANCING_IN_ENG_LEN 4
23096 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num))
23097 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_NUM(len) (((len)-8)/1)
23100 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_LEN 4
23102 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_OFST 4
23103 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_LEN 4
23106 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_LEN 1
23107 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MINNUM 1
23127 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_LEN 4
23130 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_LEN 4
23136 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num))
23137 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_NUM(len) (((len)-12)/1)
23140 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_LEN 4
23142 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_OFST 4
23143 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_LEN 4
23146 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_LEN 4
23149 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_LEN 1
23171 /* Function-relative queue instance */
23173 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_LEN 4
23175 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4
23176 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_LEN 4
23179 #define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_LEN 4
23182 #define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_LEN 4
23192 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_LEN 4
23194 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4
23195 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_LEN 4
23214 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_LEN 4
23220 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4
23221 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_LEN 4
23226 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_LEN 4
23232 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_LEN 4
23237 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_LEN 4
23242 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_LEN 4
23250 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_LEN 4
23256 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_LEN 4
23263 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_LEN 4
23279 * local queue index. The calling client must be the currently-assigned user of
23283 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_LEN 4
23284 /* Will the common pool be used as TX_vFIFO_ULL (1) */
23285 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_OFST 4
23286 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_LEN 4
23292 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_LEN 4
23295 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_LEN 4
23297 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1
23300 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_LEN 4
23302 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */
23309 /* enum: To enable Switch loopback with Rx engine 1 */
23313 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_LEN 4
23316 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_LEN 4
23334 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_LEN 4
23336 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_OFST 4
23337 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_LEN 4
23339 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1
23346 /* enum: To enable Switch loopback with Rx engine 1 */
23350 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_LEN 4
23355 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_LEN 4
23358 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_LEN 4
23360 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1
23366 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_LEN 4
23368 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_OFST 4
23369 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_LEN 4
23375 * ready to be re-used.
23383 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4
23386 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_LEN 4
23395 * it ready to be re-used.
23403 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4
23406 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_LEN 4
23429 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_LEN 4
23431 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_OFST 4
23432 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_LEN 4
23449 /* The SUC firmware version as four numbers - a.b.c.d */
23451 #define MC_CMD_SUC_VERSION_OUT_VERSION_LEN 4
23452 #define MC_CMD_SUC_VERSION_OUT_VERSION_NUM 4
23457 #define MC_CMD_SUC_VERSION_OUT_BUILD_DATE_LEN 4
23459 * indicates family, memory sizes etc. See SF-116728-SW for further details.
23462 #define MC_CMD_SUC_VERSION_OUT_CHIP_ID_LEN 4
23467 #define MC_CMD_SUC_BOOT_VERSION_IN_LEN 4
23469 #define MC_CMD_SUC_BOOT_VERSION_IN_MAGIC_LEN 4
23474 #define MC_CMD_SUC_BOOT_VERSION_OUT_LEN 4
23477 #define MC_CMD_SUC_BOOT_VERSION_OUT_VERSION_LEN 4
23485 * combination of fields, then this command returns a list of prefix-ids,
23488 * supported, returns ENOTSUP. If the firmware can't create any new prefix-ids
23502 #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_LEN 4
23505 #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_OFST 4
23506 #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_LEN 4
23511 #define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_WIDTH 1
23513 #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_LBN 1
23514 #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_WIDTH 1
23517 #define MC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_WIDTH 1
23520 #define MC_CMD_GET_RX_PREFIX_ID_IN_CLASS_WIDTH 1
23522 #define MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_LBN 4
23523 #define MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_WIDTH 1
23526 #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_WIDTH 1
23529 #define MC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_WIDTH 1
23532 #define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_MPORT_WIDTH 1
23535 #define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_WIDTH 1
23538 #define MC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_WIDTH 1
23541 #define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_WIDTH 1
23544 #define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIPPED_WIDTH 1
23547 #define MC_CMD_GET_RX_PREFIX_ID_IN_VSWITCH_STATUS_WIDTH 1
23553 #define MC_CMD_GET_RX_PREFIX_ID_OUT_LEN(num) (4+4*(num))
23554 #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_NUM(len) (((len)-4)/4)
23555 /* Number of prefix-ids returned */
23557 #define MC_CMD_GET_RX_PREFIX_ID_OUT_NUM_RX_PREFIX_IDS_LEN 4
23561 #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_OFST 4
23562 #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_LEN 4
23563 #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_MINNUM 1
23570 #define RX_PREFIX_FIELD_INFO_LEN 4
23578 #define RX_PREFIX_FIELD_INFO_WIDTH_BITS_LEN 1
23585 #define RX_PREFIX_FIELD_INFO_TYPE_LEN 1
23605 #define RX_PREFIX_FIXED_RESPONSE_LENMIN 4
23608 #define RX_PREFIX_FIXED_RESPONSE_LEN(num) (4+4*(num))
23609 #define RX_PREFIX_FIXED_RESPONSE_FIELDS_NUM(len) (((len)-4)/4)
23612 #define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_LEN 1
23616 #define RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_OFST 1
23617 #define RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_LEN 1
23625 #define RX_PREFIX_FIXED_RESPONSE_FIELDS_OFST 4
23626 #define RX_PREFIX_FIXED_RESPONSE_FIELDS_LEN 4
23646 #define MC_CMD_QUERY_RX_PREFIX_ID_IN_LEN 4
23649 #define MC_CMD_QUERY_RX_PREFIX_ID_IN_RX_PREFIX_ID_LEN 4
23652 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LENMIN 4
23655 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LEN(num) (4+1*(num))
23656 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_NUM(len) (((len)-4)/1)
23659 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_LEN 1
23662 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESERVED_OFST 1
23665 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_OFST 4
23666 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_LEN 1
23674 * A command to perform various bundle-related operations on insecure cards.
23682 #define MC_CMD_BUNDLE_IN_LEN 4
23683 /* Sub-command code */
23685 #define MC_CMD_BUNDLE_IN_OP_LEN 4
23696 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_LEN 4
23697 /* Sub-command code. Must be OP_COMPONENT_ACCESS_GET. */
23699 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_OP_LEN 4
23704 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_LEN 4
23707 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_ACCESS_MODE_LEN 4
23708 /* enum: Component partitions are read-only from the host. */
23710 /* enum: Component partitions can read read-from written-to by the host. */
23715 * read-only on firmware built with bundle support. This command marks these
23721 /* Sub-command code. Must be OP_COMPONENT_ACCESS_SET. */
23723 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_OP_LEN 4
23725 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_ACCESS_MODE_OFST 4
23726 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_ACCESS_MODE_LEN 4
23744 #define MC_CMD_GET_VPD_IN_LEN 4
23749 #define MC_CMD_GET_VPD_IN_ADDR_LEN 4
23755 #define MC_CMD_GET_VPD_OUT_LEN(num) (0+1*(num))
23756 #define MC_CMD_GET_VPD_OUT_DATA_NUM(len) (((len)-0)/1)
23759 #define MC_CMD_GET_VPD_OUT_DATA_LEN 1
23767 * Provide information about the NC-SI stack
23778 #define MC_CMD_GET_NCSI_INFO_IN_OP_LEN 4
23783 /* The NC-SI channel on which the operation is to be performed */
23784 #define MC_CMD_GET_NCSI_INFO_IN_CHANNEL_OFST 4
23785 #define MC_CMD_GET_NCSI_INFO_IN_CHANNEL_LEN 4
23791 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_SETTINGS_LEN 4
23793 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ADV_CAP_OFST 4
23794 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ADV_CAP_LEN 4
23797 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATUS_LEN 4
23803 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ENABLE_WIDTH 1
23806 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_NETWORK_TX_WIDTH 1
23808 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_LBN 4
23809 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_WIDTH 1
23813 /* The number of NC-SI commands received. */
23815 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMDS_RX_LEN 4
23816 /* The number of NC-SI commands dropped. */
23817 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_PKTS_DROPPED_OFST 4
23818 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_PKTS_DROPPED_LEN 4
23819 /* The number of invalid NC-SI commands received. */
23821 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_TYPE_ERRS_LEN 4
23824 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_CSUM_ERRS_LEN 4
23825 /* The number of NC-SI requests received. */
23827 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_RX_PKTS_LEN 4
23828 /* The number of NC-SI responses sent (includes AENs) */
23830 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_TX_PKTS_LEN 4
23831 /* The number of NC-SI AENs sent */
23833 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_AENS_SENT_LEN 4
23839 * be found within XN-200418-TC.
23841 #define CLIENT_HANDLE_LEN 4
23843 #define CLIENT_HANDLE_OPAQUE_LEN 4
23877 #define CLOCK_INFO_SETTABLE_WIDTH 1
23881 #define CLOCK_INFO_FREQUENCY_OFST 4
23883 #define CLOCK_INFO_FREQUENCY_LO_OFST 4
23884 #define CLOCK_INFO_FREQUENCY_LO_LEN 4
23888 #define CLOCK_INFO_FREQUENCY_HI_LEN 4
23893 /* Human-readable ASCII name for clock, with NUL termination */
23895 #define CLOCK_INFO_NAME_LEN 1
23902 /* The instance of the scheduler. Refer to XN-200389-AW for the location of
23906 #define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_LEN 1
23920 #define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_OFST 1
23921 #define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_LEN 1
23936 #define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_OFST 4
23937 #define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_LEN 4
23942 #define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_LEN 4
23947 #define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_LEN 4
23969 #define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_NUM(len) (((len)-0)/28)
23981 * only affects checksum validation in VNIC RX - on TX the send descriptor
23982 * explicitly specifies encapsulation. These rules are per-VNIC, i.e. only
23991 * combinations. Each driver may only have a limited set of active rules -
24003 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_LEN 4
24004 /* Any non-zero bits other than the ones named below or an unsupported
24008 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_OFST 4
24009 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_LEN 4
24010 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_OFST 4
24012 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_WIDTH 1
24013 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_OFST 4
24014 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_LBN 1
24015 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_WIDTH 1
24016 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_OFST 4
24018 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_WIDTH 1
24019 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_OFST 4
24021 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_WIDTH 1
24022 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_OFST 4
24023 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_LBN 4
24024 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_WIDTH 1
24042 * case of IPv4, the IP should be in the first 4 bytes and all other bytes
24049 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_IP_PROTO_LEN 1
24052 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ACTION_FLAGS_LEN 1
24055 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_WIDTH 1
24057 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_RSS_ON_OUTER_LBN 1
24058 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_RSS_ON_OUTER_WIDTH 1
24061 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STEER_ON_OUTER_WIDTH 1
24067 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ENCAP_TYPE_LEN 4
24070 #define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_LEN 4
24073 #define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_LEN 4
24088 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_LEN 4
24091 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_LEN 4
24097 * the endianness specified by the RFC; users should ignore the broken-out
24102 #define UUID_TIME_LOW_LEN 4
24105 #define UUID_TIME_MID_OFST 4
24112 #define UUID_VERSION_WIDTH 4
24126 * currently-loaded plugin offering the given functionality (as identified by
24132 * the newest and that is the one opened. See SF-123625-SW for architectural
24147 #define MC_CMD_PLUGIN_ALLOC_IN_FLAGS_LEN 4
24150 #define MC_CMD_PLUGIN_ALLOC_IN_FLAG_INFO_ONLY_WIDTH 1
24152 #define MC_CMD_PLUGIN_ALLOC_IN_FLAG_ALLOW_DISABLED_LBN 1
24153 #define MC_CMD_PLUGIN_ALLOC_IN_FLAG_ALLOW_DISABLED_WIDTH 1
24169 #define MC_CMD_PLUGIN_ALLOC_OUT_LEN 4
24172 #define MC_CMD_PLUGIN_ALLOC_OUT_HANDLE_LEN 4
24185 #define MC_CMD_PLUGIN_FREE_IN_LEN 4
24188 #define MC_CMD_PLUGIN_FREE_IN_HANDLE_LEN 4
24205 #define MC_CMD_PLUGIN_GET_META_GLOBAL_IN_LEN 4
24208 #define MC_CMD_PLUGIN_GET_META_GLOBAL_IN_HANDLE_LEN 4
24217 /* semver sub-version of this plugin extension */
24220 /* semver micro-version of this plugin extension */
24225 #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_NUM_MSGS_LEN 4
24237 #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAGS_LEN 4
24240 #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAG_READ_WIDTH 1
24242 #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAG_WRITE_LBN 1
24243 #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAG_WRITE_WIDTH 1
24251 #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_ADMIN_GROUP_LEN 1
24253 * corresponding to this extension, i.e. set the bit 1<<PRIVILEGE_BIT to permit
24257 #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_PRIVILEGE_BIT_LEN 1
24266 * extension in a human-readable way. Contrast with
24279 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_HANDLE_LEN 4
24281 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_SUBTYPE_OFST 4
24282 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_SUBTYPE_LEN 4
24283 /* enum: Top-level information about the extension. The returned data is an
24285 * the extension. The data is a back-to-back list of zero-terminated strings;
24286 * the even-numbered fields (0,2,4,...) are keys and their following odd-
24288 * nominally UTF-8. Per RFC5013, the same key may be repeated any number of
24290 * and the UTF-8 encoding) may have been provided by the plugin author, so
24292 * top-level structure to separate out the keys and values; the contents of the
24293 * values is not expected to be machine-readable.
24300 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_OFFSET_LEN 4
24303 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_LENMIN 4
24306 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_LEN(num) (4+1*(num))
24307 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_DATA_NUM(len) (((len)-4)/1)
24310 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_TOTAL_SIZE_LEN 4
24312 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_DATA_OFST 4
24313 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_DATA_LEN 1
24334 #define MC_CMD_PLUGIN_GET_META_MSG_IN_HANDLE_LEN 4
24336 #define MC_CMD_PLUGIN_GET_META_MSG_IN_ID_OFST 4
24337 #define MC_CMD_PLUGIN_GET_META_MSG_IN_ID_LEN 4
24345 #define MC_CMD_PLUGIN_GET_META_MSG_OUT_ID_LEN 4
24349 #define MC_CMD_PLUGIN_GET_META_MSG_OUT_INDEX_OFST 4
24350 #define MC_CMD_PLUGIN_GET_META_MSG_OUT_INDEX_LEN 4
24351 /* Short human-readable codename for this message. This is conventionally
24366 #define MC_CMD_PLUGIN_GET_META_MSG_OUT_DATA_SIZE_LEN 4
24377 #define PLUGIN_EXTENSION_ADMIN_GROUP_LEN 1
24381 #define PLUGIN_EXTENSION_FLAG_ENABLED_WIDTH 1
24401 #define MC_CMD_PLUGIN_GET_ALL_IN_LEN 4
24406 #define MC_CMD_PLUGIN_GET_ALL_IN_FLAGS_LEN 4
24409 #define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_ENABLED_WIDTH 1
24411 #define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_DISABLED_LBN 1
24412 #define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_DISABLED_WIDTH 1
24419 #define MC_CMD_PLUGIN_GET_ALL_OUT_EXTENSIONS_NUM(len) (((len)-0)/20)
24434 * identified by a 32-bit ID.
24445 #define MC_CMD_PLUGIN_REQ_IN_LEN(num) (8+1*(num))
24446 #define MC_CMD_PLUGIN_REQ_IN_DATA_NUM(len) (((len)-8)/1)
24449 #define MC_CMD_PLUGIN_REQ_IN_HANDLE_LEN 4
24451 #define MC_CMD_PLUGIN_REQ_IN_ID_OFST 4
24452 #define MC_CMD_PLUGIN_REQ_IN_ID_LEN 4
24457 #define MC_CMD_PLUGIN_REQ_IN_DATA_LEN 1
24466 #define MC_CMD_PLUGIN_REQ_OUT_LEN(num) (0+1*(num))
24467 #define MC_CMD_PLUGIN_REQ_OUT_DATA_NUM(len) (((len)-0)/1)
24472 #define MC_CMD_PLUGIN_REQ_OUT_DATA_LEN 1
24479 * DESC_ADDR in the range [DESC_ADDR_BASE:DESC_ADDR_BASE + 1 <<
24480 * WINDOW_SIZE_LOG2) map to TRGT_ADDR = DESC_ADDR - DESC_ADDR_BASE +
24488 #define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_LEN 4
24491 #define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_OFST 4
24492 #define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_LEN 4
24503 #define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_LEN 4
24507 #define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_LEN 4
24514 #define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_LEN 4
24518 * must be a multiple of 1 << TRGT_ADDR_ALIGN_LOG2.
24521 #define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_LEN 4
24527 #define DESC_ADDR_REGION_RSVD_LO_LEN 4
24531 #define DESC_ADDR_REGION_RSVD_HI_LEN 4
24551 #define MC_CMD_GET_DESC_ADDR_INFO_OUT_LEN 4
24552 /* The type of mapping; see SF-nnnnnn-xx (EF100 driver writer's guide, once
24556 #define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_TYPE_LEN 4
24582 #define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_NUM(len) (((len)-0)/32)
24588 #define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_MINNUM 1
24607 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_NUM(len) (((len)-8)/8)
24610 * should be set to 1.
24613 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_SET_REGION_MASK_LEN 4
24615 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_RSVD_OFST 4
24616 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_RSVD_LEN 4
24625 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_LEN 4
24629 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_LEN 4
24632 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_MINNUM 1
24657 #define MC_CMD_CLIENT_CMD_IN_LEN 4
24660 #define MC_CMD_CLIENT_CMD_IN_CLIENT_ID_LEN 4
24670 * unit. See also MC_CMD_CLIENT_CMD. See XN-200265-TC for background, concepts
24672 * clients". The newly-created client is a child of the client which sent this
24686 #define MC_CMD_CLIENT_ALLOC_OUT_LEN 4
24689 #define MC_CMD_CLIENT_ALLOC_OUT_CLIENT_ID_LEN 4
24704 #define MC_CMD_CLIENT_FREE_IN_LEN 4
24709 #define MC_CMD_CLIENT_FREE_IN_CLIENT_ID_LEN 4
24722 * created are then owned by the user-client. Only the VI owner can call this
24733 /* Function-relative VI number to modify. */
24735 #define MC_CMD_SET_VI_USER_IN_INSTANCE_LEN 4
24740 #define MC_CMD_SET_VI_USER_IN_CLIENT_ID_OFST 4
24741 #define MC_CMD_SET_VI_USER_IN_CLIENT_ID_LEN 4
24785 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_LEN 4
24791 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_LEN 4
24798 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_NUM(len) (((len)-0)/6)
24819 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMIN 4
24822 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LEN(num) (4+6*(num))
24823 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_NUM(len) (((len)-4)/6)
24826 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_LEN 4
24828 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_OFST 4
24840 * Retrieve physical build-level board attributes as configured at
24841 * manufacturing stage. Fields originate from EEPROM and per-platform constants
24861 * response-message.
24864 #define MC_CMD_GET_BOARD_ATTR_OUT_FLAGS_LEN 4
24867 #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_WIDTH 1
24869 #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_LBN 1
24870 #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_WIDTH 1
24873 #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_WIDTH 1
24874 #define MC_CMD_GET_BOARD_ATTR_OUT_ATTRIBUTES_OFST 4
24875 #define MC_CMD_GET_BOARD_ATTR_OUT_ATTRIBUTES_LEN 4
24876 #define MC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_OFST 4
24878 #define MC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_WIDTH 1
24879 #define MC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_OFST 4
24880 #define MC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_LBN 1
24881 #define MC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_WIDTH 1
24882 #define MC_CMD_GET_BOARD_ATTR_OUT_FPGA_VOLTAGES_SUPPORTED_OFST 4
24891 #define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_COUNT_OFST 4
24896 #define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_LEN 1
24908 * Retrieve current state of the System-on-Chip. This command is valid when
24923 #define MC_CMD_GET_SOC_STATE_OUT_FLAGS_LEN 4
24926 #define MC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_WIDTH 1
24928 #define MC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_LBN 1
24929 #define MC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_WIDTH 1
24932 #define MC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_WIDTH 1
24934 #define MC_CMD_GET_SOC_STATE_OUT_ATTRIBUTES_OFST 4
24935 #define MC_CMD_GET_SOC_STATE_OUT_ATTRIBUTES_LEN 4
24936 #define MC_CMD_GET_SOC_STATE_OUT_RUN_STATE_OFST 4
24951 #define MC_CMD_GET_SOC_STATE_OUT_RESET_COUNT_LEN 4
24971 #define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_FLAGS_LEN 4
24974 #define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_WIDTH 1
24976 * into pages. This field specifies which (0-indexed) page to request. A
24982 #define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_PAGE_OFST 4
24983 #define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_PAGE_LEN 4
24990 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_NUM(len) (((len)-16)/16)
24993 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_TOTAL_RESULTS_LEN 4
24995 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_NUM_PAGES_OFST 4
24996 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_NUM_PAGES_LEN 4
24999 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_THIS_PAGE_LEN 4
25003 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_GENERATION_LEN 4
25014 * Query per-TXQ statistics.
25025 #define MC_CMD_TXQ_STATS_IN_INSTANCE_LEN 4
25027 #define MC_CMD_TXQ_STATS_IN_FLAGS_OFST 4
25028 #define MC_CMD_TXQ_STATS_IN_FLAGS_LEN 4
25029 #define MC_CMD_TXQ_STATS_IN_CLEAR_OFST 4
25031 #define MC_CMD_TXQ_STATS_IN_CLEAR_WIDTH 1
25038 #define MC_CMD_TXQ_STATS_OUT_STATISTICS_NUM(len) (((len)-0)/8)
25042 #define MC_CMD_TXQ_STATS_OUT_STATISTICS_LO_LEN 4
25045 #define MC_CMD_TXQ_STATS_OUT_STATISTICS_HI_OFST 4
25046 #define MC_CMD_TXQ_STATS_OUT_STATISTICS_HI_LEN 4
25055 * defined in SF-120734-TC with more information in SF-122717-TC.
25057 #define FUNCTION_PERSONALITY_LEN 4
25059 #define FUNCTION_PERSONALITY_ID_LEN 4
25062 /* enum: Function has an EF100-style function control window and VI windows
25074 /* enum: Function is a Xilinx acceleration device - management function */
25076 /* enum: Function is a Xilinx acceleration device - user function */
25092 #define MC_CMD_VIRTIO_GET_FEATURES_IN_LEN 4
25097 #define MC_CMD_VIRTIO_GET_FEATURES_IN_DEVICE_ID_LEN 4
25109 * specification ( https://docs.oasis-
25110 * open.org/virtio/virtio/v1.1/csprd01/virtio-v1.1-csprd01.pdf )
25115 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_LEN 4
25118 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_OFST 4
25119 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_LEN 4
25141 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_DEVICE_ID_LEN 4
25144 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_RESERVED_OFST 4
25145 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_RESERVED_LEN 4
25152 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_LEN 4
25156 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_LEN 4
25170 * allowed on multi-queue devices is returned. Response is expected to be
25179 #define MC_CMD_VIRTIO_GET_CAPABILITIES_IN_LEN 4
25184 #define MC_CMD_VIRTIO_GET_CAPABILITIES_IN_DEVICE_ID_LEN 4
25189 #define MC_CMD_VIRTIO_GET_CAPABILITIES_OUT_LEN 4
25192 #define MC_CMD_VIRTIO_GET_CAPABILITIES_OUT_MAX_QUEUES_LEN 4
25213 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_QUEUE_TYPE_LEN 1
25220 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED_OFST 1
25221 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED_LEN 1
25229 /* Desired instance. This is the function-local index of the associated VI, not
25232 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INSTANCE_OFST 4
25233 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INSTANCE_LEN 4
25236 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_SIZE_LEN 4
25239 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FLAGS_LEN 4
25242 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USE_PASID_WIDTH 1
25247 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_LEN 4
25251 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_LEN 4
25258 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_LEN 4
25262 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_LEN 4
25269 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_LEN 4
25273 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_LEN 4
25280 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_PASID_LEN 4
25292 * the features returned from MC_CMD_VIRTIO_GET_FEATURES. Features are per-
25299 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_LEN 4
25303 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_LEN 4
25315 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_AVAIL_IDX_LEN 4
25318 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_PIDX_LEN 4
25326 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_USED_IDX_LEN 4
25329 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_CIDX_LEN 4
25335 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_MPORT_SELECTOR_LEN 4
25354 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_QUEUE_TYPE_LEN 1
25357 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_RESERVED_OFST 1
25358 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_RESERVED_LEN 1
25367 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_INSTANCE_OFST 4
25368 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_INSTANCE_LEN 4
25374 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_AVAIL_IDX_LEN 4
25377 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_PIDX_LEN 4
25379 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_USED_IDX_OFST 4
25380 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_USED_IDX_LEN 4
25382 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_CIDX_OFST 4
25383 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_CIDX_LEN 4
25402 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_DEVICE_ID_LEN 1
25405 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_RESERVED_OFST 1
25406 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_RESERVED_LEN 1
25415 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_INSTANCE_OFST 4
25416 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_INSTANCE_LEN 4
25422 #define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_RX_DBL_OFFSET_LEN 4
25424 #define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_TX_DBL_OFFSET_OFST 4
25425 #define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_TX_DBL_OFFSET_LEN 4
25428 #define MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_LEN 4
25431 #define MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_DBL_OFFSET_LEN 4
25464 #define PCIE_FUNCTION_INTF_OFST 4
25465 #define PCIE_FUNCTION_INTF_LEN 4
25483 #define QUEUE_ID_LEN 4
25491 #define QUEUE_ID_REL_QUEUE_WIDTH 1
25501 * embedded Application Processor), via EF100 descriptor proxy, memory-to-
25502 * memory and descriptor-to-completion mechanisms. Primary user is Virtio-blk
25503 * subsystem, see SF-122927-TC. This function allocates a new descriptor proxy
25504 * function on the host and assigns a user-defined label. The actual function
25523 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_LEN 4
25526 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_OFST 4
25527 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_LEN 4
25534 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_INTF_OFST 4
25535 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_INTF_LEN 4
25537 * SF-120734-TC with more information in SF-122717-TC. At present, we only
25541 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_PERSONALITY_LEN 4
25544 /* User-defined label (zero-terminated ASCII string) to uniquely identify the
25554 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_HANDLE_LEN 4
25556 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_OFST 4
25558 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_OFST 4
25559 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_LEN 4
25563 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_LEN 4
25566 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_PF_OFST 4
25571 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_INTF_LEN 4
25588 /* User-defined label (zero-terminated ASCII string) to uniquely identify the
25595 #define MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_STORE_LEN 4
25603 * Virtio specification v1.1, Sections 5.2.3 and 6 for definition of feature
25604 * bits. See Virtio specification v1.1, Section 5.2.4 (struct
25612 #define VIRTIO_BLK_CONFIG_FEATURES_LO_LEN 4
25615 #define VIRTIO_BLK_CONFIG_FEATURES_HI_OFST 4
25616 #define VIRTIO_BLK_CONFIG_FEATURES_HI_LEN 4
25621 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_WIDTH 1
25623 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_LBN 1
25624 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_WIDTH 1
25627 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SEG_MAX_WIDTH 1
25629 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_LBN 4
25630 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_WIDTH 1
25633 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_RO_WIDTH 1
25636 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BLK_SIZE_WIDTH 1
25639 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SCSI_WIDTH 1
25642 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_FLUSH_WIDTH 1
25645 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_TOPOLOGY_WIDTH 1
25648 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_CONFIG_WCE_WIDTH 1
25651 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_MQ_WIDTH 1
25654 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_DISCARD_WIDTH 1
25657 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_WRITE_ZEROES_WIDTH 1
25660 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_INDIRECT_DESC_WIDTH 1
25663 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_EVENT_IDX_WIDTH 1
25666 #define VIRTIO_BLK_CONFIG_VIRTIO_F_VERSION_1_WIDTH 1
25669 #define VIRTIO_BLK_CONFIG_VIRTIO_F_ACCESS_PLATFORM_WIDTH 1
25672 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_PACKED_WIDTH 1
25675 #define VIRTIO_BLK_CONFIG_VIRTIO_F_IN_ORDER_WIDTH 1
25678 #define VIRTIO_BLK_CONFIG_VIRTIO_F_ORDER_PLATFORM_WIDTH 1
25681 #define VIRTIO_BLK_CONFIG_VIRTIO_F_SR_IOV_WIDTH 1
25684 #define VIRTIO_BLK_CONFIG_VIRTIO_F_NOTIFICATION_DATA_WIDTH 1
25687 /* The capacity of the device (expressed in 512-byte sectors) */
25691 #define VIRTIO_BLK_CONFIG_CAPACITY_LO_LEN 4
25695 #define VIRTIO_BLK_CONFIG_CAPACITY_HI_LEN 4
25704 #define VIRTIO_BLK_CONFIG_SIZE_MAX_LEN 4
25711 #define VIRTIO_BLK_CONFIG_SEG_MAX_LEN 4
25714 /* Disk-style geometry - cylinders. Only valid when VIRTIO_BLK_F_GEOMETRY is
25721 /* Disk-style geometry - heads. Only valid when VIRTIO_BLK_F_GEOMETRY is set.
25724 #define VIRTIO_BLK_CONFIG_HEADS_LEN 1
25727 /* Disk-style geometry - sectors. Only valid when VIRTIO_BLK_F_GEOMETRY is set.
25730 #define VIRTIO_BLK_CONFIG_SECTORS_LEN 1
25735 #define VIRTIO_BLK_CONFIG_BLK_SIZE_LEN 4
25738 /* Block topology - number of logical blocks per physical block (log2). Only
25742 #define VIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_LEN 1
25745 /* Block topology - offset of first aligned logical block. Only valid when
25749 #define VIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_LEN 1
25752 /* Block topology - suggested minimum I/O size in blocks. Only valid when
25759 /* Block topology - optimal (suggested maximum) I/O size in blocks. Only valid
25763 #define VIRTIO_BLK_CONFIG_OPT_IO_SIZE_LEN 4
25779 /* Maximum discard sectors size, in 512-byte units. Only valid if
25783 #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_LEN 4
25789 #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_LEN 4
25792 /* Discard sector alignment, in 512-byte units. Only valid if
25796 #define VIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_LEN 4
25799 /* Maximum write zeroes sectors size, in 512-byte units. Only valid if
25803 #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_LEN 4
25810 #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_LEN 4
25817 #define VIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_LEN 1
25842 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LEN(num) (20+1*(num))
25843 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_NUM(len) (((len)-20)/1)
25848 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_HANDLE_LEN 4
25850 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_RESERVED_OFST 4
25857 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_LEN 1
25868 * Commit function configuration to non-volatile or volatile store. Once
25884 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_HANDLE_LEN 4
25885 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_STORE_OFST 4
25886 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_STORE_LEN 4
25887 /* enum: Store into non-volatile (dynamic) config */
25893 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_LEN 4
25897 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_CONFIG_GENERATION_LEN 4
25903 * integer handle, valid until function is deallocated, MC rebooted or power-
25913 /* User-defined label (zero-terminated ASCII string) to uniquely identify the
25923 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LEN(num) (40+1*(num))
25924 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_NUM(len) (((len)-40)/1)
25927 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_HANDLE_LEN 4
25929 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_OFST 4
25931 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_OFST 4
25932 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_LEN 4
25936 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_LEN 4
25939 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_PF_OFST 4
25944 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_INTF_LEN 4
25947 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_LEN 4
25952 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_STATUS_LEN 4
25965 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_GENERATION_LEN 4
25973 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_LEN 1
25994 #define MC_CMD_DESC_PROXY_FUNC_CLOSE_IN_LEN 4
25997 #define MC_CMD_DESC_PROXY_FUNC_CLOSE_IN_HANDLE_LEN 4
26008 #define DESC_PROXY_FUNC_MAP_FUNC_LO_LEN 4
26011 #define DESC_PROXY_FUNC_MAP_FUNC_HI_OFST 4
26012 #define DESC_PROXY_FUNC_MAP_FUNC_HI_LEN 4
26025 #define DESC_PROXY_FUNC_MAP_FUNC_INTF_OFST 4
26026 #define DESC_PROXY_FUNC_MAP_FUNC_INTF_LEN 4
26031 #define DESC_PROXY_FUNC_MAP_PERSONALITY_LEN 4
26036 /* User-defined label (zero-terminated ASCII string) to uniquely identify the
26055 #define MC_CMD_DESC_PROXY_FUNC_ENUM_IN_LEN 4
26060 #define MC_CMD_DESC_PROXY_FUNC_ENUM_IN_START_IDX_LEN 4
26063 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LENMIN 4
26066 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LEN(num) (4+52*(num))
26067 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_NUM(len) (((len)-4)/52)
26069 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FLAGS_LEN 4
26072 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_WIDTH 1
26074 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_OFST 4
26077 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_MAXNUM 4
26090 * supports multi-queue devices and has no dependency on host driver attach.
26103 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_HANDLE_LEN 4
26107 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_TARGET_EVQ_OFST 4
26108 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_TARGET_EVQ_LEN 4
26114 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_COUNT_LEN 4
26116 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_BASE_OFST 4
26117 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_BASE_LEN 4
26124 * source function (0 to max_virtqueues-1). For a multi-queue device, the
26141 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_HANDLE_LEN 4
26143 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_SOURCE_QUEUE_OFST 4
26144 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_SOURCE_QUEUE_LEN 4
26149 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_TARGET_EVQ_LEN 4
26157 * Disable descriptor proxying for function. For multi-queue functions,
26166 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_IN_LEN 4
26171 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_IN_HANDLE_LEN 4
26192 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_IN_HANDLE_LEN 4
26194 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_IN_SOURCE_QUEUE_OFST 4
26195 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_IN_SOURCE_QUEUE_LEN 4
26216 #define MC_CMD_DESC_PROXY_GET_VI_INFO_IN_LEN 4
26221 #define MC_CMD_DESC_PROXY_GET_VI_INFO_IN_HANDLE_LEN 4
26227 #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_LEN(num) (0+4*(num))
26228 #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_NUM(len) (((len)-0)/4)
26230 * queues (in order from 0 to max_virtqueues-1), as array of QUEUE_ID
26234 #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_LEN 4
26241 #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_REL_QUEUE_WIDTH 1
26249 * target. See SF-120734-TC for details on ADDR_SPC_IDs and mem2mem
26261 #define MC_CMD_GET_ADDR_SPC_ID_IN_TYPE_LEN 4
26288 /* enum: Address space ID for DMA to/from other SmartNIC memory (on-chip, DDR)
26294 #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_OFST 4
26296 #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_OFST 4
26297 #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_LEN 4
26301 #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_LEN 4
26304 #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_PF_OFST 4
26309 #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_INTF_LEN 4
26312 #define MC_CMD_GET_ADDR_SPC_ID_IN_PASID_LEN 4
26315 #define MC_CMD_GET_ADDR_SPC_ID_IN_VI_LEN 4
26318 #define MC_CMD_GET_ADDR_SPC_ID_IN_HANDLE_OFST 4
26319 #define MC_CMD_GET_ADDR_SPC_ID_IN_HANDLE_LEN 4
26329 #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_LEN 4
26332 #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_OFST 4
26333 #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_LEN 4
26354 #define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_LEN 4
26355 /* enum: Obtain a client handle for a PCIe function-type client. */
26357 /* PCIe Function ID (as struct PCIE_FUNCTION). Valid when TYPE==FUNC. Use: -
26358 * INTF=CALLER, PF=PF_NULL, VF=VF_NULL to refer to the calling function -
26360 * a sibling VF of the calling VF. - INTF=CALLER, PF=..., VF=VF_NULL to refer
26361 * to a PF on the calling interface - INTF=CALLER, PF=..., VF=... to refer to a
26362 * VF on the calling interface - INTF=..., PF=..., VF=VF_NULL to refer to a PF
26363 * on a named interface - INTF=..., PF=..., VF=... to refer to a VF on a named
26369 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_OFST 4
26371 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_OFST 4
26372 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_LEN 4
26376 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_LEN 4
26383 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_PF_OFST 4
26388 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_INTF_LEN 4
26391 #define MC_CMD_GET_CLIENT_HANDLE_OUT_LEN 4
26393 #define MC_CMD_GET_CLIENT_HANDLE_OUT_HANDLE_LEN 4
26396 #define MAE_FIELD_FLAGS_LEN 4
26398 #define MAE_FIELD_FLAGS_FLAT_LEN 4
26404 #define MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS_WIDTH 1
26407 #define MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS_WIDTH 1
26422 #define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_LEN 4
26425 #define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_MASK_OFST 4
26426 #define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_MASK_LEN 4
26486 #define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_LEN 4
26490 #define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_MASK_LEN 4
26502 #define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_LEN 4
26506 #define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_MASK_LEN 4
26518 #define MAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_LEN 1
26522 #define MAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_MASK_LEN 1
26526 #define MAE_ENC_FIELD_PAIRS_ENC_IP_TOS_LEN 1
26530 #define MAE_ENC_FIELD_PAIRS_ENC_IP_TOS_MASK_LEN 1
26534 #define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_LEN 1
26538 #define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_LEN 1
26543 #define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_LEN 1
26546 #define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_WIDTH 1
26548 #define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_LBN 1
26549 #define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_WIDTH 1
26552 #define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_WIDTH 1
26557 #define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_LEN 1
26562 #define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_LEN 1
26565 #define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_WIDTH 1
26567 #define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_MASK_LBN 1
26568 #define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_MASK_WIDTH 1
26571 #define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_MASK_WIDTH 1
26576 #define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_LEN 1
26580 #define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_LEN 4
26584 #define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_MASK_LEN 4
26609 #define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_LEN 4
26612 #define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_MASK_OFST 4
26613 #define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_MASK_LEN 4
26617 #define MAE_FIELD_MASK_VALUE_PAIRS_MARK_LEN 4
26621 #define MAE_FIELD_MASK_VALUE_PAIRS_MARK_MASK_LEN 4
26681 #define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_LEN 4
26685 #define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_MASK_LEN 4
26697 #define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_LEN 4
26701 #define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_MASK_LEN 4
26713 #define MAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_LEN 1
26717 #define MAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_MASK_LEN 1
26721 #define MAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_LEN 1
26725 #define MAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_MASK_LEN 1
26730 * other than 1.
26733 #define MAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_LEN 1
26737 #define MAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_MASK_LEN 1
26741 #define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_LEN 4
26745 #define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_MASK_LEN 4
26773 #define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_LEN 4
26777 #define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_MASK_LEN 4
26781 #define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_LEN 4
26785 #define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_MASK_LEN 4
26845 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_LEN 4
26849 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_MASK_LEN 4
26861 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_LEN 4
26865 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_MASK_LEN 4
26877 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_LEN 1
26881 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_MASK_LEN 1
26885 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_LEN 1
26889 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_MASK_LEN 1
26893 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_LEN 1
26897 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_MASK_LEN 1
26901 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_LEN 4
26905 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_MASK_LEN 4
26925 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_LEN 4
26929 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_MASK_LEN 4
26936 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_LEN 4
26939 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_MASK_OFST 4
26940 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_MASK_LEN 4
26944 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_LEN 4
26948 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_MASK_LEN 4
27008 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_LEN 4
27012 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_MASK_LEN 4
27024 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_LEN 4
27028 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_MASK_LEN 4
27040 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_LEN 1
27044 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_MASK_LEN 1
27048 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_LEN 1
27052 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_MASK_LEN 1
27057 * other than 1.
27060 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_LEN 1
27064 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_MASK_LEN 1
27068 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_LEN 4
27072 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_MASK_LEN 4
27100 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_LEN 4
27104 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_MASK_LEN 4
27108 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_LEN 4
27112 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_MASK_LEN 4
27172 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_LEN 4
27176 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_MASK_LEN 4
27188 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_LEN 4
27192 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_MASK_LEN 4
27204 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_LEN 1
27208 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_MASK_LEN 1
27212 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_LEN 1
27216 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_MASK_LEN 1
27220 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_LEN 1
27224 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_MASK_LEN 1
27228 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_LEN 4
27232 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_MASK_LEN 4
27252 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_LEN 4
27256 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_MASK_LEN 4
27260 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_LEN 4
27263 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_IP_FRAG_WIDTH 1
27265 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_DO_CT_LBN 1
27266 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_DO_CT_WIDTH 1
27269 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_HIT_WIDTH 1
27272 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_WIDTH 1
27274 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_LBN 4
27275 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_WIDTH 1
27278 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_IVLAN_WIDTH 1
27281 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_OVLAN_WIDTH 1
27284 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_IVLAN_WIDTH 1
27287 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_SYN_FIN_RST_WIDTH 1
27290 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FIRST_FRAG_WIDTH 1
27294 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_LEN 4
27306 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_LEN 4
27310 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_MASK_LEN 4
27314 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_LEN 1
27319 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD2_LEN 1
27323 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_MASK_LEN 1
27328 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD3_LEN 1
27332 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_LEN 1
27337 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD4_LEN 1
27341 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_MASK_LEN 1
27346 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD5_LEN 1
27352 * 32-bits or within any NIC interface field that needs store the value
27354 * refer to m-ports.
27356 #define MAE_MPORT_SELECTOR_LEN 4
27357 /* Used to force the tools to output bitfield-style defines for this structure.
27360 #define MAE_MPORT_SELECTOR_FLAT_LEN 4
27361 /* enum: An m-port selector value that is guaranteed never to represent a real
27365 /* enum: The m-port assigned to the calling client. */
27378 /* enum: The MPORT assigned to a given PCIe function (see also FWRIVERHD-1108)
27388 #define MAE_MPORT_SELECTOR_PPORT_ID_WIDTH 4
27391 #define MAE_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
27399 #define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
27409 * client. - When used by a PF with VF_ID == VF_ID_NULL, the mport selector
27411 * clients use ASSIGNED to achieve this behaviour). - When used by a PF with
27413 * function. - When used by a VF with VF_ID == VF_ID_NULL, the mport selector
27414 * relates to the PF owning the calling function. - When used by a VF with
27416 * calling function. - Not meaningful used by a client that is not a PCIe
27433 #define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_LEN 4
27437 #define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_OFST 4
27438 #define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_LEN 4
27447 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_LEN 4
27450 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_OFST 4
27451 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_LEN 4
27454 /* enum: Set FLAT to this value to obtain backward-compatible behaviour in
27466 * Describes capabilities of the MAE (Match-Action Engine)
27483 #define MC_CMD_MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT_LEN 4
27484 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPES_SUPPORTED_OFST 4
27485 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPES_SUPPORTED_LEN 4
27486 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN_OFST 4
27488 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN_WIDTH 1
27489 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE_OFST 4
27490 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE_LBN 1
27491 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE_WIDTH 1
27492 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_OFST 4
27494 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_WIDTH 1
27495 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_OFST 4
27497 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_WIDTH 1
27500 #define MC_CMD_MAE_GET_CAPS_OUT_COUNTERS_LEN 4
27503 #define MC_CMD_MAE_GET_CAPS_OUT_AR_COUNTERS_LEN 4
27509 #define MC_CMD_MAE_GET_CAPS_OUT_COUNTER_LISTS_LEN 4
27512 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_HEADER_LIMIT_LEN 4
27515 #define MC_CMD_MAE_GET_CAPS_OUT_RSVD_LEN 4
27518 #define MC_CMD_MAE_GET_CAPS_OUT_ACTION_SETS_LEN 4
27521 #define MC_CMD_MAE_GET_CAPS_OUT_ACTION_SET_LISTS_LEN 4
27524 #define MC_CMD_MAE_GET_CAPS_OUT_OUTER_RULES_LEN 4
27527 #define MC_CMD_MAE_GET_CAPS_OUT_ACTION_RULES_LEN 4
27532 #define MC_CMD_MAE_GET_CAPS_OUT_ACTION_PRIOS_LEN 4
27537 #define MC_CMD_MAE_GET_CAPS_OUT_OUTER_PRIOS_LEN 4
27538 /* MAE API major version. Currently 1. If this field is not present in the
27544 #define MC_CMD_MAE_GET_CAPS_OUT_API_VER_LEN 4
27553 #define MC_CMD_MAE_GET_CAPS_V2_OUT_MATCH_FIELD_COUNT_LEN 4
27554 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPES_SUPPORTED_OFST 4
27555 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPES_SUPPORTED_LEN 4
27556 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_VXLAN_OFST 4
27558 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_VXLAN_WIDTH 1
27559 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_NVGRE_OFST 4
27560 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_NVGRE_LBN 1
27561 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_NVGRE_WIDTH 1
27562 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_GENEVE_OFST 4
27564 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_GENEVE_WIDTH 1
27565 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_L2GRE_OFST 4
27567 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_L2GRE_WIDTH 1
27570 #define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTERS_LEN 4
27573 #define MC_CMD_MAE_GET_CAPS_V2_OUT_AR_COUNTERS_LEN 4
27579 #define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTER_LISTS_LEN 4
27582 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_HEADER_LIMIT_LEN 4
27585 #define MC_CMD_MAE_GET_CAPS_V2_OUT_RSVD_LEN 4
27588 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_SETS_LEN 4
27591 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_SET_LISTS_LEN 4
27594 #define MC_CMD_MAE_GET_CAPS_V2_OUT_OUTER_RULES_LEN 4
27597 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_RULES_LEN 4
27602 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_PRIOS_LEN 4
27607 #define MC_CMD_MAE_GET_CAPS_V2_OUT_OUTER_PRIOS_LEN 4
27608 /* MAE API major version. Currently 1. If this field is not present in the
27614 #define MC_CMD_MAE_GET_CAPS_V2_OUT_API_VER_LEN 4
27622 #define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTER_TYPES_SUPPORTED_LEN 4
27625 #define MC_CMD_MAE_GET_CAPS_V2_OUT_CT_COUNTERS_LEN 4
27634 #define MC_CMD_MAE_GET_CAPS_V3_OUT_MATCH_FIELD_COUNT_LEN 4
27635 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPES_SUPPORTED_OFST 4
27636 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPES_SUPPORTED_LEN 4
27637 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_VXLAN_OFST 4
27639 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_VXLAN_WIDTH 1
27640 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_NVGRE_OFST 4
27641 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_NVGRE_LBN 1
27642 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_NVGRE_WIDTH 1
27643 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_GENEVE_OFST 4
27645 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_GENEVE_WIDTH 1
27646 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_L2GRE_OFST 4
27648 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_L2GRE_WIDTH 1
27651 #define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTERS_LEN 4
27654 #define MC_CMD_MAE_GET_CAPS_V3_OUT_AR_COUNTERS_LEN 4
27660 #define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTER_LISTS_LEN 4
27663 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_HEADER_LIMIT_LEN 4
27666 #define MC_CMD_MAE_GET_CAPS_V3_OUT_RSVD_LEN 4
27669 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_SETS_LEN 4
27672 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_SET_LISTS_LEN 4
27675 #define MC_CMD_MAE_GET_CAPS_V3_OUT_OUTER_RULES_LEN 4
27678 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_RULES_LEN 4
27683 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_PRIOS_LEN 4
27688 #define MC_CMD_MAE_GET_CAPS_V3_OUT_OUTER_PRIOS_LEN 4
27689 /* MAE API major version. Currently 1. If this field is not present in the
27695 #define MC_CMD_MAE_GET_CAPS_V3_OUT_API_VER_LEN 4
27703 #define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTER_TYPES_SUPPORTED_LEN 4
27706 #define MC_CMD_MAE_GET_CAPS_V3_OUT_CT_COUNTERS_LEN 4
27709 #define MC_CMD_MAE_GET_CAPS_V3_OUT_OR_COUNTERS_LEN 4
27714 * Get a level of support for match fields when used in match-action rules
27725 #define MC_CMD_MAE_GET_AR_CAPS_OUT_LENMIN 4
27728 #define MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(num) (4+4*(num))
27729 #define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_NUM(len) (((len)-4)/4)
27732 #define MC_CMD_MAE_GET_AR_CAPS_OUT_COUNT_LEN 4
27737 #define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_OFST 4
27738 #define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_LEN 4
27757 #define MC_CMD_MAE_GET_OR_CAPS_OUT_LENMIN 4
27760 #define MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(num) (4+4*(num))
27761 #define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_NUM(len) (((len)-4)/4)
27764 #define MC_CMD_MAE_GET_OR_CAPS_OUT_COUNT_LEN 4
27766 #define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_OFST 4
27767 #define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_LEN 4
27775 * Allocate match-action-engine counters, which can be referenced in various
27786 #define MC_CMD_MAE_COUNTER_ALLOC_IN_LEN 4
27789 #define MC_CMD_MAE_COUNTER_ALLOC_IN_REQUESTED_COUNT_LEN 4
27795 #define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_REQUESTED_COUNT_LEN 4
27797 #define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_COUNTER_TYPE_OFST 4
27798 #define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_COUNTER_TYPE_LEN 4
27806 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_LEN(num) (8+4*(num))
27807 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_NUM(len) (((len)-8)/4)
27812 * counts wrap from 0xffffffff to 1.
27815 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_GENERATION_COUNT_LEN 4
27818 /* The number of counter IDs that the NIC allocated. It is never less than 1;
27822 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_COUNT_OFST 4
27823 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_COUNT_LEN 4
27826 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_LEN 4
27827 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_MINNUM 1
27836 * Free match-action-engine counters
27849 #define MC_CMD_MAE_COUNTER_FREE_IN_LEN(num) (4+4*(num))
27850 #define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_NUM(len) (((len)-4)/4)
27853 #define MC_CMD_MAE_COUNTER_FREE_IN_COUNTER_ID_COUNT_LEN 4
27855 #define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_OFST 4
27856 #define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_LEN 4
27857 #define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_MINNUM 1
27865 #define MC_CMD_MAE_COUNTER_FREE_V2_IN_COUNTER_ID_COUNT_LEN 4
27867 #define MC_CMD_MAE_COUNTER_FREE_V2_IN_FREE_COUNTER_ID_OFST 4
27868 #define MC_CMD_MAE_COUNTER_FREE_V2_IN_FREE_COUNTER_ID_LEN 4
27869 #define MC_CMD_MAE_COUNTER_FREE_V2_IN_FREE_COUNTER_ID_MINNUM 1
27874 #define MC_CMD_MAE_COUNTER_FREE_V2_IN_COUNTER_TYPE_LEN 4
27882 #define MC_CMD_MAE_COUNTER_FREE_OUT_LEN(num) (8+4*(num))
27883 #define MC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_NUM(len) (((len)-8)/4)
27896 #define MC_CMD_MAE_COUNTER_FREE_OUT_GENERATION_COUNT_LEN 4
27897 /* The number of counter IDs actually freed. It is never less than 1; failure
27902 #define MC_CMD_MAE_COUNTER_FREE_OUT_COUNTER_ID_COUNT_OFST 4
27903 #define MC_CMD_MAE_COUNTER_FREE_OUT_COUNTER_ID_COUNT_LEN 4
27911 #define MC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_LEN 4
27912 #define MC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_MINNUM 1
27943 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_FLAGS_OFST 4
27944 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_FLAGS_LEN 4
27945 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_ZERO_SQUASH_DISABLE_OFST 4
27947 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_ZERO_SQUASH_DISABLE_WIDTH 1
27948 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_COUNTER_STALL_EN_OFST 4
27949 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_COUNTER_STALL_EN_LBN 1
27950 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_COUNTER_STALL_EN_WIDTH 1
27961 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_FLAGS_OFST 4
27962 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_FLAGS_LEN 4
27963 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_ZERO_SQUASH_DISABLE_OFST 4
27965 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_ZERO_SQUASH_DISABLE_WIDTH 1
27966 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_COUNTER_STALL_EN_OFST 4
27967 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_COUNTER_STALL_EN_LBN 1
27968 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_COUNTER_STALL_EN_WIDTH 1
27979 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_COUNTER_TYPES_MASK_LEN 4
27982 #define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_LEN 4
27984 #define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_FLAGS_LEN 4
27987 #define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_USES_CREDITS_WIDTH 1
28006 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_LEN 4
28014 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_GENERATION_COUNT_LEN 4
28017 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_LENMIN 4
28020 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_LEN(num) (0+4*(num))
28021 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_NUM(len) (((len)-0)/4)
28023 * MAE_COUNTER_TYPE_AR==0, this response is backwards-compatible with V1. The
28030 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_LEN 4
28031 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_MINNUM 1
28049 #define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_LEN 4
28052 #define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_NUM_CREDITS_LEN 4
28061 * header must be constructed as a valid packet with 0-length payload.
28073 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LENMIN 4
28076 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LEN(num) (4+1*(num))
28077 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_NUM(len) (((len)-4)/1)
28079 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_ENCAP_TYPE_LEN 4
28080 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_OFST 4
28081 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_LEN 1
28087 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_LEN 4
28089 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID_LEN 4
28109 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_LEN(num) (8+1*(num))
28110 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_NUM(len) (((len)-8)/1)
28112 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_EH_ID_LEN 4
28113 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_ENCAP_TYPE_OFST 4
28114 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_ENCAP_TYPE_LEN 4
28116 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_LEN 1
28135 #define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_LENMIN 4
28138 #define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_LEN(num) (0+4*(num))
28139 #define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_NUM(len) (((len)-0)/4)
28142 #define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_LEN 4
28143 #define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_MINNUM 1
28148 #define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LENMIN 4
28151 #define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LEN(num) (0+4*(num))
28152 #define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_NUM(len) (((len)-0)/4)
28155 #define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_LEN 4
28156 #define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_MINNUM 1
28181 #define MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_LEN 4
28183 #define MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_LEN 4
28200 #define MC_CMD_MAE_MAC_ADDR_FREE_IN_LENMIN 4
28203 #define MC_CMD_MAE_MAC_ADDR_FREE_IN_LEN(num) (0+4*(num))
28204 #define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_NUM(len) (((len)-0)/4)
28207 #define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_LEN 4
28208 #define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_MINNUM 1
28213 #define MC_CMD_MAE_MAC_ADDR_FREE_OUT_LENMIN 4
28216 #define MC_CMD_MAE_MAC_ADDR_FREE_OUT_LEN(num) (0+4*(num))
28217 #define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_NUM(len) (((len)-0)/4)
28220 #define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_LEN 4
28221 #define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_MINNUM 1
28241 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAGS_LEN 4
28246 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_POP_LBN 4
28250 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DECAP_WIDTH 1
28253 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_WIDTH 1
28256 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAG_WIDTH 1
28259 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_WIDTH 1
28262 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_WIDTH 1
28265 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_WIDTH 1
28268 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_WIDTH 1
28269 /* If VLAN_PUSH >= 1, TCI value to be inserted as outermost VLAN. */
28270 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE_OFST 4
28272 /* If VLAN_PUSH >= 1, TPID value to be inserted as outermost VLAN. */
28283 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_RSVD_LEN 4
28286 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID_LEN 4
28287 /* An m-port selector identifying the m-port that the modified packet should be
28292 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DELIVER_LEN 4
28297 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID_LEN 4
28299 * it can supply a COUNTER_ID instead of allocating a single-element counter
28302 * not valid to supply a non-NULL value for both COUNTER_LIST_ID and
28306 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_ID_LEN 4
28308 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_VALUE_LEN 4
28311 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID_LEN 4
28314 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID_LEN 4
28322 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAGS_LEN 4
28327 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_LBN 4
28331 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_WIDTH 1
28334 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_WIDTH 1
28337 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_WIDTH 1
28340 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_WIDTH 1
28343 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_WIDTH 1
28346 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_WIDTH 1
28349 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_WIDTH 1
28350 /* If VLAN_PUSH >= 1, TCI value to be inserted as outermost VLAN. */
28351 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_TCI_BE_OFST 4
28353 /* If VLAN_PUSH >= 1, TPID value to be inserted as outermost VLAN. */
28364 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_RSVD_LEN 4
28367 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ENCAP_HEADER_ID_LEN 4
28368 /* An m-port selector identifying the m-port that the modified packet should be
28373 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DELIVER_LEN 4
28378 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_LIST_ID_LEN 4
28380 * it can supply a COUNTER_ID instead of allocating a single-element counter
28383 * not valid to supply a non-NULL value for both COUNTER_LIST_ID and
28387 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_ID_LEN 4
28389 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_VALUE_LEN 4
28392 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SRC_MAC_ID_LEN 4
28395 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DST_MAC_ID_LEN 4
28396 /* Source m-port ID to be reported for DO_SET_SRC_MPORT action. */
28398 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_REPORTED_SRC_MPORT_LEN 4
28399 /* Actions for modifying the Differentiated Services Code-Point (DSCP) bits
28406 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_WIDTH 1
28408 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_DECAP_COPY_LBN 1
28409 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_DECAP_COPY_WIDTH 1
28412 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_DSCP_WIDTH 1
28420 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_CONTROL_LEN 1
28423 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_WIDTH 1
28425 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_DECAP_COPY_LBN 1
28426 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_DECAP_COPY_WIDTH 1
28429 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_ECN_WIDTH 1
28435 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_0_TO_CE_WIDTH 1
28438 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_WIDTH 1
28441 #define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN 4
28447 #define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_AS_ID_LEN 4
28462 #define MC_CMD_MAE_ACTION_SET_FREE_IN_LENMIN 4
28465 #define MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(num) (0+4*(num))
28466 #define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_NUM(len) (((len)-0)/4)
28469 #define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_LEN 4
28470 #define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_MINNUM 1
28475 #define MC_CMD_MAE_ACTION_SET_FREE_OUT_LENMIN 4
28478 #define MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(num) (0+4*(num))
28479 #define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_NUM(len) (((len)-0)/4)
28482 #define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_LEN 4
28483 #define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_MINNUM 1
28505 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_LEN(num) (4+4*(num))
28506 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_NUM(len) (((len)-4)/4)
28509 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_COUNT_LEN 4
28519 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_OFST 4
28520 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_LEN 4
28521 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_MINNUM 1
28526 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_LEN 4
28531 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ASL_ID_LEN 4
28540 * Free match-action-engine redirect_lists
28548 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LENMIN 4
28551 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LEN(num) (0+4*(num))
28552 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_NUM(len) (((len)-0)/4)
28555 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_LEN 4
28556 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_MINNUM 1
28561 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_LENMIN 4
28564 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_LEN(num) (0+4*(num))
28565 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_NUM(len) (((len)-0)/4)
28568 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_LEN 4
28569 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_MINNUM 1
28589 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_LEN(num) (16+1*(num))
28590 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_NUM(len) (((len)-16)/1)
28593 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE_LEN 4
28600 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_PRIO_OFST 4
28601 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_PRIO_LEN 4
28604 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_LOOKUP_CONTROL_LEN 4
28607 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_DO_CT_WIDTH 1
28609 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_VNI_MODE_LBN 1
28615 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_DO_COUNT_WIDTH 1
28617 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_TCP_FLAGS_INHIBIT_LBN 4
28618 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_TCP_FLAGS_INHIBIT_WIDTH 1
28627 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_ACTION_CONTROL_LEN 4
28632 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_COUNTER_ID_LEN 4
28635 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_LEN 1
28641 #define MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN 4
28643 #define MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_LEN 4
28658 #define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LENMIN 4
28661 #define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(num) (0+4*(num))
28662 #define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_NUM(len) (((len)-0)/4)
28665 #define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_LEN 4
28666 #define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_MINNUM 1
28671 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LENMIN 4
28674 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(num) (0+4*(num))
28675 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_NUM(len) (((len)-0)/4)
28678 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_LEN 4
28679 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_MINNUM 1
28697 #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_OR_ID_LEN 4
28699 #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_ENCAP_TYPE_OFST 4
28700 #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_ENCAP_TYPE_LEN 4
28705 #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_ACTION_CONTROL_LEN 4
28708 #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_DO_CT_WIDTH 1
28710 #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_VNI_MODE_LBN 1
28716 #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_DO_COUNT_WIDTH 1
28718 #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_TCP_FLAGS_INHIBIT_LBN 4
28719 #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_TCP_FLAGS_INHIBIT_WIDTH 1
28730 #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_COUNTER_ID_LEN 4
28738 #define MAE_ACTION_RULE_RESPONSE_ASL_ID_LEN 4
28741 /* Only one of ASL_ID or AS_ID may have a non-NULL value. */
28742 #define MAE_ACTION_RULE_RESPONSE_AS_ID_OFST 4
28743 #define MAE_ACTION_RULE_RESPONSE_AS_ID_LEN 4
28746 /* Controls lookup flow when this rule is hit. See sub-fields for details. More
28747 * info on the lookup sequence can be found in SF-122976-TC. It is an error to
28751 #define MAE_ACTION_RULE_RESPONSE_LOOKUP_CONTROL_LEN 4
28754 #define MAE_ACTION_RULE_RESPONSE_DO_CT_WIDTH 1
28756 #define MAE_ACTION_RULE_RESPONSE_DO_RECIRC_LBN 1
28757 #define MAE_ACTION_RULE_RESPONSE_DO_RECIRC_WIDTH 1
28776 #define MAE_ACTION_RULE_RESPONSE_COUNTER_ID_LEN 4
28797 #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_LEN(num) (28+1*(num))
28798 #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_NUM(len) (((len)-28)/1)
28801 #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_PRIO_LEN 4
28803 #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_OFST 4
28807 #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_RSVD_LEN 4
28810 #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_LEN 1
28816 #define MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN 4
28818 #define MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_LEN 4
28838 #define MC_CMD_MAE_ACTION_RULE_UPDATE_IN_AR_ID_LEN 4
28840 #define MC_CMD_MAE_ACTION_RULE_UPDATE_IN_RESPONSE_OFST 4
28856 #define MC_CMD_MAE_ACTION_RULE_DELETE_IN_LENMIN 4
28859 #define MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(num) (0+4*(num))
28860 #define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_NUM(len) (((len)-0)/4)
28863 #define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_LEN 4
28864 #define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_MINNUM 1
28869 #define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LENMIN 4
28872 #define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(num) (0+4*(num))
28873 #define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_NUM(len) (((len)-0)/4)
28876 #define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_LEN 4
28877 #define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_MINNUM 1
28884 * Return the m-port corresponding to a selector.
28892 #define MC_CMD_MAE_MPORT_LOOKUP_IN_LEN 4
28894 #define MC_CMD_MAE_MPORT_LOOKUP_IN_MPORT_SELECTOR_LEN 4
28897 #define MC_CMD_MAE_MPORT_LOOKUP_OUT_LEN 4
28899 #define MC_CMD_MAE_MPORT_LOOKUP_OUT_MPORT_ID_LEN 4
28904 * Allocates a m-port, which can subsequently be used in action rules as a
28914 /* The type of m-port to allocate. Firmware may return ENOTSUP for certain
28918 #define MC_CMD_MAE_MPORT_ALLOC_IN_TYPE_LEN 4
28919 /* enum: Traffic can be sent to this type of m-port using an override
28920 * descriptor. Traffic received on this type of m-port will go to the VNIC on a
28921 * nominated m-port, and will be delivered with metadata identifying the alias
28922 * m-port.
28925 /* enum: This type of m-port has a VNIC attached. Queues can be created on this
28926 * VNIC by specifying the created m-port as an m-port selector at queue
28930 /* 128-bit value for use by the driver. */
28931 #define MC_CMD_MAE_MPORT_ALLOC_IN_UUID_OFST 4
28936 /* The type of m-port to allocate. Firmware may return ENOTSUP for certain
28940 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_TYPE_LEN 4
28941 /* enum: Traffic can be sent to this type of m-port using an override
28942 * descriptor. Traffic received on this type of m-port will go to the VNIC on a
28943 * nominated m-port, and will be delivered with metadata identifying the alias
28944 * m-port.
28947 /* enum: This type of m-port has a VNIC attached. Queues can be created on this
28948 * VNIC by specifying the created m-port as an m-port selector at queue
28952 /* 128-bit value for use by the driver. */
28953 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_UUID_OFST 4
28955 /* An m-port selector identifying the VNIC to which traffic should be
28957 * the m-port assigned to the calling client).
28960 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_DELIVER_MPORT_LEN 4
28964 /* The type of m-port to allocate. Firmware may return ENOTSUP for certain
28968 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_TYPE_LEN 4
28969 /* enum: Traffic can be sent to this type of m-port using an override
28970 * descriptor. Traffic received on this type of m-port will go to the VNIC on a
28971 * nominated m-port, and will be delivered with metadata identifying the alias
28972 * m-port.
28975 /* enum: This type of m-port has a VNIC attached. Queues can be created on this
28976 * VNIC by specifying the created m-port as an m-port selector at queue
28980 /* 128-bit value for use by the driver. */
28981 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_UUID_OFST 4
28985 #define MC_CMD_MAE_MPORT_ALLOC_OUT_LEN 4
28986 /* ID of newly-allocated m-port. */
28988 #define MC_CMD_MAE_MPORT_ALLOC_OUT_MPORT_ID_LEN 4
28992 /* ID of newly-allocated m-port. */
28994 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_MPORT_ID_LEN 4
28996 * using an alias type m-port. This value is guaranteed unique on the VNIC
29001 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_LABEL_LEN 4
29004 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_OUT_LEN 4
29005 /* ID of newly-allocated m-port. */
29007 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_OUT_MPORT_ID_LEN 4
29012 * Free a m-port which was previously allocated by the driver.
29020 #define MC_CMD_MAE_MPORT_FREE_IN_LEN 4
29023 #define MC_CMD_MAE_MPORT_FREE_IN_MPORT_ID_LEN 4
29031 #define MAE_MPORT_DESC_MPORT_ID_LEN 4
29035 #define MAE_MPORT_DESC_FLAGS_OFST 4
29036 #define MAE_MPORT_DESC_FLAGS_LEN 4
29040 #define MAE_MPORT_DESC_CALLER_FLAGS_LEN 4
29043 #define MAE_MPORT_DESC_CAN_RECEIVE_ON_WIDTH 1
29045 #define MAE_MPORT_DESC_CAN_DELIVER_TO_LBN 1
29046 #define MAE_MPORT_DESC_CAN_DELIVER_TO_WIDTH 1
29049 #define MAE_MPORT_DESC_CAN_DELETE_WIDTH 1
29052 #define MAE_MPORT_DESC_IS_ZOMBIE_WIDTH 1
29055 /* Not the ideal name; it's really the type of thing connected to the m-port */
29057 #define MAE_MPORT_DESC_MPORT_TYPE_LEN 4
29060 /* enum: Adds metadata and delivers to another m-port */
29066 /* 128-bit value available to drivers for m-port identification. */
29075 #define MAE_MPORT_DESC_RESERVED_LO_LEN 4
29079 #define MAE_MPORT_DESC_RESERVED_HI_LEN 4
29086 #define MAE_MPORT_DESC_NET_PORT_IDX_LEN 4
29089 /* The m-port delivered to */
29091 #define MAE_MPORT_DESC_ALIAS_DELIVER_MPORT_ID_LEN 4
29096 #define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_LEN 4
29106 #define MAE_MPORT_DESC_VNIC_FUNCTION_INTERFACE_LEN 4
29121 #define MAE_MPORT_DESC_VNIC_PLUGIN_TBD_LEN 4
29128 #define MAE_MPORT_DESC_V2_MPORT_ID_LEN 4
29132 #define MAE_MPORT_DESC_V2_FLAGS_OFST 4
29133 #define MAE_MPORT_DESC_V2_FLAGS_LEN 4
29137 #define MAE_MPORT_DESC_V2_CALLER_FLAGS_LEN 4
29140 #define MAE_MPORT_DESC_V2_CAN_RECEIVE_ON_WIDTH 1
29142 #define MAE_MPORT_DESC_V2_CAN_DELIVER_TO_LBN 1
29143 #define MAE_MPORT_DESC_V2_CAN_DELIVER_TO_WIDTH 1
29146 #define MAE_MPORT_DESC_V2_CAN_DELETE_WIDTH 1
29149 #define MAE_MPORT_DESC_V2_IS_ZOMBIE_WIDTH 1
29152 /* Not the ideal name; it's really the type of thing connected to the m-port */
29154 #define MAE_MPORT_DESC_V2_MPORT_TYPE_LEN 4
29157 /* enum: Adds metadata and delivers to another m-port */
29163 /* 128-bit value available to drivers for m-port identification. */
29172 #define MAE_MPORT_DESC_V2_RESERVED_LO_LEN 4
29176 #define MAE_MPORT_DESC_V2_RESERVED_HI_LEN 4
29183 #define MAE_MPORT_DESC_V2_NET_PORT_IDX_LEN 4
29186 /* The m-port delivered to */
29188 #define MAE_MPORT_DESC_V2_ALIAS_DELIVER_MPORT_ID_LEN 4
29193 #define MAE_MPORT_DESC_V2_VNIC_CLIENT_TYPE_LEN 4
29203 #define MAE_MPORT_DESC_V2_VNIC_FUNCTION_INTERFACE_LEN 4
29218 #define MAE_MPORT_DESC_V2_VNIC_PLUGIN_TBD_LEN 4
29223 #define MAE_MPORT_DESC_V2_VNIC_CLIENT_HANDLE_LEN 4
29245 #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_LEN(num) (8+1*(num))
29246 #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_NUM(len) (((len)-8)/1)
29248 #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_COUNT_LEN 4
29249 #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_SIZEOF_MPORT_DESC_OFST 4
29250 #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_SIZEOF_MPORT_DESC_LEN 4
29256 #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_LEN 1
29264 * Firmware maintains a per-client journal of mport creations and deletions.
29265 * This journal is clear-on-read, i.e. repeated calls of this command will
29275 #define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_LEN 4
29278 #define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_FLAGS_LEN 4
29284 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LEN(num) (12+1*(num))
29285 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_NUM(len) (((len)-12)/1)
29288 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_FLAGS_LEN 4
29291 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_WIDTH 1
29293 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_COUNT_OFST 4
29294 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_COUNT_LEN 4
29296 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_SIZEOF_MPORT_DESC_LEN 4
29302 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_LEN 1
29308 * describes the location and properties of one N-bit field within a wider
29309 * M-bit key/mask/response value.
29325 #define TABLE_FIELD_DESCR_WIDTH_OFST 4
29333 #define TABLE_FIELD_DESCR_MASK_TYPE_LEN 1
29340 /* enum: Whole field match: mask must be all 1 bits, or all 0 bits. */
29342 /* enum: Longest prefix match: mask must be 1 bit(s) followed by 0 bit(s). */
29350 #define TABLE_FIELD_DESCR_SCHEME_LEN 1
29365 #define MC_CMD_TABLE_LIST_IN_LEN 4
29371 #define MC_CMD_TABLE_LIST_IN_FIRST_TABLE_ID_INDEX_LEN 4
29374 #define MC_CMD_TABLE_LIST_OUT_LENMIN 4
29377 #define MC_CMD_TABLE_LIST_OUT_LEN(num) (4+4*(num))
29378 #define MC_CMD_TABLE_LIST_OUT_TABLE_ID_NUM(len) (((len)-4)/4)
29381 #define MC_CMD_TABLE_LIST_OUT_N_TABLES_LEN 4
29383 * items can be obtained by repeating the call with a non-zero
29386 #define MC_CMD_TABLE_LIST_OUT_TABLE_ID_OFST 4
29387 #define MC_CMD_TABLE_LIST_OUT_TABLE_ID_LEN 4
29410 #define MC_CMD_TABLE_DESCRIPTOR_IN_TABLE_ID_LEN 4
29417 #define MC_CMD_TABLE_DESCRIPTOR_IN_FIRST_FIELDS_INDEX_OFST 4
29418 #define MC_CMD_TABLE_DESCRIPTOR_IN_FIRST_FIELDS_INDEX_LEN 4
29425 #define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_NUM(len) (((len)-20)/8)
29428 #define MC_CMD_TABLE_DESCRIPTOR_OUT_MAX_ENTRIES_LEN 4
29433 #define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_OFST 4
29446 /* enum: STCAM (semi-TCAM) table: like a TCAM but entries shared a limited
29464 * 0=highest to N_PRIORITIES-1=lowest.
29473 #define MC_CMD_TABLE_DESCRIPTOR_OUT_FLAGS_LEN 1
29476 #define MC_CMD_TABLE_DESCRIPTOR_OUT_ALLOC_MASKS_WIDTH 1
29484 #define MC_CMD_TABLE_DESCRIPTOR_OUT_SCHEME_LEN 1
29488 * by repeating the call with a non-zero FIRST_FIELDS_INDEX.
29493 #define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_LO_LEN 4
29497 #define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_HI_LEN 4
29500 #define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_MINNUM 1
29522 #define MC_CMD_TABLE_INSERT_IN_LEN(num) (12+4*(num))
29523 #define MC_CMD_TABLE_INSERT_IN_DATA_NUM(len) (((len)-12)/4)
29526 #define MC_CMD_TABLE_INSERT_IN_TABLE_ID_LEN 4
29530 #define MC_CMD_TABLE_INSERT_IN_KEY_WIDTH_OFST 4
29543 /* Mask ID for STCAM table - used instead of mask data if the table descriptor
29544 * reports ALLOC_MASKS==1. Otherwise set to 0.
29548 /* Priority for TCAM or STCAM, in range 0..N_PRIORITIES-1, otherwise 0. */
29551 /* (32-bit alignment padding - set to 0) */
29555 * data values. Each of these items is logically treated as a single wide N-bit
29558 * N-bit value is padded with 0 bits at the MSB end if necessary to make a
29560 * sequence of 32-bit words, bits [31:0] first, then bits [63:32], etc.
29563 #define MC_CMD_TABLE_INSERT_IN_DATA_LEN 4
29564 #define MC_CMD_TABLE_INSERT_IN_DATA_MINNUM 1
29589 #define MC_CMD_TABLE_UPDATE_IN_LEN(num) (12+4*(num))
29590 #define MC_CMD_TABLE_UPDATE_IN_DATA_NUM(len) (((len)-12)/4)
29593 #define MC_CMD_TABLE_UPDATE_IN_TABLE_ID_LEN 4
29597 #define MC_CMD_TABLE_UPDATE_IN_KEY_WIDTH_OFST 4
29610 /* Mask ID for STCAM table - used instead of mask data if the table descriptor
29611 * reports ALLOC_MASKS==1. Otherwise set to 0.
29615 /* Priority for TCAM or STCAM, in range 0..N_PRIORITIES-1, otherwise 0. */
29618 /* (32-bit alignment padding - set to 0) */
29622 * data values. Each of these items is logically treated as a single wide N-bit
29625 * N-bit value is padded with 0 bits at the MSB end if necessary to make a
29627 * sequence of 32-bit words, bits [31:0] first, then bits [63:32], etc.
29630 #define MC_CMD_TABLE_UPDATE_IN_DATA_LEN 4
29631 #define MC_CMD_TABLE_UPDATE_IN_DATA_MINNUM 1
29656 #define MC_CMD_TABLE_DELETE_IN_LEN(num) (12+4*(num))
29657 #define MC_CMD_TABLE_DELETE_IN_DATA_NUM(len) (((len)-12)/4)
29660 #define MC_CMD_TABLE_DELETE_IN_TABLE_ID_LEN 4
29664 #define MC_CMD_TABLE_DELETE_IN_KEY_WIDTH_OFST 4
29677 /* Mask ID for STCAM table - used instead of mask data if the table descriptor
29678 * reports ALLOC_MASKS==1. Otherwise set to 0.
29682 /* Priority for TCAM or STCAM, in range 0..N_PRIORITIES-1, otherwise 0. */
29685 /* (32-bit alignment padding - set to 0) */
29689 * data values. Each of these items is logically treated as a single wide N-bit
29692 * N-bit value is padded with 0 bits at the MSB end if necessary to make a
29694 * sequence of 32-bit words, bits [31:0] first, then bits [63:32], etc.
29697 #define MC_CMD_TABLE_DELETE_IN_DATA_LEN 4
29698 #define MC_CMD_TABLE_DELETE_IN_DATA_MINNUM 1