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/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_cr_defs_client.h31 #define ROGUE_CR_TE_AA 0x0C00U
32 #define ROGUE_CR_TE_AA_MASKFULL 0x000000000000000Full
38 #define ROGUE_CR_TE_AA_Y2_CLRMSK 0xFFFFFFF7
39 #define ROGUE_CR_TE_AA_Y2_EN 0x00000008
44 #define ROGUE_CR_TE_AA_Y_CLRMSK 0xFFFFFFFB
45 #define ROGUE_CR_TE_AA_Y_EN 0x00000004
50 #define ROGUE_CR_TE_AA_X_CLRMSK 0xFFFFFFFD
51 #define ROGUE_CR_TE_AA_X_EN 0x00000002
55 #define ROGUE_CR_TE_AA_X2_SHIFT (0U)
56 #define ROGUE_CR_TE_AA_X2_CLRMSK (0xFFFFFFFEU)
[all …]
/linux/net/netfilter/ipset/
H A Dpfxlen.c12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
[all …]
/linux/include/linux/platform_data/x86/
H A Dpmc_atom.h13 #define PCI_DEVICE_ID_VLV_PMC 0x0F1C
15 #define PCI_DEVICE_ID_CHT_PMC 0x229C
18 #define PMC_BASE_ADDR_OFFSET 0x44
19 #define PMC_BASE_ADDR_MASK 0xFFFFFE00
20 #define PMC_MMIO_REG_LEN 0x100
24 #define PMC_FUNC_DIS 0x34
25 #define PMC_FUNC_DIS_2 0x38
32 #define PMC_S0IX_WAKE_EN 0x3C
47 #define PMC_CLK_CTL_OFFSET 0x60
50 #define PMC_CLK_CTL_GATED_ON_D3 0x0
[all …]
/linux/Documentation/devicetree/bindings/rtc/
H A Datmel,at91rm9200-rtc.yaml52 reg = <0xfffffe00 0x100>;
/linux/arch/parisc/kernel/
H A Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
/linux/arch/powerpc/include/asm/nohash/32/
H A Dmmu-8xx.h16 #define MI_GPM 0x80000000 /* Set domain manager mode */
17 #define MI_PPM 0x40000000 /* Set subpage protection */
18 #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
19 #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
20 #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
21 #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
24 * Ks = 0, Kp = 1.
27 #define MI_Ks 0x80000000 /* Should not be set */
28 #define MI_Kp 0x40000000 /* Should always be set */
39 * 0 => Kernel => 11 (all accesses performed according as user iaw page definition)
[all …]
/linux/drivers/char/
H A Dds1620.c26 #define THERM_START_CONVERT 0xee
27 #define THERM_RESET 0xaf
28 #define THERM_READ_CONFIG 0xac
29 #define THERM_READ_TEMP 0xaa
30 #define THERM_READ_TL 0xa2
31 #define THERM_READ_TH 0xa1
32 #define THERM_WRITE_CONFIG 0x0c
33 #define THERM_WRITE_TL 0x02
34 #define THERM_WRITE_TH 0x01
53 nw_gpio_modify_op(GPIO_DSCLK, clk ? GPIO_DSCLK : 0); in netwinder_ds1620_set_clk()
[all …]
/linux/drivers/pci/controller/
H A Dpci-thunder-pem.c21 #define PEM_CFG_WR 0x28
22 #define PEM_CFG_RD 0x30
45 if (devfn != 0 || where >= 2048) in thunder_pem_bridge_read()
63 case 0x40: in thunder_pem_bridge_read()
64 read_val &= 0xffff00ff; in thunder_pem_bridge_read()
65 read_val |= 0x00007000; /* Skip MSI CAP */ in thunder_pem_bridge_read()
67 case 0x70: /* Express Cap */ in thunder_pem_bridge_read()
70 * reads as 0, else leave it alone. in thunder_pem_bridge_read()
72 if (!(read_val & (0x1f << 25))) in thunder_pem_bridge_read()
75 case 0xb0: /* MSI-X Cap */ in thunder_pem_bridge_read()
[all …]
/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
H A Dhw_atl2_llh_internal.h12 #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_ADR 0x000054C8
13 #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_MSK 0x00001000
14 #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_MSKN 0xFFFFEFFF
17 #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_DEFAULT 0x0
21 #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_ADR 0x000054C8
22 #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_MSK 0x000001FF
23 #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_MSKN 0xFFFFFE00
24 #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_SHIFT 0
33 #define HW_ATL2_RPF_NEW_EN_ADR 0x00005104
35 #define HW_ATL2_RPF_NEW_EN_MSK 0x00000800
[all …]
/linux/drivers/video/fbdev/
H A Dvt8500lcdfb.c51 info->var.red.offset = 0; in vt8500lcd_set_par()
53 info->var.red.msb_right = 0; in vt8500lcd_set_par()
55 info->var.green.offset = 0; in vt8500lcd_set_par()
57 info->var.green.msb_right = 0; in vt8500lcd_set_par()
59 info->var.blue.offset = 0; in vt8500lcd_set_par()
61 info->var.blue.msb_right = 0; in vt8500lcd_set_par()
63 info->var.transp.offset = 0; in vt8500lcd_set_par()
64 info->var.transp.length = 0; in vt8500lcd_set_par()
65 info->var.transp.msb_right = 0; in vt8500lcd_set_par()
72 info->var.transp.offset = 0; in vt8500lcd_set_par()
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_phy.c59 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
63 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
68 u16 bMode, fracMode, aModeRefSel = 0; in ar9002_hw_set_channel()
69 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; in ar9002_hw_set_channel()
77 reg32 &= 0xc0000000; in ar9002_hw_set_channel()
81 int regWrites = 0; in ar9002_hw_set_channel()
85 aModeRefSel = 0; in ar9002_hw_set_channel()
109 bMode = 0; in ar9002_hw_set_channel()
110 fracMode = 0; in ar9002_hw_set_channel()
113 case 0: in ar9002_hw_set_channel()
[all …]
/linux/drivers/gpu/drm/radeon/
H A Drs690d.h32 #define R_00001E_K8_FB_LOCATION 0x00001E
33 #define R_00005F_MC_MISC_UMA_CNTL 0x00005F
34 #define G_00005F_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF)
35 #define R_000078_MC_INDEX 0x000078
36 #define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0)
37 #define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF)
38 #define C_000078_MC_IND_ADDR 0xFFFFFE00
39 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9)
40 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1)
41 #define C_000078_MC_IND_WR_EN 0xFFFFFDFF
[all …]
H A Dr600d.h30 #define CP_PACKET2 0x80000000
31 #define PACKET2_PAD_SHIFT 0
32 #define PACKET2_PAD_MASK (0x3fffffff << 0)
41 #define R6XX_MAX_BACKENDS_MASK 0xff
43 #define R6XX_MAX_SIMDS_MASK 0xff
45 #define R6XX_MAX_PIPES_MASK 0xff
48 #define ARRAY_LINEAR_GENERAL 0x00000000
49 #define ARRAY_LINEAR_ALIGNED 0x00000001
50 #define ARRAY_1D_TILED_THIN1 0x00000002
51 #define ARRAY_2D_TILED_THIN1 0x00000004
[all …]
/linux/drivers/bluetooth/
H A Dhci_bcm4377.c26 BCM4377 = 0,
32 #define BCM4377_DEVICE_ID 0x5fa0
33 #define BCM4378_DEVICE_ID 0x5f69
34 #define BCM4387_DEVICE_ID 0x5f71
35 #define BCM4388_DEVICE_ID 0x5f72
43 * 0xffffffff but is always aligned down to the previous 0x200 byte boundary
44 * which effectively limits the window to [start, start+0xfffffe00].
45 * We just limit the DMA window to [0, 0xfffffe00] to make sure we don't
48 #define BCM4377_DMA_MASK 0xfffffe00
50 #define BCM4377_PCIECFG_BAR0_WINDOW1 0x80
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91rm9200.dtsi44 #size-cells = <0>;
46 cpu@0 {
49 reg = <0>;
55 reg = <0x20000000 0x04000000>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
74 reg = <0x00200000 0x4000>;
77 ranges = <0 0x00200000 0x4000>;
[all …]
H A Dat91sam9rl.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0>;
54 reg = <0x20000000 0x04000000>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #clock-cells = <0>;
67 clock-frequency = <0>;
72 #clock-cells = <0>;
79 reg = <0x00300000 0x10000>;
[all …]
H A Dat91sam9n12.dtsi42 #size-cells = <0>;
44 cpu@0 {
47 reg = <0>;
53 reg = <0x20000000 0x10000000>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
72 reg = <0x00300000 0x8000>;
75 ranges = <0 0x00300000 0x8000>;
[all …]
H A Dat91sam9x5.dtsi44 #size-cells = <0>;
46 cpu@0 {
49 reg = <0>;
55 reg = <0x20000000 0x10000000>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
73 #clock-cells = <0>;
80 reg = <0x00300000 0x8000>;
[all …]
H A Dsama5d3.dtsi46 #size-cells = <0>;
47 cpu@0 {
50 reg = <0x0>;
51 d-cache-size = <0x8000>; // L1, 32 KB
52 i-cache-size = <0x8000>; // L1, 32 KB
58 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
63 reg = <0x20000000 0x8000000>;
69 #clock-cells = <0>;
70 clock-frequency = <0>;
75 #clock-cells = <0>;
[all …]
H A Dsam9x60.dtsi37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0>;
48 reg = <0x20000000 0x10000000>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x00300000 0x100000>;
68 ranges = <0 0x00300000 0x100000>;
79 #size-cells = <0>;
81 reg = <0x00500000 0x100000
[all …]
/linux/drivers/media/pci/cx25821/
H A Dcx25821-core.c26 static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET };
330 pr_cont("0x%08x [ %s", in cx25821_risc_decode()
332 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) { in cx25821_risc_decode()
336 pr_cont(" count=%d ]\n", risc & 0xfff); in cx25821_risc_decode()
345 cx_write(DEV_CNTRL2, 0x20); in cx25821_registers_init()
350 cx_write(PCI_INT_MSK, 0x2001FFFF); in cx25821_registers_init()
357 cx_write(PLL_A_INT_FRAC, 0x9807A58B); in cx25821_registers_init()
359 /* PLL_A_POST = 0x1C, PLL_A_OUT_TO_PIN = 0x1 */ in cx25821_registers_init()
360 cx_write(PLL_A_POST_STAT_BIST, 0x8000019C); in cx25821_registers_init()
364 cx_write(PLL_A_INT_FRAC, tmp & 0x7FFFFFFF); in cx25821_registers_init()
[all …]
/linux/drivers/pinctrl/spear/
H A Dpinctrl-spear1340.c34 #define PAD_FUNCTION_EN_1 0x668
35 #define PAD_FUNCTION_EN_2 0x66C
36 #define PAD_FUNCTION_EN_3 0x670
37 #define PAD_FUNCTION_EN_4 0x674
38 #define PAD_FUNCTION_EN_5 0x690
39 #define PAD_FUNCTION_EN_6 0x694
40 #define PAD_FUNCTION_EN_7 0x698
41 #define PAD_FUNCTION_EN_8 0x69C
44 #define PAD_SHARED_IP_EN_1 0x6A0
45 #define PAD_SHARED_IP_EN_2 0x6A4
[all …]
/linux/arch/m68k/kernel/
H A Dhead.S308 TC_ENABLE = 0x8000
309 TC_PAGE8K = 0x4000
310 TC_PAGE4K = 0x0000
313 TTR_ENABLE = 0x8000 /* enable transparent translation */
314 TTR_ANYMODE = 0x4000 /* user and kernel mode access */
315 TTR_KERNELMODE = 0x2000 /* only kernel mode access */
316 TTR_USERMODE = 0x0000 /* only user mode access */
317 TTR_CI = 0x0400 /* inhibit cache */
318 TTR_RW = 0x0200 /* read/write mode */
319 TTR_RWM = 0x0100 /* read/write mask */
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
H A Dpcie.c34 } while (0)
86 BRCMF_FW_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602),
87 BRCMF_FW_ENTRY(BRCM_CC_43465_CHIP_ID, 0xFFFFFFF0, 4366C),
88 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C),
89 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350),
90 BRCMF_FW_ENTRY(BRCM_CC_43525_CHIP_ID, 0xFFFFFFF0, 4365C),
91 BRCMF_FW_ENTRY(BRCM_CC_4355_CHIP_ID, 0x000007FF, 4355),
92 BRCMF_FW_ENTRY(BRCM_CC_4355_CHIP_ID, 0x00002000, 54591),
93 BRCMF_FW_ENTRY(BRCM_CC_4355_CHIP_ID, 0xFFFFF800, 4355C1), /* rev ID 12/C2 seen */
94 BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
[all …]

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