Lines Matching +full:0 +full:xfffffe00
37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0>;
48 reg = <0x20000000 0x10000000>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x00300000 0x100000>;
68 ranges = <0 0x00300000 0x100000>;
79 #size-cells = <0>;
81 reg = <0x00500000 0x100000
82 0xf803c000 0x400>;
93 reg = <0x00600000 0x100000>;
102 reg = <0x00700000 0x100000>;
117 reg = <0x10000000 0x60000000>;
118 ranges = <0x0 0x0 0x10000000 0x10000000
119 0x1 0x0 0x20000000 0x10000000
120 0x2 0x0 0x30000000 0x10000000
121 0x3 0x0 0x40000000 0x10000000
122 0x4 0x0 0x50000000 0x10000000
123 0x5 0x0 0x60000000 0x10000000>;
139 reg = <0x80000000 0x300>;
140 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
150 reg = <0x90000000 0x300>;
151 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
167 reg = <0xf0000000 0x200>;
171 ranges = <0x0 0xf0000000 0x800>;
176 reg = <0x200 0x200>;
179 (AT91_XDMAC_DT_MEM_IF(0) |
183 (AT91_XDMAC_DT_MEM_IF(0) |
198 reg = <0x400 0x200>;
201 #size-cells = <0>;
205 (AT91_XDMAC_DT_MEM_IF(0) |
209 (AT91_XDMAC_DT_MEM_IF(0) |
219 reg = <0x600 0x200>;
222 #size-cells = <0>;
225 (AT91_XDMAC_DT_MEM_IF(0) |
229 (AT91_XDMAC_DT_MEM_IF(0) |
240 reg = <0xf0004000 0x200>;
244 ranges = <0x0 0xf0004000 0x800>;
249 reg = <0x200 0x200>;
253 (AT91_XDMAC_DT_MEM_IF(0) |
257 (AT91_XDMAC_DT_MEM_IF(0) |
271 reg = <0x400 0x200>;
274 #size-cells = <0>;
278 (AT91_XDMAC_DT_MEM_IF(0) |
282 (AT91_XDMAC_DT_MEM_IF(0) |
292 reg = <0x600 0x200>;
295 #size-cells = <0>;
298 (AT91_XDMAC_DT_MEM_IF(0) |
302 (AT91_XDMAC_DT_MEM_IF(0) |
313 reg = <0xf0008000 0x1000>;
314 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
322 reg = <0xf0010000 0x4000>;
325 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
328 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
338 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
342 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
345 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
352 #size-cells = <0>;
358 reg = <0xf001c000 0x100>;
361 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
364 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
374 reg = <0xf0020000 0x200>;
378 ranges = <0x0 0xf0020000 0x800>;
383 reg = <0x200 0x200>;
386 (AT91_XDMAC_DT_MEM_IF(0) |
390 (AT91_XDMAC_DT_MEM_IF(0) |
405 reg = <0x600 0x200>;
408 #size-cells = <0>;
411 (AT91_XDMAC_DT_MEM_IF(0) |
415 (AT91_XDMAC_DT_MEM_IF(0) |
426 reg = <0xf0024000 0x200>;
430 ranges = <0x0 0xf0024000 0x800>;
435 reg = <0x200 0x200>;
438 (AT91_XDMAC_DT_MEM_IF(0) |
442 (AT91_XDMAC_DT_MEM_IF(0) |
457 reg = <0x600 0x200>;
460 #size-cells = <0>;
463 (AT91_XDMAC_DT_MEM_IF(0) |
467 (AT91_XDMAC_DT_MEM_IF(0) |
478 reg = <0xf0028000 0x100>;
486 reg = <0xf002c000 0x100>;
487 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
489 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
498 reg = <0xf0030000 0x100>;
499 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
505 reg = <0xf0034000 0x100>;
506 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
508 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
511 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
520 reg = <0xf0038000 0x100>;
521 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
523 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
526 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
535 reg = <0xf003c000 0x100>;
538 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
548 reg = <0xf8000000 0x300>;
557 reg = <0xf8004000 0x300>;
567 #size-cells = <0>;
568 reg = <0xf8008000 0x100>;
569 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
570 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
577 #size-cells = <0>;
578 reg = <0xf800c000 0x100>;
579 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
580 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
586 reg = <0xf8010000 0x200>;
590 ranges = <0x0 0xf8010000 0x800>;
595 reg = <0x200 0x200>;
598 (AT91_XDMAC_DT_MEM_IF(0) |
602 (AT91_XDMAC_DT_MEM_IF(0) |
617 reg = <0x600 0x200>;
620 #size-cells = <0>;
623 (AT91_XDMAC_DT_MEM_IF(0) |
627 (AT91_XDMAC_DT_MEM_IF(0) |
638 reg = <0xf8014000 0x200>;
642 ranges = <0x0 0xf8014000 0x800>;
647 reg = <0x200 0x200>;
650 (AT91_XDMAC_DT_MEM_IF(0) |
654 (AT91_XDMAC_DT_MEM_IF(0) |
669 reg = <0x600 0x200>;
672 #size-cells = <0>;
675 (AT91_XDMAC_DT_MEM_IF(0) |
679 (AT91_XDMAC_DT_MEM_IF(0) |
690 reg = <0xf8018000 0x200>;
694 ranges = <0x0 0xf8018000 0x800>;
699 reg = <0x200 0x200>;
702 (AT91_XDMAC_DT_MEM_IF(0) |
706 (AT91_XDMAC_DT_MEM_IF(0) |
721 reg = <0x600 0x200>;
724 #size-cells = <0>;
727 (AT91_XDMAC_DT_MEM_IF(0) |
731 (AT91_XDMAC_DT_MEM_IF(0) |
742 reg = <0xf801c000 0x200>;
746 ranges = <0x0 0xf801c000 0x800>;
751 reg = <0x200 0x200>;
754 (AT91_XDMAC_DT_MEM_IF(0) |
756 AT91_XDMAC_DT_PERID(0))>,
758 (AT91_XDMAC_DT_MEM_IF(0) |
773 reg = <0x400 0x200>;
776 #size-cells = <0>;
780 (AT91_XDMAC_DT_MEM_IF(0) |
782 AT91_XDMAC_DT_PERID(0))>,
784 (AT91_XDMAC_DT_MEM_IF(0) |
794 reg = <0x600 0x200>;
797 #size-cells = <0>;
800 (AT91_XDMAC_DT_MEM_IF(0) |
802 AT91_XDMAC_DT_PERID(0))>,
804 (AT91_XDMAC_DT_MEM_IF(0) |
815 reg = <0xf8020000 0x200>;
819 ranges = <0x0 0xf8020000 0x800>;
824 reg = <0x200 0x200>;
827 (AT91_XDMAC_DT_MEM_IF(0) |
831 (AT91_XDMAC_DT_MEM_IF(0) |
846 reg = <0x400 0x200>;
849 #size-cells = <0>;
853 (AT91_XDMAC_DT_MEM_IF(0) |
857 (AT91_XDMAC_DT_MEM_IF(0) |
867 reg = <0x600 0x200>;
870 #size-cells = <0>;
873 (AT91_XDMAC_DT_MEM_IF(0) |
877 (AT91_XDMAC_DT_MEM_IF(0) |
888 reg = <0xf8024000 0x200>;
892 ranges = <0x0 0xf8024000 0x800>;
897 reg = <0x200 0x200>;
900 (AT91_XDMAC_DT_MEM_IF(0) |
904 (AT91_XDMAC_DT_MEM_IF(0) |
919 reg = <0x400 0x200>;
922 #size-cells = <0>;
926 (AT91_XDMAC_DT_MEM_IF(0) |
930 (AT91_XDMAC_DT_MEM_IF(0) |
940 reg = <0x600 0x200>;
943 #size-cells = <0>;
946 (AT91_XDMAC_DT_MEM_IF(0) |
950 (AT91_XDMAC_DT_MEM_IF(0) |
961 reg = <0xf8028000 0x200>;
965 ranges = <0x0 0xf8028000 0x800>;
970 reg = <0x200 0x200>;
973 (AT91_XDMAC_DT_MEM_IF(0) |
977 (AT91_XDMAC_DT_MEM_IF(0) |
992 reg = <0x400 0x200>;
995 #size-cells = <0>;
999 (AT91_XDMAC_DT_MEM_IF(0) |
1003 (AT91_XDMAC_DT_MEM_IF(0) |
1013 reg = <0x600 0x200>;
1016 #size-cells = <0>;
1019 (AT91_XDMAC_DT_MEM_IF(0) |
1023 (AT91_XDMAC_DT_MEM_IF(0) |
1034 reg = <0xf802c000 0x1000>;
1043 reg = <0xf8030000 0x1000>;
1052 reg = <0xf8034000 0x300>;
1061 reg = <0xf8038000 0x4000>;
1062 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
1072 #size-cells = <0>;
1074 port@0 {
1076 #size-cells = <0>;
1077 reg = <0>;
1089 reg = <0xf8040000 0x200>;
1093 ranges = <0x0 0xf8040000 0x800>;
1098 reg = <0x200 0x200>;
1101 (AT91_XDMAC_DT_MEM_IF(0) |
1105 (AT91_XDMAC_DT_MEM_IF(0) |
1120 reg = <0x600 0x200>;
1123 #size-cells = <0>;
1126 (AT91_XDMAC_DT_MEM_IF(0) |
1130 (AT91_XDMAC_DT_MEM_IF(0) |
1141 reg = <0xf8044000 0x200>;
1145 ranges = <0x0 0xf8044000 0x800>;
1150 reg = <0x200 0x200>;
1153 (AT91_XDMAC_DT_MEM_IF(0) |
1157 (AT91_XDMAC_DT_MEM_IF(0) |
1172 reg = <0x600 0x200>;
1175 #size-cells = <0>;
1178 (AT91_XDMAC_DT_MEM_IF(0) |
1182 (AT91_XDMAC_DT_MEM_IF(0) |
1193 reg = <0xf8048000 0x100>;
1200 #size-cells = <0>;
1206 reg = <0xf804c000 0x100>;
1210 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
1222 reg = <0xf8050000 0x100>;
1227 reg = <0xffffde00 0x200>;
1232 reg = <0xffffe000 0x300>,
1233 <0xffffe600 0x100>;
1238 reg = <0xffffe800 0x200>;
1245 reg = <0xffffea00 0x100>;
1252 reg = <0xfffff100 0x100>;
1258 reg = <0xfffff200 0x200>;
1262 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1265 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1277 ranges = <0xfffff400 0xfffff400 0x800>;
1282 0xffffffff 0xffe03fff 0xef00019d /* pioA */
1283 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */
1284 0xffffffff 0xffffffff 0xf83fffff /* pioC */
1285 0x003fffff 0x003f8000 0x00000000 /* pioD */
1290 reg = <0xfffff400 0x200>;
1301 reg = <0xfffff600 0x200>;
1313 reg = <0xfffff800 0x200>;
1324 reg = <0xfffffa00 0x200>;
1337 reg = <0xfffffc00 0x200>;
1340 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
1346 reg = <0xfffffe00 0x10>;
1347 clocks = <&clk32k 0>;
1352 reg = <0xfffffe10 0x10>;
1353 clocks = <&clk32k 0>;
1355 #size-cells = <0>;
1363 reg = <0xfffffe20 0x20>;
1370 reg = <0xfffffe40 0x10>;
1377 reg = <0xfffffe50 0x4>;
1384 reg = <0xfffffe60 0x10>;
1389 reg = <0xfffffea8 0x100>;
1396 reg = <0xffffff80 0x24>;
1398 clocks = <&clk32k 0>;