Searched +full:0 +full:xfffffd00 (Results 1 – 10 of 10) sorted by relevance
32 reg = <0xfffffd00 0x10>;
66 reg = <0xfffffd00 0x10>;
38 #size-cells = <0>;40 cpu@0 {43 reg = <0>;49 reg = <0x20000000 0x08000000>;55 #clock-cells = <0>;56 clock-frequency = <0>;61 #clock-cells = <0>;62 clock-frequency = <0>;68 reg = <0x00300000 0x28000>;71 ranges = <0 0x00300000 0x28000>;[all …]
44 #size-cells = <0>;46 cpu@0 {49 reg = <0>;55 reg = <0x20000000 0x04000000>;61 #clock-cells = <0>;62 clock-frequency = <0>;67 #clock-cells = <0>;68 clock-frequency = <0>;74 reg = <0x00200000 0x4000>;77 ranges = <0 0x00200000 0x4000>;[all …]
43 #size-cells = <0>;45 cpu@0 {48 reg = <0>;54 reg = <0x20000000 0x04000000>;60 #clock-cells = <0>;61 clock-frequency = <0>;66 #clock-cells = <0>;67 clock-frequency = <0>;72 #clock-cells = <0>;79 reg = <0x00300000 0x10000>;[all …]
41 #size-cells = <0>;43 cpu@0 {46 reg = <0>;52 reg = <0x20000000 0x04000000>;58 #clock-cells = <0>;59 clock-frequency = <0>;64 #clock-cells = <0>;65 clock-frequency = <0>;70 #clock-cells = <0>;77 reg = <0x002ff000 0x2000>;[all …]
40 #size-cells = <0>;42 cpu@0 {45 reg = <0>;51 reg = <0x20000000 0x08000000>;57 #clock-cells = <0>;58 clock-frequency = <0>;63 #clock-cells = <0>;64 clock-frequency = <0>;70 reg = <0x00300000 0x14000>;73 ranges = <0 0x00300000 0x14000>;[all …]
46 #size-cells = <0>;48 cpu@0 {51 reg = <0>;57 reg = <0x70000000 0x10000000>;63 #clock-cells = <0>;64 clock-frequency = <0>;69 #clock-cells = <0>;70 clock-frequency = <0>;75 #clock-cells = <0>;82 reg = <0x00300000 0x10000>;[all …]
27 * 0xFFFFF0xx -- System Control34 #define SCR_ADDR 0xfffff00037 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */38 #define SCR_DMAP 0x04 /* Double Map */39 #define SCR_SO 0x08 /* Supervisor Only */40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */41 #define SCR_PRV 0x20 /* Privilege Violation */42 #define SCR_WPV 0x40 /* Write Protect Violation */43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */48 #define MRR_ADDR 0xfffff004[all …]
29 * 0xFFFFF0xx -- System Control36 #define SCR_ADDR 0xfffff00039 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */40 #define SCR_DMAP 0x04 /* Double Map */41 #define SCR_SO 0x08 /* Supervisor Only */42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */43 #define SCR_PRV 0x20 /* Privilege Violation */44 #define SCR_WPV 0x40 /* Write Protect Violation */45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */50 #define MRR_ADDR 0xfffff004[all …]