Lines Matching +full:0 +full:xfffffd00
27 * 0xFFFFF0xx -- System Control
34 #define SCR_ADDR 0xfffff000
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
38 #define SCR_DMAP 0x04 /* Double Map */
39 #define SCR_SO 0x08 /* Supervisor Only */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
41 #define SCR_PRV 0x20 /* Privilege Violation */
42 #define SCR_WPV 0x40 /* Write Protect Violation */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
48 #define MRR_ADDR 0xfffff004
53 * 0xFFFFF1xx -- Chip-Select logic
60 #define CSGBA_ADDR 0xfffff100
61 #define CSGBB_ADDR 0xfffff102
63 #define CSGBC_ADDR 0xfffff104
64 #define CSGBD_ADDR 0xfffff106
74 #define CSA_ADDR 0xfffff110
75 #define CSB_ADDR 0xfffff112
76 #define CSC_ADDR 0xfffff114
77 #define CSD_ADDR 0xfffff116
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
85 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
87 #define CSA_WS_MASK 0x0070 /* Wait State */
89 #define CSA_BSW 0x0080 /* Data Bus Width */
90 #define CSA_FLASH 0x0100 /* FLASH Memory Support */
91 #define CSA_RO 0x8000 /* Read-Only */
93 #define CSB_EN 0x0001 /* Chip-Select Enable */
94 #define CSB_SIZ_MASK 0x000e /* Chip-Select Size */
96 #define CSB_WS_MASK 0x0070 /* Wait State */
98 #define CSB_BSW 0x0080 /* Data Bus Width */
99 #define CSB_FLASH 0x0100 /* FLASH Memory Support */
100 #define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
102 #define CSB_ROP 0x2000 /* Readonly if protected */
103 #define CSB_SOP 0x4000 /* Supervisor only if protected */
104 #define CSB_RO 0x8000 /* Read-Only */
106 #define CSC_EN 0x0001 /* Chip-Select Enable */
107 #define CSC_SIZ_MASK 0x000e /* Chip-Select Size */
109 #define CSC_WS_MASK 0x0070 /* Wait State */
111 #define CSC_BSW 0x0080 /* Data Bus Width */
112 #define CSC_FLASH 0x0100 /* FLASH Memory Support */
113 #define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
115 #define CSC_ROP 0x2000 /* Readonly if protected */
116 #define CSC_SOP 0x4000 /* Supervisor only if protected */
117 #define CSC_RO 0x8000 /* Read-Only */
119 #define CSD_EN 0x0001 /* Chip-Select Enable */
120 #define CSD_SIZ_MASK 0x000e /* Chip-Select Size */
122 #define CSD_WS_MASK 0x0070 /* Wait State */
124 #define CSD_BSW 0x0080 /* Data Bus Width */
125 #define CSD_FLASH 0x0100 /* FLASH Memory Support */
126 #define CSD_DRAM 0x0200 /* Dram Selection */
127 #define CSD_COMB 0x0400 /* Combining */
128 #define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
130 #define CSD_ROP 0x2000 /* Readonly if protected */
131 #define CSD_SOP 0x4000 /* Supervisor only if protected */
132 #define CSD_RO 0x8000 /* Read-Only */
137 #define EMUCS_ADDR 0xfffff118
140 #define EMUCS_WS_MASK 0x0070
145 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
152 #define PLLCR_ADDR 0xfffff200
155 #define PLLCR_DISPLL 0x0008 /* Disable PLL */
156 #define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
157 #define PLLCR_PRESC 0x0020 /* VCO prescaler */
158 #define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
160 #define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
170 #define PLLFSR_ADDR 0xfffff202
173 #define PLLFSR_PC_MASK 0x00ff /* P Count */
174 #define PLLFSR_PC_SHIFT 0
175 #define PLLFSR_QC_MASK 0x0f00 /* Q Count */
177 #define PLLFSR_PROT 0x4000 /* Protect P & Q */
178 #define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
183 #define PCTRL_ADDR 0xfffff207
186 #define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
187 #define PCTRL_WIDTH_SHIFT 0
188 #define PCTRL_PCEN 0x80 /* Power Control Enable */
192 * 0xFFFFF3xx -- Interrupt Controller
199 #define IVR_ADDR 0xfffff300
202 #define IVR_VECTOR_MASK 0xF8
207 #define ICR_ADDR 0xfffff302
210 #define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */
211 #define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */
212 #define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */
213 #define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */
214 #define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */
215 #define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */
216 #define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */
217 #define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */
218 #define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */
223 #define IMR_ADDR 0xfffff304
230 #define SPI_IRQ_NUM 0 /* SPI interrupt */
282 #define ISR_ADDR 0xfffff30c
311 #define IPR_ADDR 0xfffff30c
339 * 0xFFFFF4xx -- Parallel Ports
346 #define PADIR_ADDR 0xfffff400 /* Port A direction reg */
347 #define PADATA_ADDR 0xfffff401 /* Port A data register */
348 #define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */
359 #define PBDIR_ADDR 0xfffff408 /* Port B direction reg */
360 #define PBDATA_ADDR 0xfffff409 /* Port B data register */
361 #define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */
362 #define PBSEL_ADDR 0xfffff40b /* Port B Select Register */
371 #define PB_CSB0 0x01 /* Use CSB0 as PB[0] */
372 #define PB_CSB1 0x02 /* Use CSB1 as PB[1] */
373 #define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */
374 #define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */
375 #define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */
376 #define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */
377 #define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */
378 #define PB_PWMO 0x80 /* Use PWMO as PB[7] */
383 #define PCDIR_ADDR 0xfffff410 /* Port C direction reg */
384 #define PCDATA_ADDR 0xfffff411 /* Port C data register */
385 #define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */
386 #define PCSEL_ADDR 0xfffff413 /* Port C Select Register */
395 #define PC_LD0 0x01 /* Use LD0 as PC[0] */
396 #define PC_LD1 0x02 /* Use LD1 as PC[1] */
397 #define PC_LD2 0x04 /* Use LD2 as PC[2] */
398 #define PC_LD3 0x08 /* Use LD3 as PC[3] */
399 #define PC_LFLM 0x10 /* Use LFLM as PC[4] */
400 #define PC_LLP 0x20 /* Use LLP as PC[5] */
401 #define PC_LCLK 0x40 /* Use LCLK as PC[6] */
402 #define PC_LACD 0x80 /* Use LACD as PC[7] */
407 #define PDDIR_ADDR 0xfffff418 /* Port D direction reg */
408 #define PDDATA_ADDR 0xfffff419 /* Port D data register */
409 #define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
410 #define PDSEL_ADDR 0xfffff41b /* Port D Select Register */
411 #define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */
412 #define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
413 #define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */
414 #define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */
427 #define PD_INT0 0x01 /* Use INT0 as PD[0] */
428 #define PD_INT1 0x02 /* Use INT1 as PD[1] */
429 #define PD_INT2 0x04 /* Use INT2 as PD[2] */
430 #define PD_INT3 0x08 /* Use INT3 as PD[3] */
431 #define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */
432 #define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */
433 #define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */
434 #define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */
439 #define PEDIR_ADDR 0xfffff420 /* Port E direction reg */
440 #define PEDATA_ADDR 0xfffff421 /* Port E data register */
441 #define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
442 #define PESEL_ADDR 0xfffff423 /* Port E Select Register */
451 #define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */
452 #define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */
453 #define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */
454 #define PE_DWE 0x08 /* Use DWE as PE[3] */
455 #define PE_RXD 0x10 /* Use RXD as PE[4] */
456 #define PE_TXD 0x20 /* Use TXD as PE[5] */
457 #define PE_RTS 0x40 /* Use RTS as PE[6] */
458 #define PE_CTS 0x80 /* Use CTS as PE[7] */
463 #define PFDIR_ADDR 0xfffff428 /* Port F direction reg */
464 #define PFDATA_ADDR 0xfffff429 /* Port F data register */
465 #define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
466 #define PFSEL_ADDR 0xfffff42b /* Port F Select Register */
475 #define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */
476 #define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */
477 #define PF_CLKO 0x04 /* Use CLKO as PF[2] */
478 #define PF_A20 0x08 /* Use A20 as PF[3] */
479 #define PF_A21 0x10 /* Use A21 as PF[4] */
480 #define PF_A22 0x20 /* Use A22 as PF[5] */
481 #define PF_A23 0x40 /* Use A23 as PF[6] */
482 #define PF_CSA1 0x80 /* Use CSA1 as PF[7] */
487 #define PGDIR_ADDR 0xfffff430 /* Port G direction reg */
488 #define PGDATA_ADDR 0xfffff431 /* Port G data register */
489 #define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
490 #define PGSEL_ADDR 0xfffff433 /* Port G Select Register */
499 #define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */
500 #define PG_A0 0x02 /* Use A0 as PG[1] */
501 #define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */
502 #define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */
503 #define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */
504 #define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */
508 * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
515 #define PWMC_ADDR 0xfffff500
518 #define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */
519 #define PWMC_CLKSEL_SHIFT 0
520 #define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */
522 #define PWMC_EN 0x0010 /* Enable PWM */
523 #define PMNC_FIFOAV 0x0020 /* FIFO Available */
524 #define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */
525 #define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */
526 #define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */
528 #define PWMC_CLKSRC 0x8000 /* Clock Source Select */
536 #define PWMS_ADDR 0xfffff502
542 #define PWMP_ADDR 0xfffff504
548 #define PWMCNT_ADDR 0xfffff505
553 * 0xFFFFF6xx -- General-Purpose Timer
560 #define TCTL_ADDR 0xfffff600
563 #define TCTL_TEN 0x0001 /* Timer Enable */
564 #define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
565 #define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */
566 #define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */
567 #define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */
568 #define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */
569 #define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */
570 #define TCTL_IRQEN 0x0010 /* IRQ Enable */
571 #define TCTL_OM 0x0020 /* Output Mode */
572 #define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */
573 #define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */
574 #define TCTL_CAP_FE 0x0080 /* Capture on falling edge */
575 #define TCTL_FRR 0x0010 /* Free-Run Mode */
584 #define TPRER_ADDR 0xfffff602
594 #define TCMP_ADDR 0xfffff604
604 #define TCR_ADDR 0xfffff606
614 #define TCN_ADDR 0xfffff608
624 #define TSTAT_ADDR 0xfffff60a
627 #define TSTAT_COMP 0x0001 /* Compare Event occurred */
628 #define TSTAT_CAPT 0x0001 /* Capture Event occurred */
636 * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
643 #define SPIMDATA_ADDR 0xfffff800
649 #define SPIMCONT_ADDR 0xfffff802
652 #define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */
653 #define SPIMCONT_BIT_COUNT_SHIFT 0
654 #define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */
655 #define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
656 #define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */
657 #define SPIMCONT_IRQ 0x0080 /* Interrupt Request */
658 #define SPIMCONT_XCH 0x0100 /* Exchange */
659 #define SPIMCONT_ENABLE 0x0200 /* Enable SPIM */
660 #define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */
669 * 0xFFFFF9xx -- UART
676 #define USTCNT_ADDR 0xfffff900
679 #define USTCNT_TXAE 0x0001 /* Transmitter Available Interrupt Enable */
680 #define USTCNT_TXHE 0x0002 /* Transmitter Half Empty Enable */
681 #define USTCNT_TXEE 0x0004 /* Transmitter Empty Interrupt Enable */
682 #define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */
683 #define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */
684 #define USTCNT_RXFE 0x0020 /* Receiver Full Interrupt Enable */
685 #define USTCNT_CTSD 0x0040 /* CTS Delta Interrupt Enable */
686 #define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */
687 #define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
688 #define USTCNT_STOP 0x0200 /* Stop bit transmission */
689 #define USTCNT_ODD 0x0400 /* Odd Parity */
690 #define USTCNT_PEN 0x0800 /* Parity Enable */
691 #define USTCNT_CLKM 0x1000 /* Clock Mode Select */
692 #define USTCNT_TXEN 0x2000 /* Transmitter Enable */
693 #define USTCNT_RXEN 0x4000 /* Receiver Enable */
694 #define USTCNT_UEN 0x8000 /* UART Enable */
712 #define UBAUD_ADDR 0xfffff902
715 #define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
716 #define UBAUD_PRESCALER_SHIFT 0
717 #define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divisor */
719 #define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
720 #define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */
725 #define URX_ADDR 0xfffff904
728 #define URX_RXDATA_ADDR 0xfffff905
731 #define URX_RXDATA_MASK 0x00ff /* Received data */
732 #define URX_RXDATA_SHIFT 0
733 #define URX_PARITY_ERROR 0x0100 /* Parity Error */
734 #define URX_BREAK 0x0200 /* Break Detected */
735 #define URX_FRAME_ERROR 0x0400 /* Framing Error */
736 #define URX_OVRUN 0x0800 /* Serial Overrun */
737 #define URX_OLD_DATA 0x1000 /* Old data in FIFO */
738 #define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */
739 #define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
740 #define URX_FIFO_FULL 0x8000 /* FIFO is Full */
745 #define UTX_ADDR 0xfffff906
748 #define UTX_TXDATA_ADDR 0xfffff907
751 #define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */
752 #define UTX_TXDATA_SHIFT 0
753 #define UTX_CTS_DELTA 0x0100 /* CTS changed */
754 #define UTX_CTS_STAT 0x0200 /* CTS State */
755 #define UTX_BUSY 0x0400 /* FIFO is busy, sending a character */
756 #define UTX_NOCTS 0x0800 /* Ignore CTS */
757 #define UTX_SEND_BREAK 0x1000 /* Send a BREAK */
758 #define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */
759 #define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */
760 #define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */
769 #define UMISC_ADDR 0xfffff908
772 #define UMISC_TX_POL 0x0004 /* Transmit Polarity */
773 #define UMISC_RX_POL 0x0008 /* Receive Polarity */
774 #define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
775 #define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
776 #define UMISC_RTS 0x0040 /* Set RTS status */
777 #define UMISC_RTSCONT 0x0080 /* Choose RTS control */
778 #define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */
779 #define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */
780 #define UMISC_LOOP 0x1000 /* Serial Loopback Enable */
781 #define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
782 #define UMISC_CLKSRC 0x4000 /* Clock Source */
783 #define UMISC_BAUD_TEST 0x8000 /* Enable Baud Test Mode */
788 #define NIPR_ADDR 0xfffff90a
791 #define NIPR_STEP_VALUE_MASK 0x00ff /* NI prescaler step value */
792 #define NIPR_STEP_VALUE_SHIFT 0
793 #define NIPR_SELECT_MASK 0x0700 /* Tap Selection */
795 #define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */
825 * 0xFFFFFAxx -- LCD Controller
832 #define LSSA_ADDR 0xfffffa00
835 #define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */
840 #define LVPW_ADDR 0xfffffa05
846 #define LXMAX_ADDR 0xfffffa08
849 #define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */
854 #define LYMAX_ADDR 0xfffffa0a
857 #define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */
862 #define LCXP_ADDR 0xfffffa18
865 #define LCXP_CC_MASK 0xc000 /* Cursor Control */
866 #define LCXP_CC_TRAMSPARENT 0x0000
867 #define LCXP_CC_BLACK 0x4000
868 #define LCXP_CC_REVERSED 0x8000
869 #define LCXP_CC_WHITE 0xc000
870 #define LCXP_CXP_MASK 0x02ff /* Cursor X position */
875 #define LCYP_ADDR 0xfffffa1a
878 #define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */
883 #define LCWCH_ADDR 0xfffffa1c
886 #define LCWCH_CH_MASK 0x001f /* Cursor Height */
887 #define LCWCH_CH_SHIFT 0
888 #define LCWCH_CW_MASK 0x1f00 /* Cursor Width */
894 #define LBLKC_ADDR 0xfffffa1f
897 #define LBLKC_BD_MASK 0x7f /* Blink Divisor */
898 #define LBLKC_BD_SHIFT 0
899 #define LBLKC_BKEN 0x80 /* Blink Enabled */
904 #define LPICF_ADDR 0xfffffa20
907 #define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */
908 #define LPICF_GS_BW 0x00
909 #define LPICF_GS_GRAY_4 0x01
910 #define LPICF_GS_GRAY_16 0x02
911 #define LPICF_PBSIZ_MASK 0x0c /* Panel Bus Width */
912 #define LPICF_PBSIZ_1 0x00
913 #define LPICF_PBSIZ_2 0x04
914 #define LPICF_PBSIZ_4 0x08
919 #define LPOLCF_ADDR 0xfffffa21
922 #define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */
923 #define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */
924 #define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */
925 #define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */
930 #define LACDRC_ADDR 0xfffffa23
933 #define LACDRC_ACDSLT 0x80 /* Signal Source Select */
934 #define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */
935 #define LACDRC_ACD_SHIFT 0
940 #define LPXCD_ADDR 0xfffffa25
943 #define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
944 #define LPXCD_PCD_SHIFT 0
949 #define LCKCON_ADDR 0xfffffa27
952 #define LCKCON_DWS_MASK 0x0f /* Display Wait-State */
953 #define LCKCON_DWS_SHIFT 0
954 #define LCKCON_DWIDTH 0x40 /* Display Memory Width */
955 #define LCKCON_LCDON 0x80 /* Enable LCD Controller */
964 #define LRRA_ADDR 0xfffffa29
970 #define LPOSR_ADDR 0xfffffa2d
973 #define LPOSR_POS_MASK 0x0f /* Pixel Offset Code */
974 #define LPOSR_POS_SHIFT 0
979 #define LFRCM_ADDR 0xfffffa31
982 #define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */
983 #define LFRCM_YMOD_SHIFT 0
984 #define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */
990 #define LGPMR_ADDR 0xfffffa33
993 #define LGPMR_G1_MASK 0x0f
994 #define LGPMR_G1_SHIFT 0
995 #define LGPMR_G2_MASK 0xf0
1001 #define PWMR_ADDR 0xfffffa36
1004 #define PWMR_PW_MASK 0x00ff /* Pulse Width */
1005 #define PWMR_PW_SHIFT 0
1006 #define PWMR_CCPEN 0x0100 /* Contrast Control Enable */
1007 #define PWMR_SRC_MASK 0x0600 /* Input Clock Source */
1008 #define PWMR_SRC_LINE 0x0000 /* Line Pulse */
1009 #define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */
1010 #define PWMR_SRC_LCD 0x4000 /* LCD clock */
1014 * 0xFFFFFBxx -- Real-Time Clock (RTC)
1021 #define RTCTIME_ADDR 0xfffffb00
1024 #define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */
1025 #define RTCTIME_SECONDS_SHIFT 0
1026 #define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */
1028 #define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */
1034 #define RTCALRM_ADDR 0xfffffb04
1037 #define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */
1038 #define RTCALRM_SECONDS_SHIFT 0
1039 #define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */
1041 #define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */
1047 #define WATCHDOG_ADDR 0xfffffb0a
1050 #define WATCHDOG_EN 0x0001 /* Watchdog Enabled */
1051 #define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */
1052 #define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occurred */
1053 #define WATCHDOG_CNT_MASK 0x0300 /* Watchdog Counter */
1059 #define RTCCTL_ADDR 0xfffffb0c
1062 #define RTCCTL_XTL 0x0020 /* Crystal Selection */
1063 #define RTCCTL_EN 0x0080 /* RTC Enable */
1072 #define RTCISR_ADDR 0xfffffb0e
1075 #define RTCISR_SW 0x0001 /* Stopwatch timed out */
1076 #define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
1077 #define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */
1078 #define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
1079 #define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */
1080 #define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */
1081 #define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */
1082 #define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */
1083 #define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */
1084 #define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */
1085 #define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */
1086 #define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */
1087 #define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */
1088 #define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */
1093 #define RTCIENR_ADDR 0xfffffb10
1096 #define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
1097 #define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
1098 #define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
1099 #define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
1100 #define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
1101 #define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */
1102 #define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */
1103 #define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */
1104 #define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */
1105 #define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */
1106 #define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */
1107 #define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */
1108 #define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */
1109 #define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */
1114 #define STPWCH_ADDR 0xfffffb12
1117 #define STPWCH_CNT_MASK 0x003f /* Stopwatch countdown value */
1118 #define SPTWCH_CNT_SHIFT 0
1123 #define DAYR_ADDR 0xfffffb1a
1126 #define DAYR_DAYS_MASK 0x1ff /* Day Setting */
1127 #define DAYR_DAYS_SHIFT 0
1132 #define DAYALARM_ADDR 0xfffffb1c
1135 #define DAYALARM_DAYSAL_MASK 0x01ff /* Day Setting of the Alarm */
1136 #define DAYALARM_DAYSAL_SHIFT 0
1140 * 0xFFFFFCxx -- DRAM Controller
1147 #define DRAMMC_ADDR 0xfffffc00
1150 #define DRAMMC_ROW12_MASK 0xc000 /* Row address bit for MD12 */
1151 #define DRAMMC_ROW12_PA10 0x0000
1152 #define DRAMMC_ROW12_PA21 0x4000
1153 #define DRAMMC_ROW12_PA23 0x8000
1154 #define DRAMMC_ROW0_MASK 0x3000 /* Row address bit for MD0 */
1155 #define DRAMMC_ROW0_PA11 0x0000
1156 #define DRAMMC_ROW0_PA22 0x1000
1157 #define DRAMMC_ROW0_PA23 0x2000
1158 #define DRAMMC_ROW11 0x0800 /* Row address bit for MD11 PA20/PA22 */
1159 #define DRAMMC_ROW10 0x0400 /* Row address bit for MD10 PA19/PA21 */
1160 #define DRAMMC_ROW9 0x0200 /* Row address bit for MD9 PA9/PA19 */
1161 #define DRAMMC_ROW8 0x0100 /* Row address bit for MD8 PA10/PA20 */
1162 #define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */
1163 #define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */
1164 #define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */
1165 #define DRAMMC_REF_MASK 0x001f /* Refresh Cycle */
1166 #define DRAMMC_REF_SHIFT 0
1171 #define DRAMC_ADDR 0xfffffc02
1174 #define DRAMC_DWE 0x0001 /* DRAM Write Enable */
1175 #define DRAMC_RST 0x0002 /* Reset Burst Refresh Enable */
1176 #define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */
1177 #define DRAMC_SLW 0x0008 /* Slow RAM */
1178 #define DRAMC_LSP 0x0010 /* Light Sleep */
1179 #define DRAMC_MSW 0x0020 /* Slow Multiplexing */
1180 #define DRAMC_WS_MASK 0x00c0 /* Wait-states */
1182 #define DRAMC_PGSZ_MASK 0x0300 /* Page Size for fast page mode */
1184 #define DRAMC_PGSZ_256K 0x0000
1185 #define DRAMC_PGSZ_512K 0x0100
1186 #define DRAMC_PGSZ_1024K 0x0200
1187 #define DRAMC_PGSZ_2048K 0x0300
1188 #define DRAMC_EDO 0x0400 /* EDO DRAM */
1189 #define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */
1190 #define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */
1192 #define DRAMC_RM 0x4000 /* Refresh Mode */
1193 #define DRAMC_EN 0x8000 /* DRAM Controller enable */
1198 * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
1205 #define ICEMACR_ADDR 0xfffffd00
1211 #define ICEMAMR_ADDR 0xfffffd04
1217 #define ICEMCCR_ADDR 0xfffffd08
1220 #define ICEMCCR_PD 0x0001 /* Program/Data Cycle Selection */
1221 #define ICEMCCR_RW 0x0002 /* Read/Write Cycle Selection */
1226 #define ICEMCMR_ADDR 0xfffffd0a
1229 #define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */
1230 #define ICEMCMR_RWM 0x0002 /* Read/Write Cycle Mask */
1235 #define ICEMCR_ADDR 0xfffffd0c
1238 #define ICEMCR_CEN 0x0001 /* Compare Enable */
1239 #define ICEMCR_PBEN 0x0002 /* Program Break Enable */
1240 #define ICEMCR_SB 0x0004 /* Single Breakpoint */
1241 #define ICEMCR_HMDIS 0x0008 /* HardMap disable */
1242 #define ICEMCR_BBIEN 0x0010 /* Bus Break Interrupt Enable */
1247 #define ICEMSR_ADDR 0xfffffd0e
1250 #define ICEMSR_EMUEN 0x0001 /* Emulation Enable */
1251 #define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */
1252 #define ICEMSR_BBIRQ 0x0004 /* Bus Break Interrupt Detected */
1253 #define ICEMSR_EMIRQ 0x0008 /* EMUIRQ Falling Edge Detected */