Lines Matching +full:0 +full:xfffffd00
46 #size-cells = <0>;
48 cpu@0 {
51 reg = <0>;
57 reg = <0x70000000 0x10000000>;
63 #clock-cells = <0>;
64 clock-frequency = <0>;
69 #clock-cells = <0>;
70 clock-frequency = <0>;
75 #clock-cells = <0>;
82 reg = <0x00300000 0x10000>;
85 ranges = <0 0x00300000 0x10000>;
104 reg = <0xfffff000 0x200>;
110 reg = <0xffffe400 0x200>;
117 reg = <0xffffe600 0x200>;
124 reg = <0xffffe800 0x200>;
129 reg = <0xffffea00 0x200>;
134 reg = <0xfffffc00 0x100>;
143 reg = <0xfffffd00 0x10>;
149 reg = <0xfffffd30 0xf>;
157 reg = <0xfffffd10 0x10>;
164 #size-cells = <0>;
165 reg = <0xfff7c000 0x100>;
166 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
174 #size-cells = <0>;
175 reg = <0xfffd4000 0x100>;
176 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
183 reg = <0xffffec00 0x200>;
184 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
194 ranges = <0xfffff200 0xfffff200 0xa00>;
198 0xffffffff 0xffc003ff /* pioA */
199 0xffffffff 0x800f8f00 /* pioB */
200 0xffffffff 0x00000e00 /* pioC */
201 0xffffffff 0xff0c1381 /* pioD */
202 0xffffffff 0x81ffff81 /* pioE */
207 pinctrl_ac97: ac97-0 {
247 pinctrl_dbgu: dbgu-0 {
255 pinctrl_i2c0: i2c0-0 {
263 pinctrl_i2c1: i2c1-0 {
271 pinctrl_isi_data_0_7: isi-0-data-0-7 {
286 pinctrl_isi_data_8_9: isi-0-data-8-9 {
292 pinctrl_isi_data_10_11: isi-0-data-10-11 {
300 pinctrl_usart0: usart0-0 {
306 pinctrl_usart0_rts: usart0_rts-0 {
311 pinctrl_usart0_cts: usart0_cts-0 {
318 pinctrl_usart1: usart1-0 {
324 pinctrl_usart1_rts: usart1_rts-0 {
329 pinctrl_usart1_cts: usart1_cts-0 {
336 pinctrl_usart2: usart2-0 {
342 pinctrl_usart2_rts: usart2_rts-0 {
347 pinctrl_usart2_cts: usart2_cts-0 {
354 pinctrl_usart3: usart3-0 {
360 pinctrl_usart3_rts: usart3_rts-0 {
365 pinctrl_usart3_cts: usart3_cts-0 {
372 pinctrl_nand_rb: nand-rb-0 {
377 pinctrl_nand_cs: nand-cs-0 {
384 pinctrl_macb_rmii: macb_rmii-0 {
398 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
412 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
414 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */
419 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
426 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
436 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
443 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
450 pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
460 pinctrl_ssc0_tx: ssc0_tx-0 {
462 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
467 pinctrl_ssc0_rx: ssc0_rx-0 {
476 pinctrl_ssc1_tx: ssc1_tx-0 {
483 pinctrl_ssc1_rx: ssc1_rx-0 {
492 pinctrl_spi0: spi0-0 {
494 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */
501 pinctrl_spi1: spi1-0 {
510 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
514 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
518 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
522 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
526 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
530 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
534 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
538 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
542 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
548 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
549 atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
552 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
556 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
560 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
564 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
568 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
572 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
576 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
580 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
586 pinctrl_fb: fb-0 {
588 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */
623 reg = <0xfffff200 0x200>;
634 reg = <0xfffff400 0x200>;
645 reg = <0xfffff600 0x200>;
656 reg = <0xfffff800 0x200>;
667 reg = <0xfffffa00 0x200>;
680 reg = <0xffffee00 0x200>;
683 pinctrl-0 = <&pinctrl_dbgu>;
691 reg = <0xfff8c000 0x200>;
697 pinctrl-0 = <&pinctrl_usart0>;
705 reg = <0xfff90000 0x200>;
711 pinctrl-0 = <&pinctrl_usart1>;
719 reg = <0xfff94000 0x200>;
725 pinctrl-0 = <&pinctrl_usart2>;
733 reg = <0xfff98000 0x200>;
739 pinctrl-0 = <&pinctrl_usart3>;
747 reg = <0xfffbc000 0x100>;
750 pinctrl-0 = <&pinctrl_macb_rmii>;
758 reg = <0xfffcc000 0x100>;
759 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
765 reg = <0xfff84000 0x100>;
768 pinctrl-0 = <&pinctrl_i2c0>;
770 #size-cells = <0>;
777 reg = <0xfff88000 0x100>;
780 pinctrl-0 = <&pinctrl_i2c1>;
782 #size-cells = <0>;
789 reg = <0xfff9c000 0x4000>;
792 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
800 reg = <0xfffa0000 0x4000>;
803 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
811 reg = <0xfffac000 0x4000>;
814 pinctrl-0 = <&pinctrl_ac97>;
822 reg = <0xfffb0000 0x100>;
823 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
826 atmel,adc-channels-used = <0xff>;
833 reg = <0xfffb4000 0x4000>;
840 #size-cells = <0>;
846 reg = <0xfffb8000 0x300>;
855 reg = <0xfff80000 0x600>;
856 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
857 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
860 #size-cells = <0>;
868 reg = <0xfffd0000 0x600>;
869 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
873 #size-cells = <0>;
881 reg = <0xfffffd40 0x10>;
892 #size-cells = <0>;
894 reg = <0xfffa4000 0x200>;
897 pinctrl-0 = <&pinctrl_spi0>;
905 #size-cells = <0>;
907 reg = <0xfffa8000 0x200>;
910 pinctrl-0 = <&pinctrl_spi1>;
918 reg = <0x00600000 0x80000
919 0xfff78000 0x400>;
920 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
928 reg = <0xfffffd50 0x4>;
930 #clock-cells = <0>;
935 reg = <0xfffffd20 0x10>;
943 reg = <0xfffffdb0 0x30>;
951 reg = <0xfffffd60 0x10>;
958 reg = <0x00500000 0x1000>;
961 pinctrl-0 = <&pinctrl_fb>;
969 reg = <0x00700000 0x100000>;
978 reg = <0x00800000 0x100000>;
991 reg = <0x10000000 0x80000000>;
992 ranges = <0x0 0x0 0x10000000 0x10000000
993 0x1 0x0 0x20000000 0x10000000
994 0x2 0x0 0x30000000 0x10000000
995 0x3 0x0 0x40000000 0x10000000
996 0x4 0x0 0x50000000 0x10000000
997 0x5 0x0 0x60000000 0x10000000>;
1011 i2c-gpio-0 {
1020 #size-cells = <0>;