| /linux/drivers/media/i2c/ |
| H A D | rdacm21.c | 28 #define OV490_I2C_ADDRESS 0x24
30 #define OV490_PAGE_HIGH_REG 0xfffd
31 #define OV490_PAGE_LOW_REG 0xfffe
37 #define OV490_SCCB_SLAVE_WRITE 0x00
38 #define OV490_SCCB_SLAVE_READ 0x01
39 #define OV490_SCCB_SLAVE0_DIR 0x80195000
40 #define OV490_SCCB_SLAVE0_ADDR_HIGH 0x80195001
41 #define OV490_SCCB_SLAVE0_ADDR_LOW 0x80195002
43 #define OV490_DVP_CTRL3 0x80286009
45 #define OV490_ODS_CTRL_FRAME_OUTPUT_EN 0x0c
[all …]
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| /linux/fs/smb/server/mgmt/ |
| H A D | ksmbd_ida.h | 14 * The value 0xFFFF MUST NOT be used as a valid TID. All other
15 * possible values for TID, including zero (0x0000), are valid.
16 * The value 0xFFFF is used to specify all TIDs or no TID,
23 * The value 0xFFFE was declared reserved in the LAN Manager 1.0
24 * documentation, so a value of 0xFFFE SHOULD NOT be used as a
26 * zero (0x0000), are valid.
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| H A D | ksmbd_ida.c | 11 return ida_alloc_range(ida, 1, 0xFFFFFFFE, KSMBD_DEFAULT_GFP); in ksmbd_acquire_smb2_tid()
19 if (id == 0xFFFE) in ksmbd_acquire_smb2_uid()
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| /linux/arch/x86/include/uapi/asm/ |
| H A D | boot.h | 6 #define NORMAL_VGA 0xffff /* 80x25 mode */
7 #define EXTENDED_VGA 0xfffe /* 80x50 mode */
8 #define ASK_VGA 0xfffd /* ask for it at bootup */
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| /linux/drivers/net/ethernet/mellanox/mlxsw/ |
| H A D | pci_hw.h | 14 #define MLXSW_PCI_CIR_BASE 0x71000
16 #define MLXSW_PCI_CIR_IN_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x04)
17 #define MLXSW_PCI_CIR_IN_MODIFIER (MLXSW_PCI_CIR_BASE + 0x08)
18 #define MLXSW_PCI_CIR_OUT_PARAM_HI (MLXSW_PCI_CIR_BASE + 0x0C)
19 #define MLXSW_PCI_CIR_OUT_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x10)
20 #define MLXSW_PCI_CIR_TOKEN (MLXSW_PCI_CIR_BASE + 0x14)
21 #define MLXSW_PCI_CIR_CTRL (MLXSW_PCI_CIR_BASE + 0x18)
30 #define MLXSW_PCI_FW_READY 0xA1844
31 #define MLXSW_PCI_FW_READY_MASK 0xFFFF
32 #define MLXSW_PCI_FW_READY_MAGIC 0x5E
[all …]
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| /linux/include/net/ |
| H A D | af_ieee802154.h | 18 IEEE802154_ADDR_NONE = 0x0,
19 /* RESERVED = 0x01, */
20 IEEE802154_ADDR_SHORT = 0x2, /* 16-bit address + PANid */
21 IEEE802154_ADDR_LONG = 0x3, /* 64-bit address + PANid */
36 #define IEEE802154_PANID_BROADCAST 0xffff
37 #define IEEE802154_ADDR_BROADCAST 0xffff
38 #define IEEE802154_ADDR_UNDEF 0xfffe
46 #define SOL_IEEE802154 0
48 #define WPAN_WANTACK 0
53 #define WPAN_SECURITY_DEFAULT 0
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| /linux/drivers/gpu/drm/gma500/ |
| H A D | psb_device.c | 23 return 0; in psb_output_init()
35 #define PSB_BLC_MAX_PWM_REG_FREQ 0xFFFE
36 #define PSB_BLC_MIN_PWM_REG_FREQ 0x2
38 #define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
77 return 0; in psb_backlight_setup()
138 return 0; in psb_save_display_registers()
167 PSB_WVDC32(0x80000000, VGACNTRL); in psb_restore_display_registers()
183 return 0; in psb_restore_display_registers()
188 return 0; in psb_power_down()
193 return 0; in psb_power_up()
[all …]
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | r600_dma.c | 60 return (rptr & 0x3fffc) >> 2; in r600_dma_get_rptr()
74 return (RREG32(DMA_RB_WPTR) & 0x3fffc) >> 2; in r600_dma_get_wptr()
88 WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc); in r600_dma_set_wptr()
117 * Returns 0 for success, error for failure.
126 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0); in r600_dma_resume()
127 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); in r600_dma_resume()
138 WREG32(DMA_RB_RPTR, 0); in r600_dma_resume()
139 WREG32(DMA_RB_WPTR, 0); in r600_dma_resume()
143 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); in r600_dma_resume()
145 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC)); in r600_dma_resume()
[all …]
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| /linux/include/linux/mtd/ |
| H A D | nftl.h | 15 #define BLOCK_NIL 0xffff /* last block of a chain */
16 #define BLOCK_FREE 0xfffe /* free block */
17 #define BLOCK_NOTEXPLORED 0xfffd /* non explored block, only used during mounting */
18 #define BLOCK_RESERVED 0xfffc /* bios block or bad block */
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| /linux/drivers/firmware/efi/libstub/ |
| H A D | smbios.c | 41 u16 handle = 0xfffe; in efi_get_smbios_record()
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| /linux/drivers/watchdog/ |
| H A D | ibmasr.c | 36 #define TOPAZ_ASR_TOGGLE 0x40
37 #define TOPAZ_ASR_DISABLE 0x80
40 #define PEARL_BASE 0xe04
41 #define PEARL_WRITE 0xe06
42 #define PEARL_READ 0xe07
44 #define PEARL_ASR_DISABLE_MASK 0x80 /* bit 7: disable = 1, enable = 0 */
45 #define PEARL_ASR_TOGGLE_MASK 0x40 /* bit 6: 0, then 1, then 0 */
48 #define JASPER_ASR_REG_OFFSET 0x38
50 #define JASPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1, enable = 0 */
51 #define JASPER_ASR_TOGGLE_MASK 0x02 /* bit 1: 0, then 1, then 0 */
[all …]
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| /linux/net/smc/ |
| H A D | smc_ism.h | 18 #define SMC_EMULATED_ISM_CHID_MASK 0xFF00
19 #define SMC_ISM_IDENT_MASK 0x00FFFF
71 return rc < 0 ? rc : 0; in smc_ism_write()
76 /* CHIDs in range of 0xFF00 to 0xFFFF are reserved in __smc_ism_is_emulated()
79 * loopback-ism: 0xFFFF in __smc_ism_is_emulated()
80 * virtio-ism: 0xFF00 ~ 0xFFFE in __smc_ism_is_emulated()
82 return ((chid & 0xFF00) == 0xFF00); in __smc_ism_is_emulated()
94 return (smcd->ops->get_chid(smcd) == 0xFFFF); in smc_ism_is_loopback()
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| /linux/drivers/mfd/ |
| H A D | wm97xx-core.c | 23 #define WM9705_VENDOR_ID 0x574d4c05
24 #define WM9712_VENDOR_ID 0x574d4c12
25 #define WM9713_VENDOR_ID 0x574d4c13
26 #define WM97xx_VENDOR_ID_MASK 0xffffffff
42 case AC97_GPIO_CFG ... 0x5c: in wm97xx_readable_reg()
44 case 0x74 ... AC97_VENDOR_ID2: in wm97xx_readable_reg()
63 { 0x02, 0x8000 },
64 { 0x04, 0x8000 },
65 { 0x06, 0x8000 },
66 { 0x0a, 0x8000 },
[all …]
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| /linux/arch/powerpc/platforms/powernv/ |
| H A D | opal-lpc.c | 29 if (opal_lpc_chip_id < 0 || port > 0xffff) in opal_lpc_inb()
30 return 0xff; in opal_lpc_inb()
32 return rc ? 0xff : be32_to_cpu(data); in opal_lpc_inb()
40 if (opal_lpc_chip_id < 0 || port > 0xfffe) in __opal_lpc_inw()
41 return 0xffff; in __opal_lpc_inw()
45 return rc ? 0xffff : be32_to_cpu(data); in __opal_lpc_inw()
57 if (opal_lpc_chip_id < 0 || port > 0xfffc) in __opal_lpc_inl()
58 return 0xffffffff; in __opal_lpc_inl()
65 return rc ? 0xffffffff : be32_to_cpu(data); in __opal_lpc_inl()
75 if (opal_lpc_chip_id < 0 || port > 0xffff) in opal_lpc_outb()
[all …]
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| /linux/drivers/net/wireless/broadcom/b43/ |
| H A D | tables.c | 21 0xFEB93FFD, 0xFEC63FFD, /* 0 */
22 0xFED23FFD, 0xFEDF3FFD,
23 0xFEEC3FFE, 0xFEF83FFE,
24 0xFF053FFE, 0xFF113FFE,
25 0xFF1E3FFE, 0xFF2A3FFF, /* 8 */
26 0xFF373FFF, 0xFF443FFF,
27 0xFF503FFF, 0xFF5D3FFF,
28 0xFF693FFF, 0xFF763FFF,
29 0xFF824000, 0xFF8F4000, /* 16 */
30 0xFF9B4000, 0xFFA84000,
[all …]
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| /linux/drivers/phy/lantiq/ |
| H A D | phy-lantiq-vrx200-pcie.c | 29 #define PCIE_PHY_PLL_CTRL1 0x44
31 #define PCIE_PHY_PLL_CTRL2 0x46
32 #define PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK GENMASK(7, 0)
36 #define PCIE_PHY_PLL_CTRL3 0x48
40 #define PCIE_PHY_PLL_CTRL4 0x4a
41 #define PCIE_PHY_PLL_CTRL5 0x4c
42 #define PCIE_PHY_PLL_CTRL6 0x4e
43 #define PCIE_PHY_PLL_CTRL7 0x50
44 #define PCIE_PHY_PLL_A_CTRL1 0x52
46 #define PCIE_PHY_PLL_A_CTRL2 0x54
[all …]
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_backlight_regs.h | 11 #define _VLV_BLC_PWM_CTL2_A (VLV_DISPLAY_BASE + 0x61250)
12 #define _VLV_BLC_PWM_CTL2_B (VLV_DISPLAY_BASE + 0x61350)
15 #define _VLV_BLC_PWM_CTL_A (VLV_DISPLAY_BASE + 0x61254)
16 #define _VLV_BLC_PWM_CTL_B (VLV_DISPLAY_BASE + 0x61354)
19 #define _VLV_BLC_HIST_CTL_A (VLV_DISPLAY_BASE + 0x61260)
20 #define _VLV_BLC_HIST_CTL_B (VLV_DISPLAY_BASE + 0x61360)
24 #define BLC_PWM_CTL2 _MMIO(0x61250) /* 965+ only */
29 #define BLM_PIPE_A (0 << 29)
42 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
44 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
[all …]
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| /linux/Documentation/admin-guide/ |
| H A D | svga.rst | 37 0..35 - Menu item number (when you have used the menu to view the list of
39 to use). 0..9 correspond to "0".."9", 10..35 to "a".."z". Warning: the
44 0x.... - Hexadecimal video mode ID (also displayed on the menu, see below
61 0 0F00 80x25
62 1 0F01 80x50
63 2 0F02 80x43
64 3 0F03 80x26
74 "0 0F00 80x25" means that the first menu item (the menu items are numbered
75 from "0" to "9" and from "a" to "z") is a 80x25 mode with ID=0x0f00 (see the
112 expressed in a hexadecimal notation (starting with "0x"). You can set a mode
[all …]
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| /linux/drivers/pnp/pnpbios/ |
| H A D | pnpbios.h | 17 #define PNP_SUCCESS 0x00
18 #define PNP_NOT_SET_STATICALLY 0x7f
19 #define PNP_UNKNOWN_FUNCTION 0x81
20 #define PNP_FUNCTION_NOT_SUPPORTED 0x82
21 #define PNP_INVALID_HANDLE 0x83
22 #define PNP_BAD_PARAMETER 0x84
23 #define PNP_SET_FAILED 0x85
24 #define PNP_EVENTS_NOT_PENDING 0x86
25 #define PNP_SYSTEM_NOT_DOCKED 0x87
26 #define PNP_NO_ISA_PNP_CARDS 0x88
[all …]
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| /linux/include/linux/mlx5/ |
| H A D | vport.h | 52 MLX5_VPORT_PF = 0x0,
53 MLX5_VPORT_FIRST_VF = 0x1,
54 MLX5_VPORT_ECPF = 0xfffe,
55 MLX5_VPORT_UPLINK = 0xffff
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| /linux/drivers/clocksource/ |
| H A D | timer-meson6.c | 26 #define MESON_ISA_TIMER_MUX 0x00
36 #define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_SYSTEM_CLOCK 0x0
37 #define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US 0x1
38 #define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_10US 0x2
39 #define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_100US 0x3
40 #define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1MS 0x4
44 #define MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK GENMASK(1, 0)
45 #define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US 0x0
46 #define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_10US 0x1
47 #define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_100US 0x0
[all …]
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| H A D | timer-cs5535.c | 70 cs5535_mfgpt_write(timer, MFGPT_REG_COUNTER, 0); in start_timer()
79 return 0; in mfgpt_shutdown()
86 return 0; in mfgpt_set_periodic()
92 return 0; in mfgpt_next_event()
122 cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_COUNTER, 0); in mfgpt_tick()
172 0xF, 0xFFFE); in cs5535_mfgpt_init()
174 return 0; in cs5535_mfgpt_init()
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| /linux/drivers/net/wireless/broadcom/b43legacy/ |
| H A D | ilt.c | 23 0xFEB93FFD, 0xFEC63FFD, /* 0 */
24 0xFED23FFD, 0xFEDF3FFD,
25 0xFEEC3FFE, 0xFEF83FFE,
26 0xFF053FFE, 0xFF113FFE,
27 0xFF1E3FFE, 0xFF2A3FFF, /* 8 */
28 0xFF373FFF, 0xFF443FFF,
29 0xFF503FFF, 0xFF5D3FFF,
30 0xFF693FFF, 0xFF763FFF,
31 0xFF824000, 0xFF8F4000, /* 16 */
32 0xFF9B4000, 0xFFA84000,
[all …]
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| /linux/include/uapi/linux/raid/ |
| H A D | md_p.h | 29 * 0 - 31 Constant generic RAID device information.
56 #define MD_SB_GENERIC_OFFSET 0
74 #define MD_DISK_FAULTY 0 /* disk is faulty / operational */
95 #define MD_DISK_ROLE_SPARE 0xffff
96 #define MD_DISK_ROLE_FAULTY 0xfffe
97 #define MD_DISK_ROLE_JOURNAL 0xfffd
98 #define MD_DISK_ROLE_MAX 0xff00 /* max value of regular disk role */
101 __u32 number; /* 0 Device number in the entire set */
109 #define MD_SB_MAGIC 0xa92b4ef
[all...] |
| /linux/include/rdma/ |
| H A D | iba.h | 123 IBA_FIELD_BLOC(field_struct, byte_offset, 0, num_bits)
126 field_struct, (byte_offset)&0xFFFE, \
132 field_struct, (byte_offset)&0xFFFC, \
138 field_struct, byte_offset, GENMASK_ULL(63, 0), 64
|