28 #define OV490_I2C_ADDRESS		0x24
30 #define OV490_PAGE_HIGH_REG		0xfffd
31 #define OV490_PAGE_LOW_REG		0xfffe
37 #define OV490_SCCB_SLAVE_WRITE		0x00
38 #define OV490_SCCB_SLAVE_READ		0x01
39 #define OV490_SCCB_SLAVE0_DIR		0x80195000
40 #define OV490_SCCB_SLAVE0_ADDR_HIGH	0x80195001
41 #define OV490_SCCB_SLAVE0_ADDR_LOW	0x80195002
43 #define OV490_DVP_CTRL3			0x80286009
45 #define OV490_ODS_CTRL_FRAME_OUTPUT_EN	0x0c
46 #define OV490_ODS_CTRL			0x8029d000
48 #define OV490_HOST_CMD			0x808000c0
49 #define OV490_HOST_CMD_TRIGGER		0xc1
51 #define OV490_ID_VAL			0x0490
52 #define OV490_ID(_p, _v)		((((_p) & 0xff) << 8) | ((_v) & 0xff))
53 #define OV490_PID			0x8080300a
54 #define OV490_VER			0x8080300b
58 #define OV490_GPIO0			BIT(0)
59 #define OV490_SPWDN0			BIT(0)
60 #define OV490_GPIO_SEL0			0x80800050
61 #define OV490_GPIO_SEL1			0x80800051
62 #define OV490_GPIO_DIRECTION0		0x80800054
63 #define OV490_GPIO_DIRECTION1		0x80800055
64 #define OV490_GPIO_OUTPUT_VALUE0	0x80800058
65 #define OV490_GPIO_OUTPUT_VALUE1	0x80800059
67 #define OV490_ISP_HSIZE_LOW		0x80820060
68 #define OV490_ISP_HSIZE_HIGH		0x80820061
69 #define OV490_ISP_VSIZE_LOW		0x80820062
70 #define OV490_ISP_VSIZE_HIGH		0x80820063
73 #define OV10640_ID_HIGH			0xa6
74 #define OV10640_CHIP_ID			0x300a
98 	{0xfffd, 0x80},
99 	{0xfffe, 0x82},
100 	{0x0071, 0x11},
101 	{0x0075, 0x11},
102 	{0xfffe, 0x29},
103 	{0x6010, 0x01},
108 	{0xe000, 0x14},
109 	{0xfffe, 0x28},
110 	{0x6000, 0x04},
111 	{0x6004, 0x00},
114 	 * Use 0x808000bb register instead.
116 	{0x6008, 0x00},
117 	{0xfffe, 0x80},
118 	{0x0091, 0x00},
119 	/* bit[3]=0 - PCLK polarity workaround. */
120 	{0x00bb, 0x1d},
122 	{0xfffe, 0x85},
123 	{0x0008, 0x00},
124 	{0x0009, 0x01},
126 	{0x000A, 0x05},
127 	{0x000B, 0x00},
129 	{0x0030, 0x02},
130 	{0x0031, 0x00},
131 	{0x0032, 0x00},
132 	{0x0033, 0x00},
134 	{0x0038, 0x02},
135 	{0x0039, 0x00},
136 	{0x003A, 0x00},
137 	{0x003B, 0x00},
139 	{0x0070, 0x2C},
140 	{0x0071, 0x01},
141 	{0x0072, 0x00},
142 	{0x0073, 0x00},
144 	{0x0074, 0x64},
145 	{0x0075, 0x00},
146 	{0x0076, 0x00},
147 	{0x0077, 0x00},
148 	{0x0000, 0x14},
149 	{0x0001, 0x00},
150 	{0x0002, 0x00},
151 	{0x0003, 0x00},
156 	{0x0004, 0x32},
157 	{0x0005, 0x00},
158 	{0x0006, 0x00},
159 	{0x0007, 0x00},
160 	{0xfffe, 0x80},
162 	{0x0081, 0x00},
164 	{0xfffe, 0x19},
165 	{0x5000, 0x00},
166 	{0x5001, 0x30},
167 	{0x5002, 0x8c},
168 	{0x5003, 0xb2},
169 	{0xfffe, 0x80},
170 	{0x00c0, 0xc1},
172 	{0xfffe, 0x19},
173 	{0x5000, 0x01},
174 	{0x5001, 0x00},
175 	{0xfffe, 0x80},
176 	{0x00c0, 0xdc},
188 	if (ret < 0) {  in ov490_read()
189 		dev_dbg(dev->dev, "%s: register 0x%04x read failed (%d)\n",  in ov490_read()
194 	return 0;  in ov490_read()
203 	if (ret < 0) {  in ov490_write()
204 		dev_err(dev->dev, "%s: register 0x%04x write failed (%d)\n",  in ov490_write()
209 	return 0;  in ov490_write()
219 		return 0;  in ov490_set_page()
236 	return 0;  in ov490_set_page()
251 	dev_dbg(dev->dev, "%s: 0x%08x = 0x%02x\n", __func__, reg, *val);  in ov490_read_reg()
253 	return 0;  in ov490_read_reg()
268 	dev_dbg(dev->dev, "%s: 0x%08x = 0x%02x\n", __func__, reg, val);  in ov490_write_reg()
270 	return 0;  in ov490_write_reg()
288 	if (code->pad || code->index > 0)  in rdacm21_enum_mbus_code()
293 	return 0;  in rdacm21_enum_mbus_code()
315 	return 0;  in rdacm21_get_fmt()
335 	/* Enable GPIO0#0 (reset) and GPIO1#0 (pwdn) as output lines. */  in ov10640_power_up()
345 	ov490_write_reg(dev, OV490_GPIO_OUTPUT_VALUE0, 0x00);  in ov10640_power_up()
354 	u8 val = 0;  in ov10640_check_id()
357 	for (i = 0; i < OV10640_PID_TIMEOUT; ++i) {  in ov10640_check_id()
363 				OV10640_CHIP_ID & 0xff);  in ov10640_check_id()
378 		dev_err(dev->dev, "OV10640 ID mismatch: (0x%02x)\n", val);  in ov10640_check_id()
382 	dev_dbg(dev->dev, "OV10640 ID = 0x%2x\n", val);  in ov10640_check_id()
384 	return 0;  in ov10640_check_id()
399 	for (i = 0; i < OV490_PID_TIMEOUT; ++i) {  in ov490_initialize()
401 		if (ret == 0)  in ov490_initialize()
411 	if (ret < 0)  in ov490_initialize()
415 		dev_err(dev->dev, "OV490 ID mismatch (0x%04x)\n",  in ov490_initialize()
421 	for (i = 0; i < OV490_OUTPUT_EN_TIMEOUT; ++i) {  in ov490_initialize()
437 	for (i = 0; i < ARRAY_SIZE(ov490_regs_wizard); ++i) {  in ov490_initialize()
440 		if (ret < 0) {  in ov490_initialize()
442 				"%s: register %u (0x%04x) write failed (%d)\n",  in ov490_initialize()
456 	dev->fmt.width = (val & 0xf) << 8;  in ov490_initialize()
458 	dev->fmt.width |= (val & 0xff);  in ov490_initialize()
461 	dev->fmt.height = (val & 0xf) << 8;  in ov490_initialize()
463 	dev->fmt.height |= val & 0xff;  in ov490_initialize()
465 	/* Set bus width to 12 bits with [0:11] ordering. */  in ov490_initialize()
466 	ov490_write_reg(dev, OV490_DVP_CTRL3, 0x10);  in ov490_initialize()
470 	return 0;  in ov490_initialize()
513 	ret = max9271_set_address(&dev->serializer, dev->addrs[0]);  in rdacm21_initialize()
516 	dev->serializer.client->addr = dev->addrs[0];  in rdacm21_initialize()
556 	if (ret < 0) {  in rdacm21_probe()
567 	if (ret < 0)  in rdacm21_probe()
587 	if (ret < 0)  in rdacm21_probe()
594 	return 0;  in rdacm21_probe()