Lines Matching +full:0 +full:xfffe

14 #define MLXSW_PCI_CIR_BASE			0x71000
16 #define MLXSW_PCI_CIR_IN_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x04)
17 #define MLXSW_PCI_CIR_IN_MODIFIER (MLXSW_PCI_CIR_BASE + 0x08)
18 #define MLXSW_PCI_CIR_OUT_PARAM_HI (MLXSW_PCI_CIR_BASE + 0x0C)
19 #define MLXSW_PCI_CIR_OUT_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x10)
20 #define MLXSW_PCI_CIR_TOKEN (MLXSW_PCI_CIR_BASE + 0x14)
21 #define MLXSW_PCI_CIR_CTRL (MLXSW_PCI_CIR_BASE + 0x18)
30 #define MLXSW_PCI_FW_READY 0xA1844
31 #define MLXSW_PCI_FW_READY_MASK 0xFFFF
32 #define MLXSW_PCI_FW_READY_MAGIC 0x5E
34 #define MLXSW_PCI_DOORBELL_SDQ_OFFSET 0x000
35 #define MLXSW_PCI_DOORBELL_RDQ_OFFSET 0x200
36 #define MLXSW_PCI_DOORBELL_CQ_OFFSET 0x400
37 #define MLXSW_PCI_DOORBELL_EQ_OFFSET 0x600
38 #define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET 0x800
39 #define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET 0xA00
50 #define MLXSW_PCI_SDQ_EMAD_INDEX 0
51 #define MLXSW_PCI_SDQ_EMAD_TC 0
65 #define MLXSW_PCI_EQE_UPDATE_COUNT 0x80
68 #define MLXSW_PCI_WQE_TYPE_ETHERNET 0xA
74 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
86 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
91 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
96 MLXSW_ITEM32(pci, wqe, ipcs, 0x00, 14, 1);
99 * Size of i-th scatter/gather entry, 0 if entry is unused.
101 MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false);
107 MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false);
148 MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1);
149 MLXSW_ITEM32(pci, cqe12, lag, 0x00, 24, 1);
150 mlxsw_pci_cqe_item_helpers(lag, 0, 12, 12);
153 * When lag=0: System port on which the packet was received
156 * bits [3:0] sub_port on which the packet was received
158 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
159 MLXSW_ITEM32(pci, cqe0, lag_id, 0x00, 4, 12);
160 MLXSW_ITEM32(pci, cqe12, lag_id, 0x00, 0, 16);
161 mlxsw_pci_cqe_item_helpers(lag_id, 0, 12, 12);
162 MLXSW_ITEM32(pci, cqe0, lag_subport, 0x00, 0, 4);
163 MLXSW_ITEM32(pci, cqe12, lag_subport, 0x00, 16, 8);
164 mlxsw_pci_cqe_item_helpers(lag_subport, 0, 12, 12);
169 MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);
176 MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
178 #define MLXSW_PCI_CQE2_MIRROR_CONG_INVALID 0xFFFF
182 * packet that does mirroring to the CPU. Value of 0xFFFF means that the
185 MLXSW_ITEM32(pci, cqe2, mirror_cong_high, 0x08, 16, 4);
190 MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 10);
196 MLXSW_ITEM32(pci, cqe0, crc, 0x0C, 8, 1);
197 MLXSW_ITEM32(pci, cqe12, crc, 0x0C, 9, 1);
198 mlxsw_pci_cqe_item_helpers(crc, 0, 12, 12);
203 MLXSW_ITEM32(pci, cqe0, e, 0x0C, 7, 1);
204 MLXSW_ITEM32(pci, cqe12, e, 0x00, 27, 1);
205 mlxsw_pci_cqe_item_helpers(e, 0, 12, 12);
209 * 0 - Receive Queue
211 MLXSW_ITEM32(pci, cqe0, sr, 0x0C, 6, 1);
212 MLXSW_ITEM32(pci, cqe12, sr, 0x00, 26, 1);
213 mlxsw_pci_cqe_item_helpers(sr, 0, 12, 12);
218 MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5);
219 MLXSW_ITEM32(pci, cqe12, dqn, 0x0C, 1, 6);
220 mlxsw_pci_cqe_item_helpers(dqn, 0, 12, 12);
225 * 0: uSec - 1.024uSec (default for devices which do not support
226 * time_stamp_type). Only bits 15:0 are valid
229 * - time_stamp[29:0] = nSec
233 * - time_stamp[29:0] = nSec
234 * Formats 0..2 are configured by
239 MLXSW_ITEM32(pci, cqe2, time_stamp_low, 0x0C, 16, 16);
241 #define MLXSW_PCI_CQE2_MIRROR_TCLASS_INVALID 0x1F
245 * CPU. Value of 0x1F means that the traffic class is invalid.
247 MLXSW_ITEM32(pci, cqe2, mirror_tclass, 0x10, 27, 5);
252 MLXSW_ITEM32(pci, cqe2, tx_lag, 0x10, 24, 1);
256 * CPU. Reserved when tx_lag is 0.
258 MLXSW_ITEM32(pci, cqe2, tx_lag_subport, 0x10, 16, 8);
260 #define MLXSW_PCI_CQE2_TX_PORT_MULTI_PORT 0xFFFE
261 #define MLXSW_PCI_CQE2_TX_PORT_INVALID 0xFFFF
265 * Value of 0xFFFE means multi-port. Value fo 0xFFFF means that the Tx LAG ID
266 * is invalid. Reserved when tx_lag is 0.
268 MLXSW_ITEM32(pci, cqe2, tx_lag_id, 0x10, 0, 16);
272 * Value of 0xFFFE means multi-port. Value fo 0xFFFF means that the Tx port is
275 MLXSW_ITEM32(pci, cqe2, tx_system_port, 0x10, 0, 16);
279 * packet that does mirroring to the CPU. Value of 0xFFFF means that the
282 MLXSW_ITEM32(pci, cqe2, mirror_cong_low, 0x14, 20, 12);
297 MLXSW_ITEM32(pci, cqe2, user_def_val_orig_pkt_len, 0x14, 0, 20);
302 MLXSW_ITEM32(pci, cqe2, mirror_reason, 0x18, 24, 8);
313 * 0: uSec - 1.024uSec (default for devices which do not support
320 MLXSW_ITEM32(pci, cqe2, time_stamp_type, 0x18, 22, 2);
322 #define MLXSW_PCI_CQE2_MIRROR_LATENCY_INVALID 0xFFFFFF
327 * 0: uSec - 1.024uSec (default for devices which do not support
328 * time_stamp_type). Only bits 15:0 are valid
331 * - time_stamp[29:0] = nSec
335 * - time_stamp[29:0] = nSec
336 * Formats 0..2 are configured by
341 MLXSW_ITEM32(pci, cqe2, time_stamp_high, 0x18, 0, 22);
355 return full_ts >> 30 & 0xFF; in mlxsw_pci_cqe2_time_stamp_sec_get()
362 return full_ts & 0x3FFFFFFF; in mlxsw_pci_cqe2_time_stamp_nsec_get()
367 * Value of 0xFFFFFF means that the latency is invalid. Units are according to
370 MLXSW_ITEM32(pci, cqe2, mirror_latency, 0x1C, 8, 24);
375 MLXSW_ITEM32(pci, cqe01, owner, 0x0C, 0, 1);
376 MLXSW_ITEM32(pci, cqe2, owner, 0x1C, 0, 1);
382 MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8);
383 #define MLXSW_PCI_EQE_EVENT_TYPE_COMP 0x00
384 #define MLXSW_PCI_EQE_EVENT_TYPE_CMD 0x0A
389 MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);
394 MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);
399 MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1);
404 MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16);
409 MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8);
414 MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32);
419 MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32);