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Searched +full:0 +full:xfee00000 (Results 1 – 13 of 13) sorted by relevance

/linux/arch/arm/mach-socfpga/
H A Dcore.h10 #define SOCFPGA_RSTMGR_CTRL 0x04
11 #define SOCFPGA_RSTMGR_MODMPURST 0x10
12 #define SOCFPGA_RSTMGR_MODPERRST 0x14
13 #define SOCFPGA_RSTMGR_BRGMODRST 0x1c
15 #define SOCFPGA_A10_RSTMGR_CTRL 0xC
16 #define SOCFPGA_A10_RSTMGR_MODMPURST 0x20
19 #define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */
20 #define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */
22 #define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
40 #define SOCFPGA_SCU_VIRT_BASE 0xfee00000
/linux/drivers/gpu/drm/xe/regs/
H A Dxe_gtt_defs.h19 #define GUC_GGTT_TOP 0xFEE00000
39 #define XE_PAGE_PRESENT BIT_ULL(0)
/linux/arch/m68k/include/asm/
H A Dsun3xprom.h18 #define SUN3X_IOMMU 0x60000000
19 #define SUN3X_ENAREG 0x61000000
20 #define SUN3X_INTREG 0x61001400
21 #define SUN3X_DIAGREG 0x61001800
22 #define SUN3X_ZS1 0x62000000
23 #define SUN3X_ZS2 0x62002000
24 #define SUN3X_LANCE 0x65002000
25 #define SUN3X_EEPROM 0x64000000
26 #define SUN3X_IDPROM 0x640007d8
27 #define SUN3X_VIDEO_BASE 0x50400000
[all …]
/linux/arch/x86/include/asm/
H A Dmsi.h52 #define X86_MSI_BASE_ADDRESS_LOW (0xfee00000 >> 20)
60 #define X86_MSI_BASE_ADDRESS_HIGH (0)
/linux/arch/powerpc/sysdev/
H A Dgrackle.c18 #define GRACKLE_CFA(b, d, o) (0x80 | ((b) << 8) | ((d) << 16) \
21 #define GRACKLE_PICR1_LOOPSNOOP 0x00000010
27 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); in grackle_set_loop_snoop()
31 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); in grackle_set_loop_snoop()
38 setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0); in setup_grackle()
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dintel,ce4100-lapic.yaml67 reg = <0xfee00000 0x1000>;
/linux/arch/powerpc/platforms/embedded6xx/
H A Dmpc10x.h24 * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff
25 * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff
26 * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000
29 * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff
30 * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff
31 * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000
40 #define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA)
41 #define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA)
42 #define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA)
49 #define MPC10X_MAPA_CNFG_ADDR 0x80000cf8
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dge_imp3a.dts22 reg = <0 0xfef05000 0 0x1000>;
24 ranges = <0x0 0x0 0x0 0xff000000 0x01000000
25 0x1 0x0 0x0 0xe0000000 0x08000000
26 0x2 0x0 0x0 0xe8000000 0x08000000
27 0x3 0x0 0x0 0xfc100000 0x00020000
28 0x4 0x0 0x0 0xfc000000 0x00008000
29 0x5 0x0 0x0 0xfc008000 0x00008000
30 0x6 0x0 0x0 0xfee00000 0x00040000
31 0x7 0x0 0x0 0xfee80000 0x00040000>;
33 /* nor@0,0 is a mirror of part of the memory in nor@1,0
[all …]
H A Dc293pcie.dts46 reg = <0xf 0xffe1e000 0 0x2000>;
47 ranges = <0x0 0x0 0xf 0xec000000 0x04000000
48 0x1 0x0 0xf 0xff800000 0x00010000
49 0x2 0x0 0xf 0xffdf0000 0x00010000>;
54 ranges = <0x0 0xf 0xffe00000 0x100000>;
58 reg = <0xf 0xffe0a000 0 0x1000>;
59 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0x80000000
[all …]
/linux/arch/x86/platform/ce4100/
H A Dfalconfalls.dts16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
26 soc@0 {
36 reg = <0xfec00000 0x1000>;
41 reg = <0xfed00000 0x200>;
46 reg = <0xfee00000 0x1000>;
54 bus-range = <0 0>;
55 ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000
56 0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000
[all …]
/linux/drivers/net/ethernet/cirrus/
H A Dcs89x0.h18 #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
22 #define PP_ISAIOB 0x0020 /* IO base address */
23 #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
24 #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
25 #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
26 #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
27 #define PP_ISASOF 0x0026 /* ISA DMA offset */
28 #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
29 #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
30 #define PP_CS8900_ISAMemB 0x002C /* Memory base */
[all …]
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-naneng-combphy.c3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
24 #define RK3528_PHYREG5 0x14
27 #define RK3528_PHYREG6 0x18
29 #define RK3528_PHYREG6_PLL_KVCO_VALUE 0x2
31 #define RK3528_PHYREG6_SSC_UPWARD 0
34 #define RK3528_PHYREG40 0x100
36 #define RK3528_PHYREG40_SSC_CNT GENMASK(10, 0)
37 #define RK3528_PHYREG40_SSC_CNT_VALUE 0x17d
39 #define RK3528_PHYREG42 0x108
41 #define RK3528_PHYREG42_CKDRV_CLK_PLL 0
[all …]
/linux/drivers/iommu/amd/
H A Diommu.c53 #define MSI_RANGE_START (0xfee00000)
54 #define MSI_RANGE_END (0xfeefffff)
55 #define HT_RANGE_START (0xfd00000000ULL)
56 #define HT_RANGE_END (0xffffffffffULL)
135 amd_iommu_atomic128_set(&ptr->data128[0], new->data128[0]); in write_dte_lower128()
158 if (!(ptr->data[0] & DTE_FLAG_V)) { in update_dte256()
163 } else if (!(new->data[0] & DTE_FLAG_V)) { in update_dte256()
168 } else if (!FIELD_GET(DTE_FLAG_GV, ptr->data[0])) { in update_dte256()
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