xref: /linux/arch/arm/mach-socfpga/core.h (revision 03ab8e6297acd1bc0eedaa050e2a1635c576fd11)
11a59d1b8SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
29c4566a1SDinh Nguyen /*
39c4566a1SDinh Nguyen  * Copyright 2012 Pavel Machek <pavel@denx.de>
444fd8c7dSAlan Tull  * Copyright (C) 2012-2015 Altera Corporation
59c4566a1SDinh Nguyen  */
69c4566a1SDinh Nguyen 
79c4566a1SDinh Nguyen #ifndef __MACH_CORE_H
89c4566a1SDinh Nguyen #define __MACH_CORE_H
99c4566a1SDinh Nguyen 
105c04b57fSDinh Nguyen #define SOCFPGA_RSTMGR_CTRL	0x04
11d686ce42SAlan Tull #define SOCFPGA_RSTMGR_MODMPURST	0x10
125c04b57fSDinh Nguyen #define SOCFPGA_RSTMGR_MODPERRST	0x14
135c04b57fSDinh Nguyen #define SOCFPGA_RSTMGR_BRGMODRST	0x1c
145c04b57fSDinh Nguyen 
15cd871d51SDinh Nguyen #define SOCFPGA_A10_RSTMGR_CTRL		0xC
1645be0cdbSDinh Nguyen #define SOCFPGA_A10_RSTMGR_MODMPURST	0x20
1745be0cdbSDinh Nguyen 
185c04b57fSDinh Nguyen /* System Manager bits */
195c04b57fSDinh Nguyen #define RSTMGR_CTRL_SWCOLDRSTREQ	0x1	/* Cold Reset */
205c04b57fSDinh Nguyen #define RSTMGR_CTRL_SWWARMRSTREQ	0x2	/* Warm Reset */
215c04b57fSDinh Nguyen 
22d686ce42SAlan Tull #define RSTMGR_MPUMODRST_CPU1		0x2     /* CPU1 Reset */
23d686ce42SAlan Tull 
244d113838SThor Thayer void socfpga_init_l2_ecc(void);
257cc5a5d3SThor Thayer void socfpga_init_ocram_ecc(void);
26ff6fd147SThor Thayer void socfpga_init_arria10_l2_ecc(void);
27c5fb04ccSThor Thayer void socfpga_init_arria10_ocram_ecc(void);
289c4566a1SDinh Nguyen 
295c04b57fSDinh Nguyen extern void __iomem *sys_manager_base_addr;
305c04b57fSDinh Nguyen extern void __iomem *rst_manager_base_addr;
3144fd8c7dSAlan Tull extern void __iomem *sdr_ctl_base_addr;
325c04b57fSDinh Nguyen 
3344fd8c7dSAlan Tull u32 socfpga_sdram_self_refresh(u32 sdr_base);
3444fd8c7dSAlan Tull extern unsigned int socfpga_sdram_self_refresh_sz;
359c4566a1SDinh Nguyen 
36*187bea47STakashi Iwai extern char secondary_trampoline[], secondary_trampoline_end[];
379c4566a1SDinh Nguyen 
383a4356c0SDinh Nguyen extern unsigned long socfpga_cpu1start_addr;
399c4566a1SDinh Nguyen 
40de04261dSVince Bridgers #define SOCFPGA_SCU_VIRT_BASE   0xfee00000
419c4566a1SDinh Nguyen 
429c4566a1SDinh Nguyen #endif
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