Lines Matching +full:0 +full:xfee00000
3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
24 #define RK3528_PHYREG6 0x18
26 #define RK3528_PHYREG6_PLL_KVCO_VALUE 0x2
28 #define RK3528_PHYREG6_SSC_UPWARD 0
31 #define RK3528_PHYREG40 0x100
33 #define RK3528_PHYREG40_SSC_CNT GENMASK(10, 0)
34 #define RK3528_PHYREG40_SSC_CNT_VALUE 0x17d
36 #define RK3528_PHYREG42 0x108
38 #define RK3528_PHYREG42_CKDRV_CLK_PLL 0
41 #define RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE 0x9
43 #define RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ_VALUE 0x7
44 #define RK3528_PHYREG42_PLL_KVCO_ADJ GENMASK(2, 0)
45 #define RK3528_PHYREG42_PLL_KVCO_ADJ_VALUE 0x0
47 #define RK3528_PHYREG80 0x200
50 #define RK3528_PHYREG81 0x204
52 #define RK3528_PHYREG81_SLEW_RATE_CTRL GENMASK(2, 0)
53 #define RK3528_PHYREG81_SLEW_RATE_CTRL_SLOW 0x7
55 #define RK3528_PHYREG83 0x20c
56 #define RK3528_PHYREG83_RX_SQUELCH GENMASK(2, 0)
57 #define RK3528_PHYREG83_RX_SQUELCH_VALUE 0x6
59 #define RK3528_PHYREG86 0x218
63 #define RK3568_PHYREG6 0x14
68 #define RK3568_PHYREG7 0x18
72 #define RK3568_PHYREG7_RX_RTERM_MASK GENMASK(3, 0)
73 #define RK3568_PHYREG7_RX_RTERM_SHIFT 0
76 #define RK3568_PHYREG8 0x1C
79 #define RK3568_PHYREG11 0x28
80 #define RK3568_PHYREG11_SU_TRIM_0_7 0xF0
82 #define RK3568_PHYREG12 0x2C
85 #define RK3568_PHYREG13 0x30
87 #define RK3568_PHYREG13_RESISTER_SHIFT 0x4
91 #define RK3568_PHYREG14 0x34
92 #define RK3568_PHYREG14_CKRCV_AMP1 BIT(0)
94 #define RK3568_PHYREG15 0x38
95 #define RK3568_PHYREG15_CTLE_EN BIT(0)
100 #define RK3568_PHYREG16 0x3C
101 #define RK3568_PHYREG16_SSC_CNT_VALUE 0x5f
103 #define RK3568_PHYREG18 0x44
104 #define RK3568_PHYREG18_PLL_LOOP 0x32
106 #define RK3568_PHYREG32 0x7C
110 #define RK3568_PHYREG32_SSC_UPWARD 0
116 #define RK3568_PHYREG33 0x80
123 #define RK3588_PHYREG27 0x6C
124 #define RK3588_PHYREG27_RX_TRIM 0x4C
127 #define RK3576_PHYREG10 0x24
128 #define RK3576_PHYREG10_SSC_PCM_MASK GENMASK(3, 0)
131 #define RK3576_PHYREG17 0x40
133 #define RK3576_PHYREG21 0x50
134 #define RK3576_PHYREG21_RX_SQUELCH_VAL 0x0D
136 #define RK3576_PHYREG30 0x74
291 return 0; in rockchip_combphy_init()
306 return 0; in rockchip_combphy_exit()
324 if (priv->type != PHY_NONE && priv->type != args->args[0]) in rockchip_combphy_xlate()
326 args->args[0], priv->type); in rockchip_combphy_xlate()
328 priv->type = args->args[0]; in rockchip_combphy_xlate()
342 for (i = 0; i < priv->num_clks; i++) { in rockchip_combphy_parse_dt()
377 return 0; in rockchip_combphy_parse_dt()
399 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in rockchip_combphy_probe()
407 for (id = 0; id < phy_cfg->num_phys; id++) { in rockchip_combphy_probe()
460 /* Enable adaptive CTLE for USB3.0 Rx */ in rk3528_combphy_cfg()
494 /* Set ssc_cnt[10:0]=00101111101 & 31.5KHz */ in rk3528_combphy_cfg()
512 /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000, swing 650mv */ in rk3528_combphy_cfg()
513 writel(0x570804f0, priv->mmio + RK3528_PHYREG42); in rk3528_combphy_cfg()
552 return 0; in rk3528_combphy_cfg()
557 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
558 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
559 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
560 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
561 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
562 .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 },
563 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
564 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
565 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
566 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
567 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
568 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
569 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x110 },
570 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x00 },
571 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x101 },
572 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
574 .u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 },
580 0xffdc0000,
609 /* Enable adaptive CTLE for USB3.0 Rx */ in rk3562_combphy_cfg()
645 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ in rk3562_combphy_cfg()
667 writel(0x4, priv->mmio + RK3568_PHYREG12); in rk3562_combphy_cfg()
673 writel(0x32, priv->mmio + RK3568_PHYREG18); in rk3562_combphy_cfg()
674 writel(0xf0, priv->mmio + RK3568_PHYREG11); in rk3562_combphy_cfg()
702 return 0; in rk3562_combphy_cfg()
707 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
708 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
709 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
710 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
711 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
712 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
713 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
714 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
715 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
716 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
717 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
718 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
719 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
720 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
721 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
722 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
723 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
724 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
725 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
731 0xff750000
761 /* Enable adaptive CTLE for USB3.0 Rx. */ in rk3568_combphy_cfg()
786 case 0: in rk3568_combphy_cfg()
802 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) in rk3568_combphy_cfg()
840 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ in rk3568_combphy_cfg()
905 return 0; in rk3568_combphy_cfg()
910 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
911 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
912 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 },
913 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 },
914 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
915 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
916 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
917 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
918 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
919 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
920 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
921 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
922 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
923 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
924 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
925 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
926 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 },
927 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
928 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
929 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
930 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
931 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
932 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 },
933 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 },
934 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 },
935 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 },
937 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 },
938 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 },
939 .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 },
940 .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 },
946 0xfe820000,
947 0xfe830000,
948 0xfe840000,
977 /* Enable adaptive CTLE for USB3.0 Rx */ in rk3576_combphy_cfg()
1037 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ in rk3576_combphy_cfg()
1052 writel(0x00, priv->mmio + RK3588_PHYREG27); in rk3576_combphy_cfg()
1056 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min in rk3576_combphy_cfg()
1060 writel(0x90, priv->mmio + RK3568_PHYREG11); in rk3576_combphy_cfg()
1061 writel(0x02, priv->mmio + RK3568_PHYREG12); in rk3576_combphy_cfg()
1062 writel(0x57, priv->mmio + RK3568_PHYREG14); in rk3576_combphy_cfg()
1076 writel(0xc0, priv->mmio + RK3576_PHYREG30); in rk3576_combphy_cfg()
1085 writel(0x4c, priv->mmio + RK3588_PHYREG27); in rk3576_combphy_cfg()
1089 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min in rk3576_combphy_cfg()
1095 writel(0x90, priv->mmio + RK3568_PHYREG11); in rk3576_combphy_cfg()
1096 writel(0x43, priv->mmio + RK3568_PHYREG12); in rk3576_combphy_cfg()
1097 writel(0x88, priv->mmio + RK3568_PHYREG13); in rk3576_combphy_cfg()
1098 writel(0x56, priv->mmio + RK3568_PHYREG14); in rk3576_combphy_cfg()
1129 writel(0x0c, priv->mmio + RK3588_PHYREG27); in rk3576_combphy_cfg()
1133 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min in rk3576_combphy_cfg()
1139 writel(0x90, priv->mmio + RK3568_PHYREG11); in rk3576_combphy_cfg()
1140 writel(0x43, priv->mmio + RK3568_PHYREG12); in rk3576_combphy_cfg()
1141 writel(0x88, priv->mmio + RK3568_PHYREG13); in rk3576_combphy_cfg()
1142 writel(0x56, priv->mmio + RK3568_PHYREG14); in rk3576_combphy_cfg()
1153 writel(0x00, priv->mmio + RK3576_PHYREG17); in rk3576_combphy_cfg()
1157 writel(0x00, priv->mmio + RK3588_PHYREG27); in rk3576_combphy_cfg()
1161 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min in rk3576_combphy_cfg()
1166 writel(0x90, priv->mmio + RK3568_PHYREG11); in rk3576_combphy_cfg()
1167 writel(0x02, priv->mmio + RK3568_PHYREG12); in rk3576_combphy_cfg()
1168 writel(0x08, priv->mmio + RK3568_PHYREG13); in rk3576_combphy_cfg()
1169 writel(0x57, priv->mmio + RK3568_PHYREG14); in rk3576_combphy_cfg()
1170 writel(0x40, priv->mmio + RK3568_PHYREG15); in rk3576_combphy_cfg()
1180 return 0; in rk3576_combphy_cfg()
1185 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
1186 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
1187 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
1188 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
1189 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
1190 .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 },
1191 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
1192 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
1193 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
1194 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
1195 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
1196 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
1197 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
1198 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
1199 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
1200 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
1201 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
1202 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
1203 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
1204 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
1205 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
1206 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
1207 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
1209 .pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 },
1210 .pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 },
1216 0x2b050000,
1217 0x2b060000
1249 /* Enable adaptive CTLE for USB3.0 Rx. */ in rk3588_combphy_cfg()
1280 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) in rk3588_combphy_cfg()
1305 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ in rk3588_combphy_cfg()
1367 return 0; in rk3588_combphy_cfg()
1372 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
1373 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
1374 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
1375 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
1376 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
1377 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
1378 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
1379 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
1380 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
1381 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
1382 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
1383 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
1384 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
1385 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
1386 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
1387 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
1388 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
1389 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
1390 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
1391 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
1393 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 },
1394 .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 },
1395 .pipe_pcie1l0_sel = { 0x0100, 0, 0, 0x01, 0x0 },
1396 .pipe_pcie1l1_sel = { 0x0100, 1, 1, 0x01, 0x0 },
1402 0xfee00000,
1403 0xfee10000,
1404 0xfee20000,