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/linux/Documentation/devicetree/bindings/net/
H A Dopencores-ethoc.txt18 reg = <0xfd030000 0x4000 0xfd800000 0x4000>;
/linux/Documentation/devicetree/bindings/pci/
H A Damazon,al-alpine-v3-pcie.yaml57 reg = <0x0 0xfb600000 0x0 0x00100000
58 0x0 0xfd800000 0x0 0x00010000
59 0x0 0xfd810000 0x0 0x00001000>;
61 bus-range = <0 255>;
67 interrupt-map-mask = <0x00 0 0 7>;
68 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; /* INTa */
69 ranges = <0x02000000 0x0 0xc0010000 0x0 0xc0010000 0x0 0x07ff0000>;
/linux/arch/sh/kernel/cpu/shmobile/
H A Dpm.c41 #define RAM_BASE 0xfd800000 /* RSMEM */
43 #define RAM_BASE 0xe5200000 /* ILRAM */
86 /* part 0: data area */ in sh_mobile_register_self_refresh()
88 sdp->addr.stbcr = 0xa4150020; /* STBCR */ in sh_mobile_register_self_refresh()
89 sdp->addr.bar = 0xa4150040; /* BAR */ in sh_mobile_register_self_refresh()
90 sdp->addr.pteh = 0xff000000; /* PTEH */ in sh_mobile_register_self_refresh()
91 sdp->addr.ptel = 0xff000004; /* PTEL */ in sh_mobile_register_self_refresh()
92 sdp->addr.ttb = 0xff000008; /* TTB */ in sh_mobile_register_self_refresh()
93 sdp->addr.tea = 0xff00000c; /* TEA */ in sh_mobile_register_self_refresh()
94 sdp->addr.mmucr = 0xff000010; /* MMUCR */ in sh_mobile_register_self_refresh()
[all …]
/linux/arch/sh/drivers/pci/
H A Dpcie-sh7786.c44 .name = "PCIe0 MEM 0",
45 .start = 0xfd000000,
46 .end = 0xfd000000 + SZ_8M - 1,
50 .start = 0xc0000000,
51 .end = 0xc0000000 + SZ_512M - 1,
55 .start = 0x10000000,
56 .end = 0x10000000 + SZ_64M - 1,
60 .start = 0xfe100000,
61 .end = 0xfe100000 + SZ_1M - 1,
68 .name = "PCIe1 MEM 0",
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dgef_sbc610.dts25 reg = <0x0 0x40000000>; // set by uboot
29 reg = <0xfef05000 0x1000>;
31 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
32 1 0 0xe8000000 0x08000000 // Paged Flash 0
33 2 0 0xe0000000 0x08000000 // Paged Flash 1
34 3 0 0xfc100000 0x00020000 // NVRAM
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
[all …]
H A Dgef_ppc9a.dts25 reg = <0x0 0x40000000>; // set by uboot
29 reg = <0xfef05000 0x1000>;
31 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
32 1 0 0xe8000000 0x08000000 // Paged Flash 0
33 2 0 0xe0000000 0x08000000 // Paged Flash 1
34 3 0 0xfc100000 0x00020000 // NVRAM
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
[all …]
/linux/arch/powerpc/platforms/pasemi/
H A Ddma_lib.c109 start = 0; in pasemi_alloc_tx_chan()
117 start = 0; in pasemi_alloc_tx_chan()
238 * Allocate a descriptor ring for a channel. Returns 0 on success, errno
255 return 0; in pasemi_dma_alloc_ring()
271 chan->ring_size = 0; in pasemi_dma_free_ring()
272 chan->ring_dma = 0; in pasemi_dma_free_ring()
303 * Returns 1 on success, 0 on failure.
314 for (retries = 0; retries < MAX_RETRIES; retries++) { in pasemi_dma_stop_chan()
317 pasemi_write_dma_reg(reg, 0); in pasemi_dma_stop_chan()
325 for (retries = 0; retries < MAX_RETRIES; retries++) { in pasemi_dma_stop_chan()
[all …]
/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi31 bootscr-address = /bits/ 64 <0x20000000>;
37 #size-cells = <0>;
39 cpu0: cpu@0 {
45 reg = <0x0>;
55 reg = <0x1>;
66 reg = <0x2>;
77 reg = <0x3>;
92 CPU_SLEEP_0: cpu-sleep-0 {
94 arm,psci-suspend-param = <0x40000000>;
135 reg = <0x0 0x3ed00000 0x0 0x40000>;
[all …]
/linux/arch/arm64/boot/dts/exynos/google/
H A Dgs101.dtsi34 #size-cells = <0>;
71 cpu0: cpu@0 {
74 reg = <0x0000>;
84 reg = <0x0100>;
94 reg = <0x0200>;
104 reg = <0x0300>;
114 reg = <0x0400>;
124 reg = <0x0500>;
134 reg = <0x0600>;
144 reg = <0x0700>;
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a77995.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
38 #clock-cells = <0>;
39 clock-frequency = <0>;
44 #size-cells = <0>;
46 a53_0: cpu@0 {
48 reg = <0x0>;
[all …]
H A Dr8a774c0.dtsi18 * The external audio clocks are configured as 0 Hz fixed frequency
24 #clock-cells = <0>;
25 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #clock-cells = <0>;
37 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
71 #size-cells = <0>;
[all …]
H A Dr8a77990.dtsi18 * The external audio clocks are configured as 0 Hz fixed frequency
24 #clock-cells = <0>;
25 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #clock-cells = <0>;
37 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
71 #size-cells = <0>;
[all …]
H A Dr8a774a1.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
48 cluster0_opp: opp-table-0 {
[all …]
H A Dr8a774b1.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
48 cluster0_opp: opp-table-0 {
[all …]
H A Dr8a774e1.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
48 cluster0_opp: opp-table-0 {
[all …]
H A Dr8a77960.dtsi18 * The external audio clocks are configured as 0 Hz fixed frequency
24 #clock-cells = <0>;
25 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #clock-cells = <0>;
37 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
47 cluster0_opp: opp-table-0 {
[all …]
H A Dr8a77965.dtsi23 * The external audio clocks are configured as 0 Hz fixed frequency
29 #clock-cells = <0>;
30 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
41 #clock-cells = <0>;
42 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
52 cluster0_opp: opp-table-0 {
[all …]
H A Dr8a77961.dtsi18 * The external audio clocks are configured as 0 Hz fixed frequency
24 #clock-cells = <0>;
25 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #clock-cells = <0>;
37 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
47 cluster0_opp: opp-table-0 {
[all …]
H A Dr8a77951.dtsi23 * The external audio clocks are configured as 0 Hz fixed frequency
29 #clock-cells = <0>;
30 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
41 #clock-cells = <0>;
42 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
52 cluster0_opp: opp-table-0 {
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk356x-base.dtsi50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&scmi_clk 0>;
59 i-cache-size = <0x8000>;
62 d-cache-size = <0x8000>;
71 reg = <0x0 0x100>;
74 i-cache-size = <0x8000>;
77 d-cache-size = <0x8000>;
86 reg = <0x0 0x200>;
[all …]