Lines Matching +full:0 +full:xfd800000

41 #define RAM_BASE 0xfd800000 /* RSMEM */
43 #define RAM_BASE 0xe5200000 /* ILRAM */
86 	/* part 0: data area */  in sh_mobile_register_self_refresh()
88 	sdp->addr.stbcr = 0xa4150020; /* STBCR */  in sh_mobile_register_self_refresh()
89 	sdp->addr.bar = 0xa4150040; /* BAR */  in sh_mobile_register_self_refresh()
90 	sdp->addr.pteh = 0xff000000; /* PTEH */  in sh_mobile_register_self_refresh()
91 	sdp->addr.ptel = 0xff000004; /* PTEL */  in sh_mobile_register_self_refresh()
92 	sdp->addr.ttb = 0xff000008; /* TTB */  in sh_mobile_register_self_refresh()
93 	sdp->addr.tea = 0xff00000c; /* TEA */  in sh_mobile_register_self_refresh()
94 	sdp->addr.mmucr = 0xff000010; /* MMUCR */  in sh_mobile_register_self_refresh()
95 	sdp->addr.ptea = 0xff000034; /* PTEA */  in sh_mobile_register_self_refresh()
96 	sdp->addr.pascr = 0xff000070; /* PASCR */  in sh_mobile_register_self_refresh()
97 	sdp->addr.irmcr = 0xff000078; /* IRMCR */  in sh_mobile_register_self_refresh()
98 	sdp->addr.ccr = 0xff00001c; /* CCR */  in sh_mobile_register_self_refresh()
99 	sdp->addr.ramcr = 0xff000074; /* RAMCR */  in sh_mobile_register_self_refresh()
120 	WARN_ON(vp > (onchip_mem + 0x600));  in sh_mobile_register_self_refresh()
121 	vp = onchip_mem + 0x600; /* located at interrupt vector */  in sh_mobile_register_self_refresh()
139 	return 0;  in sh_pm_enter()