Lines Matching +full:0 +full:xfd800000
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&scmi_clk 0>;
59 i-cache-size = <0x8000>;
62 d-cache-size = <0x8000>;
71 reg = <0x0 0x100>;
74 i-cache-size = <0x8000>;
77 d-cache-size = <0x8000>;
86 reg = <0x0 0x200>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
101 reg = <0x0 0x300>;
104 i-cache-size = <0x8000>;
107 d-cache-size = <0x8000>;
122 cache-size = <0x80000>;
135 arm,smc-id = <0x82000010>;
138 #size-cells = <0>;
141 reg = <0x14>;
184 reg = <0x0 0x0010f000 0x0 0x100>;
202 #clock-cells = <0>;
209 pinctrl-0 = <&clk32k_out0>;
211 #clock-cells = <0>;
216 reg = <0 0xfc400000 0 0x1000>;
223 ports-implemented = <0x1>;
230 reg = <0 0xfc800000 0 0x1000>;
237 ports-implemented = <0x1>;
244 reg = <0x0 0xfcc00000 0x0 0x400000>;
260 reg = <0x0 0xfd000000 0x0 0x400000>;
278 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
279 <0x0 0xfd460000 0 0x80000>; /* GICR */
283 mbi-alias = <0x0 0xfd410000>;
293 reg = <0x0 0xfd440000 0 0x20000>;
302 reg = <0x0 0xfd800000 0x0 0x40000>;
313 reg = <0x0 0xfd840000 0x0 0x40000>;
324 reg = <0x0 0xfd880000 0x0 0x40000>;
335 reg = <0x0 0xfd8c0000 0x0 0x40000>;
346 reg = <0x0 0xfdc20000 0x0 0x10000>;
355 reg = <0x0 0xfdc50000 0x0 0x1000>;
360 reg = <0x0 0xfdc60000 0x0 0x10000>;
365 reg = <0x0 0xfdc80000 0x0 0x1000>;
370 reg = <0x0 0xfdc90000 0x0 0x1000>;
375 reg = <0x0 0xfdca0000 0x0 0x8000>;
380 reg = <0x0 0xfdca8000 0x0 0x8000>;
385 reg = <0x0 0xfdd00000 0x0 0x1000>;
392 reg = <0x0 0xfdd20000 0x0 0x1000>;
405 reg = <0x0 0xfdd40000 0x0 0x1000>;
409 pinctrl-0 = <&i2c0_xfer>;
412 #size-cells = <0>;
418 reg = <0x0 0xfdd50000 0x0 0x100>;
422 dmas = <&dmac0 0>, <&dmac0 1>;
423 pinctrl-0 = <&uart0_xfer>;
432 reg = <0x0 0xfdd70000 0x0 0x10>;
435 pinctrl-0 = <&pwm0m0_pins>;
443 reg = <0x0 0xfdd70010 0x0 0x10>;
446 pinctrl-0 = <&pwm1m0_pins>;
454 reg = <0x0 0xfdd70020 0x0 0x10>;
457 pinctrl-0 = <&pwm2m0_pins>;
465 reg = <0x0 0xfdd70030 0x0 0x10>;
468 pinctrl-0 = <&pwm3_pins>;
476 reg = <0x0 0xfdd90000 0x0 0x1000>;
482 #size-cells = <0>;
490 #power-domain-cells = <0>;
501 #power-domain-cells = <0>;
512 #power-domain-cells = <0>;
525 #power-domain-cells = <0>;
532 #power-domain-cells = <0>;
539 #power-domain-cells = <0>;
548 #power-domain-cells = <0>;
555 reg = <0x0 0xfde60000 0x0 0x4000>;
569 reg = <0x0 0xfdea0000 0x0 0x800>;
580 reg = <0x0 0xfdea0800 0x0 0x40>;
585 #iommu-cells = <0>;
590 reg = <0x0 0xfdeb0000 0x0 0x180>;
601 reg = <0x0 0xfdee0000 0x0 0x800>;
611 reg = <0x0 0xfdee0800 0x0 0x40>;
616 #iommu-cells = <0>;
621 reg = <0x0 0xfe000000 0x0 0x4000>;
626 fifo-depth = <0x100>;
635 reg = <0x0 0xfe010000 0x0 0x10000>;
659 #address-cells = <0x1>;
660 #size-cells = <0x0>;
664 snps,blen = <0 0 0 0 16 8 4>;
681 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
694 #size-cells = <0>;
696 vp0: port@0 {
697 reg = <0>;
699 #size-cells = <0>;
705 #size-cells = <0>;
711 #size-cells = <0>;
718 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
722 #iommu-cells = <0>;
729 reg = <0x00 0xfe060000 0x00 0x10000>;
743 #size-cells = <0>;
745 dsi0_in: port@0 {
746 reg = <0>;
757 reg = <0x0 0xfe070000 0x0 0x10000>;
771 #size-cells = <0>;
773 dsi1_in: port@0 {
774 reg = <0>;
785 reg = <0x0 0xfe0a0000 0x0 0x20000>;
794 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
798 #sound-dai-cells = <0>;
803 #size-cells = <0>;
805 hdmi_in: port@0 {
806 reg = <0>;
817 reg = <0x0 0xfe128000 0x0 0x20>;
822 reg = <0x0 0xfe138080 0x0 0x20>;
827 reg = <0x0 0xfe138100 0x0 0x20>;
832 reg = <0x0 0xfe138180 0x0 0x20>;
837 reg = <0x0 0xfe148000 0x0 0x20>;
842 reg = <0x0 0xfe148080 0x0 0x20>;
847 reg = <0x0 0xfe148100 0x0 0x20>;
852 reg = <0x0 0xfe150000 0x0 0x20>;
857 reg = <0x0 0xfe158000 0x0 0x20>;
862 reg = <0x0 0xfe158100 0x0 0x20>;
867 reg = <0x0 0xfe158180 0x0 0x20>;
872 reg = <0x0 0xfe158200 0x0 0x20>;
877 reg = <0x0 0xfe158280 0x0 0x20>;
882 reg = <0x0 0xfe158300 0x0 0x20>;
887 reg = <0x0 0xfe180000 0x0 0x20>;
892 reg = <0x0 0xfe190000 0x0 0x20>;
897 reg = <0x0 0xfe190280 0x0 0x20>;
902 reg = <0x0 0xfe190300 0x0 0x20>;
907 reg = <0x0 0xfe190380 0x0 0x20>;
912 reg = <0x0 0xfe190400 0x0 0x20>;
917 reg = <0x0 0xfe198000 0x0 0x20>;
922 reg = <0x0 0xfe1a8000 0x0 0x20>;
927 reg = <0x0 0xfe1a8080 0x0 0x20>;
932 reg = <0x0 0xfe1a8100 0x0 0x20>;
937 reg = <0x00 0xfe230000 0x00 0x400>;
944 reg = <0x3 0xc0000000 0x0 0x00400000>,
945 <0x0 0xfe260000 0x0 0x00010000>,
946 <0x0 0xf4000000 0x0 0x00100000>;
954 bus-range = <0x0 0xf>;
962 interrupt-map-mask = <0 0 0 7>;
963 interrupt-map = <0 0 0 1 &pcie_intc 0>,
964 <0 0 0 2 &pcie_intc 1>,
965 <0 0 0 3 &pcie_intc 2>,
966 <0 0 0 4 &pcie_intc 3>;
967 linux,pci-domain = <0>;
971 msi-map = <0x0 &its 0x0 0x1000>;
976 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
977 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
978 <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
986 #address-cells = <0>;
996 reg = <0x0 0xfe2b0000 0x0 0x4000>;
1001 fifo-depth = <0x100>;
1010 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1015 fifo-depth = <0x100>;
1024 reg = <0x0 0xfe300000 0x0 0x4000>;
1028 pinctrl-0 = <&fspi_pins>;
1035 reg = <0x0 0xfe310000 0x0 0x10000>;
1053 reg = <0x0 0xfe388000 0x0 0x4000>;
1062 reg = <0x0 0xfe400000 0x0 0x1000>;
1068 dmas = <&dmac1 0>;
1073 #sound-dai-cells = <0>;
1079 reg = <0x0 0xfe410000 0x0 0x1000>;
1092 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
1098 #sound-dai-cells = <0>;
1104 reg = <0x0 0xfe420000 0x0 0x1000>;
1116 pinctrl-0 = <&i2s2m0_sclktx
1120 #sound-dai-cells = <0>;
1126 reg = <0x0 0xfe430000 0x0 0x1000>;
1136 #sound-dai-cells = <0>;
1142 reg = <0x0 0xfe440000 0x0 0x1000>;
1148 pinctrl-0 = <&pdmm0_clk
1157 #sound-dai-cells = <0>;
1163 reg = <0x0 0xfe460000 0x0 0x1000>;
1170 pinctrl-0 = <&spdifm0_tx>;
1171 #sound-dai-cells = <0>;
1177 reg = <0x0 0xfe530000 0x0 0x4000>;
1188 reg = <0x0 0xfe550000 0x0 0x4000>;
1199 reg = <0x0 0xfe5a0000 0x0 0x1000>;
1203 pinctrl-0 = <&i2c1_xfer>;
1206 #size-cells = <0>;
1212 reg = <0x0 0xfe5b0000 0x0 0x1000>;
1216 pinctrl-0 = <&i2c2m0_xfer>;
1219 #size-cells = <0>;
1225 reg = <0x0 0xfe5c0000 0x0 0x1000>;
1229 pinctrl-0 = <&i2c3m0_xfer>;
1232 #size-cells = <0>;
1238 reg = <0x0 0xfe5d0000 0x0 0x1000>;
1242 pinctrl-0 = <&i2c4m0_xfer>;
1245 #size-cells = <0>;
1251 reg = <0x0 0xfe5e0000 0x0 0x1000>;
1255 pinctrl-0 = <&i2c5m0_xfer>;
1258 #size-cells = <0>;
1264 reg = <0x0 0xfe600000 0x0 0x100>;
1272 reg = <0x0 0xfe610000 0x0 0x1000>;
1279 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1281 #size-cells = <0>;
1287 reg = <0x0 0xfe620000 0x0 0x1000>;
1294 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1296 #size-cells = <0>;
1302 reg = <0x0 0xfe630000 0x0 0x1000>;
1309 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1311 #size-cells = <0>;
1317 reg = <0x0 0xfe640000 0x0 0x1000>;
1324 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
1326 #size-cells = <0>;
1332 reg = <0x0 0xfe650000 0x0 0x100>;
1337 pinctrl-0 = <&uart1m0_xfer>;
1346 reg = <0x0 0xfe660000 0x0 0x100>;
1351 pinctrl-0 = <&uart2m0_xfer>;
1360 reg = <0x0 0xfe670000 0x0 0x100>;
1365 pinctrl-0 = <&uart3m0_xfer>;
1374 reg = <0x0 0xfe680000 0x0 0x100>;
1379 pinctrl-0 = <&uart4m0_xfer>;
1388 reg = <0x0 0xfe690000 0x0 0x100>;
1393 pinctrl-0 = <&uart5m0_xfer>;
1402 reg = <0x0 0xfe6a0000 0x0 0x100>;
1407 pinctrl-0 = <&uart6m0_xfer>;
1416 reg = <0x0 0xfe6b0000 0x0 0x100>;
1421 pinctrl-0 = <&uart7m0_xfer>;
1430 reg = <0x0 0xfe6c0000 0x0 0x100>;
1435 pinctrl-0 = <&uart8m0_xfer>;
1444 reg = <0x0 0xfe6d0000 0x0 0x100>;
1449 pinctrl-0 = <&uart9m0_xfer>;
1461 thermal-sensors = <&tsadc 0>;
1529 reg = <0x0 0xfe710000 0x0 0x100>;
1540 pinctrl-0 = <&tsadc_shutorg>;
1548 reg = <0x0 0xfe720000 0x0 0x100>;
1560 reg = <0x0 0xfe6e0000 0x0 0x10>;
1563 pinctrl-0 = <&pwm4_pins>;
1571 reg = <0x0 0xfe6e0010 0x0 0x10>;
1574 pinctrl-0 = <&pwm5_pins>;
1582 reg = <0x0 0xfe6e0020 0x0 0x10>;
1585 pinctrl-0 = <&pwm6_pins>;
1593 reg = <0x0 0xfe6e0030 0x0 0x10>;
1596 pinctrl-0 = <&pwm7_pins>;
1604 reg = <0x0 0xfe6f0000 0x0 0x10>;
1607 pinctrl-0 = <&pwm8m0_pins>;
1615 reg = <0x0 0xfe6f0010 0x0 0x10>;
1618 pinctrl-0 = <&pwm9m0_pins>;
1626 reg = <0x0 0xfe6f0020 0x0 0x10>;
1629 pinctrl-0 = <&pwm10m0_pins>;
1637 reg = <0x0 0xfe6f0030 0x0 0x10>;
1640 pinctrl-0 = <&pwm11m0_pins>;
1648 reg = <0x0 0xfe700000 0x0 0x10>;
1651 pinctrl-0 = <&pwm12m0_pins>;
1659 reg = <0x0 0xfe700010 0x0 0x10>;
1662 pinctrl-0 = <&pwm13m0_pins>;
1670 reg = <0x0 0xfe700020 0x0 0x10>;
1673 pinctrl-0 = <&pwm14m0_pins>;
1681 reg = <0x0 0xfe700030 0x0 0x10>;
1684 pinctrl-0 = <&pwm15m0_pins>;
1692 reg = <0x0 0xfe830000 0x0 0x100>;
1709 reg = <0x0 0xfe840000 0x0 0x100>;
1726 reg = <0x0 0xfe870000 0x0 0x10000>;
1729 #phy-cells = <0>;
1738 reg = <0x0 0xfe850000 0x0 0x10000>;
1741 #phy-cells = <0>;
1750 reg = <0x0 0xfe860000 0x0 0x10000>;
1753 #phy-cells = <0>;
1762 reg = <0x0 0xfe8a0000 0x0 0x10000>;
1768 #clock-cells = <0>;
1772 #phy-cells = <0>;
1777 #phy-cells = <0>;
1784 reg = <0x0 0xfe8b0000 0x0 0x10000>;
1790 #clock-cells = <0>;
1794 #phy-cells = <0>;
1799 #phy-cells = <0>;
1814 reg = <0x0 0xfdd60000 0x0 0x100>;
1818 gpio-ranges = <&pinctrl 0 0 32>;
1826 reg = <0x0 0xfe740000 0x0 0x100>;
1830 gpio-ranges = <&pinctrl 0 32 32>;
1838 reg = <0x0 0xfe750000 0x0 0x100>;
1842 gpio-ranges = <&pinctrl 0 64 32>;
1850 reg = <0x0 0xfe760000 0x0 0x100>;
1854 gpio-ranges = <&pinctrl 0 96 32>;
1862 reg = <0x0 0xfe770000 0x0 0x100>;
1866 gpio-ranges = <&pinctrl 0 128 32>;