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/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
H A Dphy.c29 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
41 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
62 {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
63 {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
64 {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
65 {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
66 {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
70 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
71 {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
72 {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
[all …]
/linux/drivers/dma/
H A Dste_dma40_ll.h10 #define D40_DREG_PCBASE 0x400
35 #define D40_SREG_CFG_PHY_EVTL_POS 0
40 #define D40_SREG_ELEM_PHY_EIDX_POS 0
42 #define D40_SREG_ELEM_PHY_ECNT_MASK (0xFFFF << D40_SREG_ELEM_PHY_ECNT_POS)
45 #define D40_SREG_LNK_PHY_TCP_POS 0
52 #define D40_SREG_LNK_PHYS_LNK_MASK 0xFFFFFFF8UL
60 #define D40_SREG_ELEM_LOG_TCP_POS 0
62 #define D40_SREG_ELEM_LOG_LIDX_MASK (0xFF << D40_SREG_ELEM_LOG_LIDX_POS)
66 #define D40_EVENTLINE_MASK(i) (0x3 << D40_EVENTLINE_POS(i))
72 #define D40_MEM_LCSP0_SPTR_POS 0
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dphy.c38 u32 original_value = 0, readback_value, bitshift; in rtl8723e_phy_query_rf_reg()
70 u32 original_value = 0, bitshift; in rtl8723e_phy_set_rf_reg()
117 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2); in _rtl8723e_phy_bb_config_1t()
118 rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022); in _rtl8723e_phy_bb_config_1t()
119 rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45); in _rtl8723e_phy_bb_config_1t()
120 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23); in _rtl8723e_phy_bb_config_1t()
121 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1); in _rtl8723e_phy_bb_config_1t()
122 rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2); in _rtl8723e_phy_bb_config_1t()
123 rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2); in _rtl8723e_phy_bb_config_1t()
124 rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2); in _rtl8723e_phy_bb_config_1t()
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192c/
H A Dphy_common.c24 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", in rtl92c_phy_query_bb_reg()
59 return 0; in _rtl92c_phy_fw_rf_serial_read()
79 u8 rfpi_enable = 0; in _rtl92c_phy_rf_serial_read()
82 offset &= 0x3f; in _rtl92c_phy_rf_serial_read()
86 return 0xFFFFFFFF; in _rtl92c_phy_rf_serial_read()
115 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n", in _rtl92c_phy_rf_serial_read()
136 offset &= 0x3f; in _rtl92c_phy_rf_serial_write()
138 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; in _rtl92c_phy_rf_serial_write()
140 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", in _rtl92c_phy_rf_serial_write()
148 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2); in _rtl92c_phy_bb_config_1t()
[all …]
/linux/drivers/staging/media/starfive/camss/
H A Dstf-isp.h19 #define STF_ISP_REG_OFFSET_MAX 0x0fff
23 #define ISP_REG_CSI_INPUT_EN_AND_STATUS 0x000
29 #define CSI_EN_S BIT(0)
31 #define ISP_REG_CSIINTS 0x008
33 #define CSI_SHA_M(n) ((n) << 0)
36 #define ISP_REG_CSI_MODULE_CFG 0x010
48 #define CSI_DC_EN BIT(0)
50 #define ISP_REG_SENSOR 0x014
53 #define IMAGER_SEL(n) ((n) << 0)
55 #define ISP_REG_RAW_FORMAT_CFG 0x018
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
H A Dphy.c52 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask, in rtl88e_phy_query_bb_reg()
148 u8 rfpi_enable = 0; in _rtl88e_phy_rf_serial_read()
151 offset &= 0xff; in _rtl88e_phy_rf_serial_read()
155 return 0xFFFFFFFF; in _rtl88e_phy_rf_serial_read()
182 "RFR-%d Addr[0x%x]=0x%x\n", in _rtl88e_phy_rf_serial_read()
201 offset &= 0xff; in _rtl88e_phy_rf_serial_write()
203 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; in _rtl88e_phy_rf_serial_write()
206 "RFW-%d Addr[0x%x]=0x%x\n", in _rtl88e_phy_rf_serial_write()
215 rtl_write_byte(rtlpriv, 0x04CA, 0x0B); in rtl88e_phy_mac_config()
229 regval | BIT(13) | BIT(0) | BIT(1)); in rtl88e_phy_bb_config()
[all …]
H A Dreg.h7 #define TXPKT_BUF_SELECT 0x69
8 #define RXPKT_BUF_SELECT 0xA5
9 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
11 #define REG_SYS_ISO_CTRL 0x0000
12 #define REG_SYS_FUNC_EN 0x0002
13 #define REG_APS_FSMCO 0x0004
14 #define REG_SYS_CLKR 0x0008
15 #define REG_9346CR 0x000A
16 #define REG_EE_VPD 0x000C
17 #define REG_AFE_MISC 0x0010
[all …]
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_wed_regs.h8 #define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(14, 0)
9 #define MTK_WDMA_DESC_CTRL_LEN1_V2 GENMASK(13, 0)
26 #define MTK_WED_REV_ID 0x004
28 #define MTK_WED_RESET 0x008
29 #define MTK_WED_RESET_TX_BM BIT(0)
48 #define MTK_WED_CTRL 0x00c
49 #define MTK_WED_CTRL_WPDMA_INT_AGENT_EN BIT(0)
75 #define MTK_WED_EXT_INT_STATUS 0x020
76 #define MTK_WED_EXT_INT_STATUS_TF_LEN_ERR BIT(0)
103 #define MTK_WED_EXT_INT_MASK 0x028
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dreg.h7 #define TXPKT_BUF_SELECT 0x69
8 #define RXPKT_BUF_SELECT 0xA5
9 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
11 #define REG_SYS_ISO_CTRL 0x0000
12 #define REG_SYS_FUNC_EN 0x0002
13 #define REG_APS_FSMCO 0x0004
14 #define REG_SYS_CLKR 0x0008
15 #define REG_9346CR 0x000A
16 #define REG_EE_VPD 0x000C
17 #define REG_AFE_MISC 0x0010
[all …]
H A Dtable.c7 0x800, 0x8020D010,
8 0x804, 0x080112E0,
9 0x808, 0x0E028233,
10 0x80C, 0x12131113,
11 0x810, 0x20101263,
12 0x814, 0x020C3D10,
13 0x818, 0x03A00385,
14 0x820, 0x00000000,
15 0x824, 0x00030FE0,
16 0x828, 0x00000000,
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192d/
H A Dphy_common.c29 u8 rfpi_enable = 0; in _rtl92d_phy_rf_serial_read()
60 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n", in _rtl92d_phy_rf_serial_read()
77 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; in _rtl92d_phy_rf_serial_write()
79 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", in _rtl92d_phy_rf_serial_write()
114 if (bitmask == 0) in rtl92d_phy_set_rf_reg()
141 /* 16 LSBs if read 32-bit from 0x870 */ in rtl92d_phy_init_bb_rf_register_definition()
143 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ in rtl92d_phy_init_bb_rf_register_definition()
145 /* 16 LSBs if read 32-bit from 0x874 */ in rtl92d_phy_init_bb_rf_register_definition()
147 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ in rtl92d_phy_init_bb_rf_register_definition()
151 /* 16 LSBs if read 32-bit from 0x8E0 */ in rtl92d_phy_init_bb_rf_register_definition()
[all …]
H A Ddm_common.c13 0x7f8001fe, /* 0, +6.0dB */
14 0x788001e2, /* 1, +5.5dB */
15 0x71c001c7, /* 2, +5.0dB */
16 0x6b8001ae, /* 3, +4.5dB */
17 0x65400195, /* 4, +4.0dB */
18 0x5fc0017f, /* 5, +3.5dB */
19 0x5a400169, /* 6, +3.0dB */
20 0x55400155, /* 7, +2.5dB */
21 0x50800142, /* 8, +2.0dB */
22 0x4c000130, /* 9, +1.5dB */
[all …]
H A Dreg.h8 /* 0x0000h ~ 0x00FFh System Configuration */
10 #define REG_SYS_ISO_CTRL 0x0000
11 #define REG_SYS_FUNC_EN 0x0002
12 #define REG_APS_FSMCO 0x0004
13 #define REG_SYS_CLKR 0x0008
14 #define REG_9346CR 0x000A
15 #define REG_EE_VPD 0x000C
16 #define REG_AFE_MISC 0x0010
17 #define REG_SPS0_CTRL 0x0011
18 #define REG_POWER_OFF_IN_PROCESS 0x0017
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192du/
H A Dphy.c27 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
39 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
61 {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
62 {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
63 {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
64 {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
65 {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
69 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
70 {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
71 {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Dreg.h7 #define TXPKT_BUF_SELECT 0x69
8 #define RXPKT_BUF_SELECT 0xA5
9 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
11 #define REG_SYS_ISO_CTRL 0x0000
12 #define REG_SYS_FUNC_EN 0x0002
13 #define REG_APS_FSMCO 0x0004
14 #define REG_SYS_CLKR 0x0008
15 #define REG_9346CR 0x000A
16 #define REG_EE_VPD 0x000C
17 #define REG_SYS_SWR_CTRL1 0x0010
[all …]
H A Dphy.c52 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", in rtl92ee_phy_query_bb_reg()
142 u8 rfpi_enable = 0; in _rtl92ee_phy_rf_serial_read()
145 offset &= 0xff; in _rtl92ee_phy_rf_serial_read()
149 return 0xFFFFFFFF; in _rtl92ee_phy_rf_serial_read()
175 "RFR-%d Addr[0x%x]=0x%x\n", in _rtl92ee_phy_rf_serial_read()
194 offset &= 0xff; in _rtl92ee_phy_rf_serial_write()
196 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; in _rtl92ee_phy_rf_serial_write()
199 "RFW-%d Addr[0x%x]=0x%x\n", rfpath, in _rtl92ee_phy_rf_serial_write()
219 regval | BIT(13) | BIT(0) | BIT(1)); in rtl92ee_phy_bb_config()
226 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); in rtl92ee_phy_bb_config()
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
H A Dreg.h7 #define TXPKT_BUF_SELECT 0x69
8 #define RXPKT_BUF_SELECT 0xA5
9 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
11 #define REG_SYS_ISO_CTRL 0x0000
12 #define REG_SYS_FUNC_EN 0x0002
13 #define REG_APS_FSMCO 0x0004
14 #define REG_SYS_CLKR 0x0008
15 #define REG_9346CR 0x000A
16 #define REG_EE_VPD 0x000C
17 #define REG_AFE_MISC 0x0010
[all …]
/linux/arch/x86/events/intel/
H A Duncore_snbep.c8 #define SNBEP_CPUNODEID 0x40
9 #define SNBEP_GIDNIDMAP 0x54
12 #define SNBEP_PMON_BOX_CTL_RST_CTRL (1 << 0)
20 #define SNBEP_PMON_CTL_EV_SEL_MASK 0x000000ff
21 #define SNBEP_PMON_CTL_UMASK_MASK 0x0000ff00
27 #define SNBEP_PMON_CTL_TRESH_MASK 0xff000000
35 #define SNBEP_U_MSR_PMON_CTL_TRESH_MASK 0x1f000000
48 #define SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK 0x0000c000
49 #define SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK 0x1f000000
66 #define SNBEP_PCI_PMON_BOX_CTL 0xf4
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8821c_table.c10 0x010, 0x00000043,
11 0x025, 0x0000001D,
12 0x026, 0x000000CE,
13 0x04F, 0x00000001,
14 0x029, 0x000000F9,
15 0x420, 0x00000080,
16 0x421, 0x0000001F,
17 0x428, 0x0000000A,
18 0x429, 0x00000010,
19 0x430, 0x00000000,
[all …]
H A Drtw8822b_table.c10 0x029, 0x000000F9,
11 0x420, 0x00000080,
12 0x421, 0x0000001F,
13 0x428, 0x0000000A,
14 0x429, 0x00000010,
15 0x430, 0x00000000,
16 0x431, 0x00000000,
17 0x432, 0x00000000,
18 0x433, 0x00000001,
19 0x434, 0x00000004,
[all …]