29 	u8 rfpi_enable = 0;  in _rtl92d_phy_rf_serial_read()
60 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n",  in _rtl92d_phy_rf_serial_read()
77 	data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;  in _rtl92d_phy_rf_serial_write()
79 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",  in _rtl92d_phy_rf_serial_write()
114 	if (bitmask == 0)  in rtl92d_phy_set_rf_reg()
141 	/* 16 LSBs if read 32-bit from 0x870 */  in rtl92d_phy_init_bb_rf_register_definition()
143 	/* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */  in rtl92d_phy_init_bb_rf_register_definition()
145 	/* 16 LSBs if read 32-bit from 0x874 */  in rtl92d_phy_init_bb_rf_register_definition()
147 	/* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */  in rtl92d_phy_init_bb_rf_register_definition()
151 	/* 16 LSBs if read 32-bit from 0x8E0 */  in rtl92d_phy_init_bb_rf_register_definition()
153 	/* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */  in rtl92d_phy_init_bb_rf_register_definition()
155 	/* 16 LSBs if read 32-bit from 0x8E4 */  in rtl92d_phy_init_bb_rf_register_definition()
157 	/* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */  in rtl92d_phy_init_bb_rf_register_definition()
161 	/* 16 LSBs if read 32-bit from 0x860 */  in rtl92d_phy_init_bb_rf_register_definition()
163 	/* 16 LSBs if read 32-bit from 0x864 */  in rtl92d_phy_init_bb_rf_register_definition()
167 	/* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */  in rtl92d_phy_init_bb_rf_register_definition()
169 	/* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */  in rtl92d_phy_init_bb_rf_register_definition()
271 		index = 0;  in rtl92d_store_pwrindex_diffrate_offset()
276 	else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)  in rtl92d_store_pwrindex_diffrate_offset()
292 	else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)  in rtl92d_store_pwrindex_diffrate_offset()
307 		"MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",  in rtl92d_store_pwrindex_diffrate_offset()
320 	rtlphy->default_initialgain[0] =  in rtl92d_phy_get_hw_reg_originalvalue()
329 		"Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",  in rtl92d_phy_get_hw_reg_originalvalue()
330 		rtlphy->default_initialgain[0],  in rtl92d_phy_get_hw_reg_originalvalue()
337 		"Default framesync (0x%x) = 0x%x\n",  in rtl92d_phy_get_hw_reg_originalvalue()
360 		cckpowerlevel[RF90_PATH_A] = 0;  in _rtl92d_get_txpower_index()
361 		cckpowerlevel[RF90_PATH_B] = 0;  in _rtl92d_get_txpower_index()
386 	rtlphy->cur_cck_txpwridx = cckpowerlevel[0];  in _rtl92d_ccxpower_index_check()
387 	rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];  in _rtl92d_ccxpower_index_check()
414 	_rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0],  in rtl92d_phy_set_txpower_level()
415 				  &ofdmpowerlevel[0]);  in rtl92d_phy_set_txpower_level()
417 		_rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0],  in rtl92d_phy_set_txpower_level()
418 					     &ofdmpowerlevel[0]);  in rtl92d_phy_set_txpower_level()
420 		rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);  in rtl92d_phy_set_txpower_level()
421 	rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);  in rtl92d_phy_set_txpower_level()
446 	rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);  in rtl92d_phy_enable_rf_env()
449 	rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);  in rtl92d_phy_enable_rf_env()
453 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0);  in rtl92d_phy_enable_rf_env()
455 	/*Set 0 to 12 bits for 8255 */  in rtl92d_phy_enable_rf_env()
456 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);  in rtl92d_phy_enable_rf_env()
497 	return 0;  in rtl92d_get_rightchnlplace_for_iqk()
508 	for (i = 0; i < regnum; i++)  in rtl92d_phy_save_adda_registers()
520 	for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)  in rtl92d_phy_save_mac_registers()
534 	pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4;  in rtl92d_phy_path_adda_on()
536 		pathon = rtlpriv->rtlhal.interfaceindex == 0 ?  in rtl92d_phy_path_adda_on()
537 		    0x04db25a4 : 0x0b1b25a4;  in rtl92d_phy_path_adda_on()
538 	for (i = 0; i < IQK_ADDA_REG_NUM; i++)  in rtl92d_phy_path_adda_on()
550 	rtl_write_byte(rtlpriv, macreg[0], 0x3F);  in rtl92d_phy_mac_setting_calibration()
574 	for (i = 0; i < ARRAY_SIZE(channel5g); i++)  in _rtl92d_is_legal_5g_channel()
585 	u32 smallest_abs_val = 0xffffffff, u4tmp;  in rtl92d_phy_calc_curvindex()
589 	for (i = 0; i < chnl_num; i++) {  in rtl92d_phy_calc_curvindex()
592 		curveindex[i] = 0;  in rtl92d_phy_calc_curvindex()
593 		for (j = 0; j < (CV_CURVE_CNT * 2); j++) {  in rtl92d_phy_calc_curvindex()
602 		smallest_abs_val = 0xffffffff;  in rtl92d_phy_calc_curvindex()
619 	/* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */  in rtl92d_phy_reset_iqk_result()
620 	for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {  in rtl92d_phy_reset_iqk_result()
621 		rtlphy->iqk_matrix[i].value[0][0] = 0x100;  in rtl92d_phy_reset_iqk_result()
622 		rtlphy->iqk_matrix[i].value[0][2] = 0x100;  in rtl92d_phy_reset_iqk_result()
623 		rtlphy->iqk_matrix[i].value[0][4] = 0x100;  in rtl92d_phy_reset_iqk_result()
624 		rtlphy->iqk_matrix[i].value[0][6] = 0x100;  in rtl92d_phy_reset_iqk_result()
625 		rtlphy->iqk_matrix[i].value[0][1] = 0x0;  in rtl92d_phy_reset_iqk_result()
626 		rtlphy->iqk_matrix[i].value[0][3] = 0x0;  in rtl92d_phy_reset_iqk_result()
627 		rtlphy->iqk_matrix[i].value[0][5] = 0x0;  in rtl92d_phy_reset_iqk_result()
628 		rtlphy->iqk_matrix[i].value[0][7] = 0x0;  in rtl92d_phy_reset_iqk_result()
652 		de_digtable->cur_igvalue = 0x37;  in rtl92d_phy_set_io()
654 			de_digtable->cur_igvalue = 0x17;  in rtl92d_phy_set_io()
715 	u8 phy_ctrl = 0xf0;  in rtl92d_phy_config_macphymode()
719 		phy_ctrl &= ~(BIT(0) | BIT(1) | BIT(2));  in rtl92d_phy_config_macphymode()
726 		rtl_write_byte(rtlpriv, offset, phy_ctrl | BIT(0) | BIT(1));  in rtl92d_phy_config_macphymode()
736 		rtl_write_byte(rtlpriv, offset, phy_ctrl | BIT(0));  in rtl92d_phy_config_macphymode()
767 		if (rtlhal->interfaceindex == 0) {  in rtl92d_phy_config_macphymode_info()
786 		group = 0;  in rtl92d_get_chnlgroup_fromarray()
818 		group = 0;  in rtl92d_phy_get_chnlgroup_bypg()
838 		rtl_write_byte(rtlpriv, REG_DMC, 0x0);  in rtl92d_phy_config_maccoexist_rfpage()
839 		rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);  in rtl92d_phy_config_maccoexist_rfpage()
840 		rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);  in rtl92d_phy_config_maccoexist_rfpage()
843 		rtl_write_byte(rtlpriv, REG_DMC, 0xf8);  in rtl92d_phy_config_maccoexist_rfpage()
844 		rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);  in rtl92d_phy_config_maccoexist_rfpage()
845 		rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);  in rtl92d_phy_config_maccoexist_rfpage()
848 		rtl_write_byte(rtlpriv, REG_DMC, 0x0);  in rtl92d_phy_config_maccoexist_rfpage()
849 		rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10);  in rtl92d_phy_config_maccoexist_rfpage()
850 		rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);  in rtl92d_phy_config_maccoexist_rfpage()