Lines Matching +full:0 +full:xeb4
27 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
39 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
61 {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
62 {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
63 {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
64 {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
65 {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
69 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
70 {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
71 {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
74 static const u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF;
77 {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
78 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
79 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}
86 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0,
87 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff
91 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000,
92 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090,
93 0x32c9a
97 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000,
98 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a
174 "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
242 for (i = 0; i < arraylength; i = i + 2)
247 /* rtl_write_byte(rtlpriv, 0x14,0x71); */
250 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B);
253 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07);
263 u16 phy_reg_arraylen, agctab_arraylen = 0;
269 if (rtlhal->interfaceindex == 0) {
293 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
299 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
304 for (i = 0; i < agctab_arraylen; i = i + 2) {
333 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
362 rtlphy->pwrgroup_cnt = 0;
378 0x200);
396 regval | BIT(13) | BIT(0) | BIT(1));
398 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
399 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
401 /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */
418 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
419 rtl_write_byte(rtlpriv, 0x15, 0xe9);
421 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
431 rtl_set_bbreg(hw, REG_AFE_XTAL_CTRL, 0xf0,
432 rtlpriv->efuse.crystalcap & 0x0f);
433 rtl_set_bbreg(hw, REG_AFE_PLL_CTRL, 0xf0000000,
434 (rtlpriv->efuse.crystalcap & 0xf0) >> 4);
458 if (rtlpriv->efuse.internal_pa_5g[0]) {
473 * mac1 start on 5G, mac 0 has to set phy0 & phy1
485 for (i = 0; i < radioa_arraylen; i = i + 2) {
492 for (i = 0; i < radiob_arraylen; i = i + 2) {
544 reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
556 rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
557 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
562 rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
563 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
570 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
573 BIT(10) | BIT(11), 0);
574 rtl_set_bbreg(hw, 0x818, BIT(26) | BIT(27),
592 rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BCCKEN | BOFDMEN, 0);
593 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00);
594 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0);
633 rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BCCKEN | BOFDMEN, 0x3);
639 reg_mac = rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1;
641 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */
669 BOFDMEN | BCCKEN, 0);
670 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
672 /* fc area 0xd2c */
680 /* leave 0 for channel1-14. */
682 for (i = 0; i < MAX_RF_IMR_INDEX_NORMAL; i++)
688 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
703 BOFDMEN | BCCKEN, 0);
705 0x00f00000, 0xf);
707 for (i = 0; i < MAX_RF_IMR_INDEX_NORMAL; i++) {
711 rf_imr_param_normal[0][i]);
715 0x00f00000, 0);
731 u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2;
733 u32 regb30 = rtl_get_bbreg(hw, 0xb30, BIT(27));
734 u8 index = 0, i, rfpath;
745 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp);
747 for (i = 0; i < RF_CHNL_NUM_5G; i++) {
749 index = 0;
751 for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) {
774 if (regb30 && rtlhal->interfaceindex == 0) {
782 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) {
783 if (i == 0 && rtlhal->macphymode == DUALMAC_DUALPHY) {
786 RFREG_OFFSET_MASK, 0xE439D);
789 0x7FF) | (u4tmp << 11);
802 "offset 0x%x value 0x%x path %d index %d readback 0x%x\n",
818 if (regb30 && rtlhal->interfaceindex == 0) {
826 value = 0x07;
828 value = 0x02;
830 index = 0;
846 for (i = 0;
849 if (rf_for_c_cut_5g_internal_pa[i] == 0x03 &&
854 0x7bdef);
861 "offset 0x%x value 0x%x path %d index %d\n",
875 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
880 index = 0;
888 if (rtlhal->interfaceindex == 0) {
910 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) {
925 "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n",
934 "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
942 rtlhal->interfaceindex == 0) {
965 u8 result = 0;
969 if (rtlhal->interfaceindex == 0) {
970 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c1f);
971 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c1f);
973 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c22);
974 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c22);
976 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140102);
978 configpathb ? 0x28160202 : 0x28160502);
981 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x10008c22);
982 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x10008c22);
983 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82140102);
984 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160206);
989 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);
993 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
994 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1003 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1005 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94);
1007 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c);
1009 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4);
1012 (((rege94 & 0x03FF0000) >> 16) != 0x142) &&
1013 (((rege9c & 0x03FF0000) >> 16) != 0x42))
1014 result |= 0x01;
1020 (((regea4 & 0x03FF0000) >> 16) != 0x132) &&
1021 (((regeac & 0x03FF0000) >> 16) != 0x36))
1022 result |= 0x02;
1038 u8 timeout = 20, timecount = 0;
1040 u8 result = 0;
1049 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1f);
1050 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1f);
1051 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140307);
1052 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160960);
1055 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c2f);
1056 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c2f);
1057 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);
1058 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68110000);
1063 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);
1066 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60);
1067 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30);
1069 for (i = 0; i < retrycount; i++) {
1073 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1074 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1082 rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, BIT(26)) == 0) {
1087 timecount = 0;
1089 rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASK_IQK_RESULT) == 0) {
1096 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1098 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94);
1100 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c);
1102 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4);
1105 (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
1106 result |= 0x01;
1115 (((regea4 & 0x03FF0000) >> 16) != 0x132)) {
1116 result |= 0x02;
1124 rtlphy->iqk_bb_backup[0]);
1128 if (!(result & 0x01)) /* Tx IQK fail */
1129 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x19008c00);
1131 if (!(result & 0x02)) { /* Rx IQK fail */
1132 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100);
1133 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x19008c00);
1136 "Path A Rx IQK fail!! 0xe34 = %#x\n",
1148 u8 result = 0;
1151 rtl_set_bbreg(hw, RIQK_AGC_CONT, MASKDWORD, 0x00000002);
1152 rtl_set_bbreg(hw, RIQK_AGC_CONT, MASKDWORD, 0x00000000);
1160 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1162 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4);
1164 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc);
1166 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4);
1168 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc);
1171 (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
1172 (((regebc & 0x03FF0000) >> 16) != 0x42))
1173 result |= 0x01;
1178 (((regec4 & 0x03FF0000) >> 16) != 0x132) &&
1179 (((regecc & 0x03FF0000) >> 16) != 0x36))
1180 result |= 0x02;
1193 u8 timeout = 20, timecount = 0;
1195 u8 result = 0;
1199 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1f);
1200 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1f);
1201 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000);
1202 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68110000);
1205 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c2f);
1206 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c2f);
1207 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82140307);
1208 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160960);
1212 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);
1215 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700);
1216 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30);
1218 for (i = 0; i < retrycount; i++) {
1222 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);
1223 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1230 rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, BIT(29)) == 0) {
1235 timecount = 0;
1237 rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASK_IQK_RESULT) == 0) {
1244 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1246 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4);
1248 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc);
1250 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4);
1252 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc);
1255 (((regeb4 & 0x03FF0000) >> 16) != 0x142))
1256 result |= 0x01;
1261 (((regec4 & 0x03FF0000) >> 16) != 0x132)) {
1262 result |= 0x02;
1271 rtlphy->iqk_bb_backup[0]);
1275 if (!(result & 0x01))
1276 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x19008c00);
1278 if (!(result & 0x02)) {
1279 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100);
1280 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x19008c00);
1283 "Path B Rx IQK fail!! 0xe54 = %#x\n",
1299 for (i = 0; i < regnum; i++) {
1303 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, 0x50);
1316 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1327 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x0);
1328 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000);
1329 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x808000);
1339 mode = pi_mode ? 0x01000100 : 0x01000000;
1371 if (t == 0) {
1373 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue);
1389 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017038);
1391 if (t == 0)
1399 rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BCCKEN, 0x00);
1400 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
1401 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
1402 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000);
1403 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
1406 0x00010000);
1408 0x00010000);
1416 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x0f600000);
1418 rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x0f600000);
1422 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x808000);
1423 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
1424 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1426 for (i = 0; i < retrycount; i++) {
1428 if (patha_ok == 0x03) {
1431 result[t][0] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A,
1440 } else if (i == (retrycount - 1) && patha_ok == 0x01) {
1445 result[t][0] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A,
1451 if (patha_ok == 0x00)
1459 for (i = 0; i < retrycount; i++) {
1461 if (pathb_ok == 0x03) {
1473 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1483 if (pathb_ok == 0x00)
1492 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x000000);
1494 if (t != 0) {
1517 /* load 0xe30 IQC default value */
1518 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00);
1519 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00);
1559 if (t == 0) {
1561 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue);
1581 rf_path_div = rtl_get_bbreg(hw, 0xb30, BIT(27));
1584 if (t == 0)
1597 rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BCCKEN, 0x00);
1598 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
1599 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
1600 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000);
1601 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
1604 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0);
1605 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x20000000);
1608 rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0);
1609 rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x20000000);
1614 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x808000);
1615 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x10007c00);
1616 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1619 if (patha_ok == 0x03) {
1621 result[t][0] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A,
1629 } else if (patha_ok == 0x01) { /* Tx IQK OK */
1633 result[t][0] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A,
1638 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x000000);
1639 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe70 = %#x\n",
1641 RTPRINT(rtlpriv, FINIT, INIT_IQK, "RF path A 0x0 = %#x\n",
1643 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x808000);
1653 if (pathb_ok == 0x03) {
1664 } else if (pathb_ok == 0x01) { /* Tx IQK OK */
1680 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0);
1692 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x010170b8);
1694 rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0x010170b8);
1717 u32 i, j, diff, sim_bitmap, bound, u4temp = 0;
1718 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
1727 sim_bitmap = 0;
1729 for (i = 0; i < bound; i++) {
1734 if (result[c1][i] + result[c1][i + 1] == 0)
1736 else if (result[c2][i] + result[c2][i + 1] == 0)
1746 if (sim_bitmap == 0) {
1747 for (i = 0; i < (bound / 4); i++) {
1748 if (final_candidate[i] != 0xFF) {
1756 for (i = 0; i < bound; i++)
1759 if (u4temp == 0) /* IQK fail for c1 & c2 */
1765 if (!(sim_bitmap & 0x0F)) { /* path A OK */
1766 for (i = 0; i < 4; i++)
1768 } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */
1769 for (i = 0; i < 2; i++)
1773 if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */
1776 } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */
1797 if (iqk_ok && final_candidate != 0xFF) {
1798 val_x = result[final_candidate][0];
1799 if ((val_x & 0x00000200) != 0)
1800 val_x = val_x | 0xFFFFFC00;
1802 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x\n", val_x);
1803 rtl_set_bbreg(hw, RTX_IQK_TONE_A, 0x3FF0000, val_x);
1804 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), 0);
1807 if ((val_y & 0x00000200) != 0)
1808 val_y = val_y | 0xFFFFFC00;
1814 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%x\n", val_y);
1816 rtl_set_bbreg(hw, RTX_IQK_TONE_A, 0x3FF, val_y);
1817 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26), 0);
1819 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe30 = 0x%x\n",
1828 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
1829 reg = result[final_candidate][3] & 0x3F;
1830 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
1831 reg = (result[final_candidate][3] >> 6) & 0xF;
1832 rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg);
1837 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x19008c00);
1838 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100);
1839 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x19008c00);
1863 if (final_candidate == 0xFF || !iqk_ok)
1867 oldval_0 = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0xffc00000);
1869 val_x = result[final_candidate][0];
1870 if ((val_x & 0x00000200) != 0)
1871 val_x = val_x | 0xFFFFFC00;
1875 "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n",
1877 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
1879 ((val_x * oldval_0 >> 7) & 0x1));
1882 if ((val_y & 0x00000200) != 0)
1883 val_y = val_y | 0xFFFFFC00;
1892 "Y = 0x%lx, tx0_c = 0x%lx\n",
1895 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, (tx0_c & 0x3C0) >> 6);
1896 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, tx0_c & 0x3F);
1899 (val_y * oldval_0 >> 7) & 0x1);
1901 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n",
1911 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
1912 reg = result[final_candidate][3] & 0x3F;
1913 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
1914 reg = (result[final_candidate][3] >> 6) & 0xF;
1915 rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg);
1931 if (iqk_ok && final_candidate != 0xFF) {
1933 if ((val_x & 0x00000200) != 0)
1934 val_x = val_x | 0xFFFFFC00;
1936 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x\n", val_x);
1937 rtl_set_bbreg(hw, RTX_IQK_TONE_B, 0x3FF0000, val_x);
1938 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), 0);
1941 if ((val_y & 0x00000200) != 0)
1942 val_y = val_y | 0xFFFFFC00;
1948 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%x\n", val_y);
1950 rtl_set_bbreg(hw, RTX_IQK_TONE_B, 0x3FF, val_y);
1951 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30), 0);
1953 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe50 = 0x%x\n",
1962 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
1963 reg = result[final_candidate][7] & 0x3F;
1964 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
1965 reg = (result[final_candidate][7] >> 6) & 0xF;
1966 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
1971 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x19008c00);
1972 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100);
1973 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x19008c00);
1996 if (final_candidate == 0xFF || !iqk_ok)
1999 oldval_1 = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0xffc00000);
2002 if ((val_x & 0x00000200) != 0)
2003 val_x = val_x | 0xFFFFFC00;
2006 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n",
2008 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
2010 (val_x * oldval_1 >> 7) & 0x1);
2013 if ((val_y & 0x00000200) != 0)
2014 val_y = val_y | 0xFFFFFC00;
2020 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n",
2023 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, (tx1_c & 0x3C0) >> 6);
2024 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, tx1_c & 0x3F);
2026 (val_y * oldval_1 >> 7) & 0x1);
2032 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2033 reg = result[final_candidate][7] & 0x3F;
2034 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2035 reg = (result[final_candidate][7] >> 6) & 0xF;
2036 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
2045 long regebc, regec4, regecc, regtmp = 0;
2054 final_candidate = 0xff;
2063 for (i = 0; i < 3; i++) {
2075 0, 1);
2077 final_candidate = 0;
2084 0, 2);
2086 final_candidate = 0;
2095 for (i = 0; i < 8; i++)
2098 if (regtmp != 0)
2101 final_candidate = 0xFF;
2106 for (i = 0; i < 4; i++) {
2107 rege94 = result[i][0];
2121 if (final_candidate != 0xff) {
2122 rege94 = result[final_candidate][0];
2145 rtlphy->reg_e94 = 0x100;
2146 rtlphy->reg_eb4 = 0x100; /* X default value */
2147 rtlphy->reg_e9c = 0x0;
2148 rtlphy->reg_ebc = 0x0; /* Y default value */
2150 if (rege94 != 0 /*&& regea4 != 0*/)
2153 regea4 == 0);
2155 regeb4 != 0 /*&& regec4 != 0*/)
2158 regec4 == 0);
2160 if (final_candidate != 0xFF) {
2164 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2165 rtlphy->iqk_matrix[indexforchannel].value[0][i] =
2207 if ((!rtlhal->load_imrandiqk_setting_for2g && indexforchannel == 0) ||
2208 indexforchannel > 0) {
2213 if (rtlphy->iqk_matrix[indexforchannel].value[0][0] != 0)
2215 rtlphy->iqk_matrix[indexforchannel].value, 0,
2216 rtlphy->iqk_matrix[indexforchannel].value[0][2] == 0);
2219 rtlphy->iqk_matrix[indexforchannel].value[0][4] != 0)
2221 rtlphy->iqk_matrix[indexforchannel].value, 0,
2222 rtlphy->iqk_matrix[indexforchannel].value[0][6] == 0);
2244 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp);
2257 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2266 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
2269 rtlpriv->rtlhal.interfaceindex == 0) {
2278 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2281 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
2282 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800));
2297 u16 timeout = 800, timecount = 0;
2304 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
2305 if ((tmpreg & 0x70) != 0)
2307 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
2310 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2312 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F);
2314 for (index = 0; index < path; index++) {
2316 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2321 RFREG_OFFSET_MASK, 0x010000);
2325 rtl_set_rfreg(hw, index, RF_SYN_G4, 0x700, 0x7);
2329 BIT(17), 0x0);
2333 0x08000, 0x01);
2336 for (index = 0; index < path; index++) {
2350 if ((tmpreg & 0x70) != 0)
2351 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
2353 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2355 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00);
2357 for (index = 0; index < path; index++) {
2360 if (index == 0 && rtlhal->interfaceindex == 0) {
2368 memset(curvecount_val, 0, sizeof(curvecount_val));
2372 0x08000, 0x0);
2374 RTPRINT(rtlpriv, FINIT, INIT_IQK, "set RF 0x18[15] = 0\n");
2377 for (i = 0; i < CV_CURVE_CNT; i++) {
2378 u32 readval = 0, readval2 = 0;
2380 rtl_set_rfreg(hw, (enum radio_path)index, 0x3F,
2381 0x7f, i);
2383 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D,
2384 RFREG_OFFSET_MASK, 0x0);
2387 0x4F, RFREG_OFFSET_MASK);
2388 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5;
2390 /* reg 0x4f [4:0] */
2391 /* reg 0x50 [19:10] */
2393 0x50, 0xffc00);
2394 curvecount_val[2 * i] = (((readval & 0x1F) << 10) |
2398 if (index == 0 && rtlhal->interfaceindex == 0)
2409 BIT(17), 0x1);
2413 for (index = 0; index < path; index++) {
2417 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2418 rtl_write_byte(rtlpriv, offset, 0x50);
2430 u32 timeout = 2000, timecount = 0;
2455 u32 timeout = 1000, timecount = 0;
2460 return 0;
2462 return 0;
2467 return 0;
2479 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0)))
2481 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0)))
2491 return 0;
2498 return 0;
2513 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
2515 channel, 0xff);
2547 /* a. SYS_CLKR 0x08[11] = 1 restore MAC clock */
2548 /* b. SPS_CTRL 0x11[7:0] = 0x2b */
2550 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
2552 /* c. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */
2553 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2556 /* d. APSD_CTRL 0x600[7:0] = 0x00 */
2557 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
2559 /* e. SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function again */
2560 /* f. SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function*/
2561 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2562 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2564 /* g. txpause 0x522[7:0] = 0x00 enable mac tx queue */
2565 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2574 /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
2575 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2577 /* b. RF path 0 offset 0x00 = 0x00 disable RF */
2578 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
2580 /* c. APSD_CTRL 0x600[7:0] = 0x40 */
2581 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
2583 /* d. APSD_CTRL 0x600[7:0] = 0x00
2584 * APSD_CTRL 0x600[7:0] = 0x00
2585 * RF path 0 offset 0x00 = 0x00
2586 * APSD_CTRL 0x600[7:0] = 0x40
2588 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
2589 while (u4btmp != 0 && retry > 0) {
2590 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
2591 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
2592 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
2593 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
2596 if (retry == 0) {
2598 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
2600 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2601 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2602 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2608 /* e. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */
2609 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2611 /* f. SPS_CTRL 0x11[7:0] = 0x22 */
2613 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
2631 u32 initializecount = 0;
2699 u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1);
2703 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */
2719 if (rtlhal->interfaceindex == 0) {
2729 for (i = 0; i < 200; i++) {
2730 if ((value8 & BIT(7)) == 0)
2753 /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */
2755 /* r_select_5G for path_A/B, 0x878 */
2756 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0);
2757 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0);
2759 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0);
2760 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0);
2763 /* rssi_table_select: index 0 for 2.4G. 1~3 for 5G, 0xc78 */
2764 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0);
2766 /* fc_area 0xd2c */
2767 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0);
2770 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
2772 /* TX BB gain shift*1, Just for testchip, 0xc80, 0xc88 */
2773 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, 0x40000100);
2774 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, 0x40000100);
2784 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
2785 ((rtlefuse->eeprom_cc & BIT(0)) << 5));
2786 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0);
2788 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017038);
2789 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x0f600000);
2803 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
2804 ((rtlefuse->eeprom_cc & BIT(0)) << 5));
2811 BIT(31) | BIT(15), 0);
2813 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017038);
2814 rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0x01017038);
2815 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x0f600000);
2816 rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x0f600000);
2821 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1);
2822 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1);
2824 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1);
2825 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1);
2828 /* rssi_table_select: index 0 for 2.4G. 1~3 for 5G */
2829 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1);
2832 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1);
2835 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
2837 /* TX BB gain shift, Just for testchip, 0xc80, 0xc88 */
2840 0x2d4000b5);
2843 0x20000080);
2848 MASKDWORD, 0x2d4000b5);
2851 MASKDWORD, 0x20000080);
2854 rtl_set_bbreg(hw, 0xB30, BIT(27), 0);
2865 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017098);
2866 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x20000000);
2882 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017098);
2883 rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0x01017098);
2884 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x20000000);
2885 rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x20000000);
2890 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100);
2891 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100);
2892 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 0x00);
2894 BIT(26) | BIT(24), 0x00);
2895 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 0x00);
2896 rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, 0x00);
2897 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00);
2903 /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */
2905 BIT(18) | 0xff, 1);
2908 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
2909 0x1c000, 0x07);
2911 /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */
2913 0x97524);
2917 if (rtlhal->interfaceindex == 0 && rtlhal->bandset == BAND_ON_2_4G) {
2923 RFREG_OFFSET_MASK, 0x97524);
2932 RFREG_OFFSET_MASK, 0x87401);
2941 /* Use antenna 0, 0xc04, 0xd04 */
2942 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11);
2943 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1);
2946 if (rtlhal->interfaceindex == 0) {
2948 BIT(13), 0x3);
2952 BIT(12) | BIT(13), 0x3);
2956 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(19) | BIT(20), 0x0);
2959 /* Use antenna 0 & 1, 0xc04, 0xd04 */
2960 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33);
2961 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3);
2962 /* disable ad/da clock1,0x888 */
2963 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0);
2965 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(19) | BIT(20), 0x1);
2973 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C,
2977 for (i = 0; i < 2; i++)
2978 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n",
2997 if (rtlhal->interfaceindex == 0) {
3028 read_efuse_byte(hw, 0x3FA, &val8);
3030 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "%s: 0x3FA %#x\n",
3033 if (!(val8 & BIT(0)) && (is_single_mac || rtlhal->interfaceindex == 0)) {
3034 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, 0x07401);
3035 rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x70000);
3036 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x0F425);
3037 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x4F425);
3038 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x8F425);
3041 rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x30000);
3049 rtl_set_rfreg(hw, rf_path, RF_CHNLBW, RFREG_OFFSET_MASK, 0x07401);
3050 rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x70000);
3051 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x0F425);
3052 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x4F425);
3053 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x8F425);
3056 rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x30000);
3061 if (!(val8 & BIT(2)) && (is_single_mac || rtlhal->interfaceindex == 0)) {
3063 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, 0x17524);
3064 rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x70000);
3065 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x0F496);
3066 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x4F496);
3067 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x8F496);
3070 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, 0x37564);
3071 rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x70000);
3072 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x0F496);
3073 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x4F496);
3074 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x8F496);
3077 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, 0x57595);
3078 rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x70000);
3079 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x0F496);
3080 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x4F496);
3081 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x8F496);
3084 rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x30000);
3093 rtl_set_rfreg(hw, rf_path, RF_CHNLBW, RFREG_OFFSET_MASK, 0x17524);
3094 rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x70000);
3095 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x0F496);
3096 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x4F496);
3097 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x8F496);
3100 rtl_set_rfreg(hw, rf_path, RF_CHNLBW, RFREG_OFFSET_MASK, 0x37564);
3101 rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x70000);
3102 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x0F496);
3103 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x4F496);
3104 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x8F496);
3107 rtl_set_rfreg(hw, rf_path, RF_CHNLBW, RFREG_OFFSET_MASK, 0x57595);
3108 rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x70000);
3109 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x0F496);
3110 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x4F496);
3111 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x8F496);
3114 rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x30000);