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/linux/arch/arm64/boot/dts/marvell/
H A Darmada-7040-db.dts20 memory@0 {
22 reg = <0x0 0x0 0x0 0x80000000>;
33 regulator-name = "cp0-usb3-0-current-regulator";
38 states = <500000 0x0
39 900000 0x1>;
41 gpios-states = <0>;
51 states = <500000 0x0
52 900000 0x1>;
54 gpios-states = <0>;
57 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
[all …]
/linux/Documentation/devicetree/bindings/mtd/partitions/
H A Dnvmem-cells.yaml45 reg = <0x1200000 0x0140000>;
51 macaddr_gmac1: macaddr_gmac1@0 {
52 reg = <0x0 0x6>;
56 reg = <0x6 0x6>;
60 reg = <0x1000 0x2f20>;
64 reg = <0x5000 0x2f20>;
73 partition@0 {
75 reg = <0x000000 0x100000>;
82 reg = <0x100000 0xe00000>;
88 reg = <0xf00000 0x100000>;
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,k3-m4f-rproc.yaml92 reg = <0x00 0x9cb00000 0x00 0x100000>;
98 reg = <0x00 0x9cc00000 0x00 0xe00000>;
107 mailbox0_cluster0: mailbox-0 {
113 reg = <0x00 0x5000000 0x00 0x30000>,
114 <0x00 0x5040000 0x00 0x10000>;
123 ti,sci-proc-ids = <0x18 0xff>;
/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-dir665.dts18 reg = <0x00000000 0x8000000>; /* 128 MB */
28 pinctrl-0 =< &pmx_led_usb
81 flash@0 {
86 reg = <0>;
88 partition@0 {
90 reg = <0x0 0x30000>;
96 reg = <0x30000 0x10000>;
102 reg = <0x40000 0x180000>;
107 reg = <0x1c0000 0xe00000>;
112 reg = <0xfc0000 0x10000>;
[all …]
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dgoya_masks.h180 ) & 0x7FFFFF)
191 #define GOYA_IRQ_HBW_ID_MASK 0x1FFF
192 #define GOYA_IRQ_HBW_ID_SHIFT 0
193 #define GOYA_IRQ_HBW_INTERNAL_ID_MASK 0xE000
195 #define GOYA_IRQ_HBW_AGENT_ID_MASK 0x1F0000
197 #define GOYA_IRQ_HBW_Y_MASK 0xE00000
199 #define GOYA_IRQ_HBW_X_MASK 0x7000000
201 #define GOYA_IRQ_LBW_ID_MASK 0xFF
202 #define GOYA_IRQ_LBW_ID_SHIFT 0
203 #define GOYA_IRQ_LBW_INTERNAL_ID_MASK 0x700
[all …]
/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp43x-gateworks-gw2358.dts16 memory@0 {
19 reg = <0x00000000 0x8000000>;
35 gpios = <&pld1 0 GPIO_ACTIVE_LOW>;
47 #size-cells = <0>;
51 reg = <0x28>;
55 reg = <0x68>;
59 reg = <0x51>;
66 reg = <0x56>;
73 reg = <0x57>;
81 flash@0,0 {
[all …]
/linux/arch/m68k/include/asm/
H A Dm5307sim.h27 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */
28 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
29 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
30 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
31 #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
32 #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Itr Assignment */
33 #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */
34 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
35 #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pend */
36 #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
[all …]
/linux/arch/csky/kernel/probes/
H A Dsimulate-insn.c18 *ptr = *(&regs->exregs[0] + index - 16); in csky_insn_reg_get_val()
47 *(&regs->exregs[0] + index - 16) = val; in csky_insn_reg_set_val()
72 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_br16()
79 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_br32()
87 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_bt16()
97 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_bt32()
107 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_bf16()
117 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_bf32()
125 unsigned long tmp = (opcode >> 2) & 0xf; in simulate_jmp16()
129 instruction_pointer_set(regs, tmp & 0xfffffffe); in simulate_jmp16()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/linux/lib/xz/
H A Dxz_dec_bcj.c1 // SPDX-License-Identifier: 0BSD
68 * PowerPC 4 0
69 * IA-64 16 0
70 * ARM 4 0
72 * SPARC 4 0
85 return b == 0x00 || b == 0xFF; in bcj_x86_test_msbyte()
93 static const uint8_t mask_to_bit_num[8] = { 0, 1, 2, 2, 3, 3, 3, 3 }; in bcj_x86()
104 return 0; in bcj_x86()
107 for (i = 0; i < size; ++i) { in bcj_x86()
108 if ((buf[i] & 0xFE) != 0xE8) in bcj_x86()
[all …]
/linux/arch/mips/lantiq/xway/
H A Dsysctrl.c21 #define CGU_IFCCR 0x0018
22 #define CGU_IFCCR_VR9 0x0024
24 #define CGU_SYS 0x0010
26 #define CGU_PCICR 0x0034
27 #define CGU_PCICR_VR9 0x0038
29 #define CGU_EPHY 0x10
33 #define PMU_PWDCR 0x1C
35 #define PMU_PWDSR 0x20
37 #define PMU_PWDCR1 0x24
39 #define PMU_PWDSR1 0x28
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_7_1_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_7_1_0_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_7_0_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_7_1_3_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define GCK_MCLK_FUSES__StartupMClkDid_MASK 0x7f
32 #define GCK_MCLK_FUSES__StartupMClkDid__SHIFT 0x0
33 #define GCK_MCLK_FUSES__MClkADCA_MASK 0x780
34 #define GCK_MCLK_FUSES__MClkADCA__SHIFT 0x7
35 #define GCK_MCLK_FUSES__MClkDDCA_MASK 0x1800
36 #define GCK_MCLK_FUSES__MClkDDCA__SHIFT 0xb
[all …]
/linux/arch/mips/include/asm/pci/
H A Dbridge.h30 #define BRIDGE_ATE_RAM_SIZE 0x00000400 /* 1kB ATE RAM */
32 #define BRIDGE_CONFIG_BASE 0x20000
33 #define BRIDGE_CONFIG1_BASE 0x28000
34 #define BRIDGE_CONFIG_END 0x30000
35 #define BRIDGE_CONFIG_SLOT_SIZE 0x1000
37 #define BRIDGE_SSRAM_512K 0x00080000 /* 512kB */
38 #define BRIDGE_SSRAM_128K 0x00020000 /* 128kB */
39 #define BRIDGE_SSRAM_64K 0x00010000 /* 64kB */
40 #define BRIDGE_SSRAM_0K 0x00000000 /* 0kB */
48 #define ATE_V 0x01
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
/linux/drivers/remoteproc/
H A Domap_remoteproc.c157 * Return: 0 on success, otherwise an appropriate failure
179 timer->timer_ops->set_load(timer->odt, 0); in omap_rproc_request_timer()
181 return 0; in omap_rproc_request_timer()
193 * Return: 0 on success, otherwise a failure as returned by DMTimer ops
210 * Return: 0 on success, otherwise a failure as returned by DMTimer ops
225 * Return: 0 on success, otherwise a failure as returned by DMTimer ops
287 if (timers[i].irq > 0 && irq == timers[i].irq) { in omap_rproc_watchdog_isr()
315 * Return: 0 on success, otherwise an appropriate failure
320 int ret = 0; in omap_rproc_enable_timers()
331 return 0; in omap_rproc_enable_timers()
[all …]

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