Searched +full:0 +full:xde000000 (Results 1 – 6 of 6) sorted by relevance
28 const: 0x1f1c31 const: 0x204252 reg = <0x62000000 0x00800000>,53 <0x48000000 0x00001000>;57 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,58 <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;59 bus-range = <0x00 0xff>;60 vendor-id = <0x1f1c>;61 device-id = <0x2042>;
55 CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region62 by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of72 can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can83 normally mapped to the 0x0 address of this region, while eDMA84 is available at 0x80000 base address.153 pattern: '^dma([0-9]|1[0-5])?$'226 reg = <0xdfc00000 0x0001000>, /* IP registers */227 <0xd0000000 0x0002000>; /* Configuration space */231 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,232 <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;[all …]
18 reg = <0xde000000 0x2000000>;
12 reg = <0xde000000 0x2000000>;19 arm,smc-id = <0xbc000000>;
16 #define MI_GPM 0x80000000 /* Set domain manager mode */17 #define MI_PPM 0x40000000 /* Set subpage protection */18 #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */19 #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */20 #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */21 #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */24 * Ks = 0, Kp = 1.27 #define MI_Ks 0x80000000 /* Should not be set */28 #define MI_Kp 0x40000000 /* Should always be set */39 * 0 => Kernel => 11 (all accesses performed according as user iaw page definition)[all …]