Home
last modified time | relevance | path

Searched +full:0 +full:xc4000 (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/media/tuners/
H A Dxc4000.h3 * Driver for Xceive XC4000 "QAM/8VSB single chip tuner"
20 /* value to be written to XREG_AMPLITUDE in DVB-T mode (0: no write) */
22 /* if non-zero, register 0x0E is set to filter analog TV video output */
28 /* xc4000 callback command */
29 #define XC4000_TUNER_RESET 0
35 * The xc4000 driver cares not for this value, other than ensuring
/linux/Documentation/admin-guide/media/
H A Dcx23885-cardlist.rst11 :stub-columns: 0
17 * - 0
142 - Leadtek Winfast PxDVR3200 H XC4000
H A Dcx88-cardlist.rst11 :stub-columns: 0
17 * - 0
370 - Leadtek WinFast DTV1800 H (XC4000)
/linux/arch/arm/mach-imx/
H A Dmx3x.h36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
/linux/drivers/media/pci/cx88/
H A Dcx88-cards.c11 #include "xc4000.h"
19 static unsigned int tuner[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
20 static unsigned int radio[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
21 static unsigned int card[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
43 } while (0)
60 .vmux = 0,
81 .vmux = 0,
82 .gpio0 = 0xff00, // internal decoder
85 .vmux = 0,
86 .gpio0 = 0xff01, // mono from tuner chip
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dmarvell,pp2.yaml32 const: 0
59 '^(ethernet-)?port@[0-2]$':
92 "hifX", with X in [0..8], and "link". The names "tx-cpu0",
165 '^(ethernet-)?port@[0-2]$':
187 '^(ethernet-)?port@[0-1]$':
204 #size-cells = <0>;
206 reg = <0xf0000 0xa000>,
207 <0xc0000 0x3060>,
208 <0xc4000 0x100>,
209 <0xc5000 0x100>;
[all …]
/linux/drivers/staging/gpib/hp_82335/
H A Dhp82335.c216 return 0; in hp82335_allocate_private()
227 return 0x1ff8 + register_num; in tms9914_to_hp82335_offset()
244 writeb(0, tms_priv->mmiobase + HPREG_INTR_CLEAR); in hp82335_clear_interrupt()
254 board->status = 0; in hp82335_attach()
265 case 0xc4000: in hp82335_attach()
266 case 0xc8000: in hp82335_attach()
267 case 0xcc000: in hp82335_attach()
268 case 0xd0000: in hp82335_attach()
269 case 0xd4000: in hp82335_attach()
270 case 0xd8000: in hp82335_attach()
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-375.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
80 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
85 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
86 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
[all …]
/linux/drivers/media/common/
H A Dtveeprom.c67 /* 0-9 */
236 { TUNER_ABSENT, "Xceive XC4000"},
284 /* 0-4 */
306 { TVEEPROM_AUDPROC_OTHER, "Type 0x12" },
319 { TVEEPROM_AUDPROC_MSP, "Type 0x1d" },
352 /* 0-4 */
412 return 0; in hasRadioTuner()
421 ** if packet[0] == 0x84, then packet[0..1] == length in tveeprom_hauppauge_analog()
422 ** else length = packet[0] & 3f; in tveeprom_hauppauge_analog()
423 ** if packet[0] & f8 == f8, then EOD and packet[1] == checksum in tveeprom_hauppauge_analog()
[all …]
/linux/drivers/media/usb/dvb-usb/
H A Ddib0700_devices.c17 #include "xc4000.h"
29 …vation of Low-Noise-Amplifier(s) (LNA), if applicable for the device (default: 0=automatic/off).");
42 .i2c_address = 0x60,
45 .i2c_address = 0x61,
52 .setup = (1 << 8) | (5 << 5) | (0 << 4) | (0 << 3) | (0 << 2) | (2 << 0),
57 .agc2_min = 0,
59 .agc1_pt1 = 0,
62 .agc1_slope1 = 0,
65 .agc2_pt1 = 0,
74 .max_time = 0x196,
[all …]
/linux/drivers/media/v4l2-core/
H A Dtuner-core.c43 #include "xc4000.h"
95 } while (0)
267 return 0; in fe_set_config()
308 dprintk("tuner 0x%02x: Tuner type absent\n", c->addr); in set_type()
350 buffer[0] = 0x0b; in set_type()
351 buffer[1] = 0xdc; in set_type()
352 buffer[2] = 0x9c; in set_type()
353 buffer[3] = 0x60; in set_type()
356 buffer[2] = 0x86; in set_type()
357 buffer[3] = 0x54; in set_type()
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-sa8775p.c74 .offset = 0x0,
77 .enable_reg = 0x4b028,
78 .enable_mask = BIT(0),
89 { 0x1, 2 },
94 .offset = 0x0,
111 .offset = 0x1000,
114 .enable_reg = 0x4b028,
126 .offset = 0x4000,
129 .enable_reg = 0x4b028,
141 .offset = 0x5000,
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
H A Dbnx2x_reg.h26 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
27 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
28 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
29 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
30 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
31 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
33 #define ATC_REG_ATC_INIT_ARRAY 0x1100b8
35 #define ATC_REG_ATC_INIT_DONE 0x1100bc
36 /* [RC 6] Interrupt register #0 read clear */
37 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0
[all …]