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/linux/arch/arm/boot/dts/marvell/
H A Darmada-395.dtsi19 reg = <0x18000 0x20>;
24 reg = <0xa8000 0x2000>;
32 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
H A Darmada-38x.dtsi42 pcie-mem-aperture = <0xe0000000 0x8000000>;
43 pcie-io-aperture = <0xe8000000 0x100000>;
47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
66 clocks = <&coreclk 0>;
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dqoriq-fman3-0-1g-0.dtsi3 * QorIQ FMan v3 1g port #0 device tree
11 cell-index = <0x8>;
13 reg = <0x88000 0x1000>;
17 cell-index = <0x28>;
19 reg = <0xa8000 0x1000>;
23 cell-index = <0>;
25 reg = <0xe0000 0x1000>;
34 #size-cells = <0>;
36 reg = <0xe1000 0x1000>;
38 pcsphy0: ethernet-phy@0 {
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dqcom-usb-ipq4019-phy.yaml30 const: 0
46 #phy-cells = <0>;
48 reg = <0xa8000 0x40>;
/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-fman3-0-10g-2.dtsi3 * QorIQ FMan v3 10g port #2 device tree stub [ controller @ offset 0x400000 ]
11 cell-index = <0x8>;
13 reg = <0x88000 0x1000>;
18 cell-index = <0x28>;
20 reg = <0xa8000 0x1000>;
25 cell-index = <0>;
27 reg = <0xe0000 0x1000>;
36 #size-cells = <0>;
38 reg = <0xe1000 0x1000>;
41 pcsphy0: ethernet-phy@0 {
[all …]
H A Dqoriq-fman-0-1g-0.dtsi2 * QorIQ FMan 1g port #0 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x8>;
39 reg = <0x88000 0x1000>;
43 cell-index = <0x28>;
45 reg = <0xa8000 0x1000>;
49 cell-index = <0>;
51 reg = <0xe0000 0x1000>;
59 #size-cells = <0>;
61 reg = <0xe1120 0xee0>;
62 interrupts = <100 2 0 0>;
[all …]
H A Dqoriq-fman3-1-1g-0.dtsi2 * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x500000 ]
37 cell-index = <0x8>;
39 reg = <0x88000 0x1000>;
43 cell-index = <0x28>;
45 reg = <0xa8000 0x1000>;
49 cell-index = <0>;
51 reg = <0xe0000 0x1000>;
60 #size-cells = <0>;
62 reg = <0xe1000 0x1000>;
65 pcsphy8: ethernet-phy@0 {
[all …]
H A Dqoriq-fman3-0-1g-0.dtsi2 * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x8>;
39 reg = <0x88000 0x1000>;
43 cell-index = <0x28>;
45 reg = <0xa8000 0x1000>;
49 cell-index = <0>;
51 reg = <0xe0000 0x1000>;
60 #size-cells = <0>;
62 reg = <0xe1000 0x1000>;
65 pcsphy0: ethernet-phy@0 {
[all …]
H A Dqoriq-fman-1-1g-0.dtsi2 * QorIQ FMan 1g port #0 device tree stub [ controller @ offset 0x500000 ]
37 cell-index = <0x8>;
39 reg = <0x88000 0x1000>;
43 cell-index = <0x28>;
45 reg = <0xa8000 0x1000>;
49 cell-index = <0>;
51 reg = <0xe0000 0x1000>;
59 #size-cells = <0>;
61 reg = <0xe1120 0xee0>;
64 reg = <0x8>;
H A Dqoriq-fman3-0-10g-0-best-effort.dtsi2 * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x8>;
39 reg = <0x88000 0x1000>;
45 cell-index = <0x28>;
47 reg = <0xa8000 0x1000>;
53 cell-index = <0>;
55 reg = <0xe0000 0x1000>;
64 #size-cells = <0>;
66 reg = <0xe1000 0x1000>;
69 pcsphy0: ethernet-phy@0 {
[all …]
H A Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dfsl,fman-port.yaml72 reg = <0xa8000 0x1000>;
73 cell-index = <0x28>;
H A Dfsl,fman.yaml22 FMan block. The offset is 0xc4 from the beginning of the
23 Frame Processing Manager memory map (0xc3000 from the
38 DEVDISR[1] 1 0
43 DCFG_DEVDISR2[6] 1 0
50 DCFG_CCSR_DEVDISR2[24] 1 0
156 reg = <0x400000 0x100000>;
157 ranges = <0 0x400000 0x100000>;
165 fsl,qman-channel-range = <0x40 0xc>;
167 muram@0 {
169 reg = <0x0 0x28000>;
[all …]
/linux/arch/arm/mach-imx/
H A Dmx3x.h36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7996/
H A Dmmio.c20 #define INVALID_REG_ADDR 0xffffffff
23 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } },
24 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } },
25 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } },
26 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } },
27 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } },
28 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } },
29 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } },
30 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } },
31 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } },
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dmmio.c21 [INT_SOURCE_CSR] = 0xd7010,
22 [INT_MASK_CSR] = 0xd7014,
23 [INT1_SOURCE_CSR] = 0xd7088,
24 [INT1_MASK_CSR] = 0xd708c,
25 [INT_MCU_CMD_SOURCE] = 0xd51f0,
26 [INT_MCU_CMD_EVENT] = 0x3108,
27 [WFDMA0_ADDR] = 0xd4000,
28 [WFDMA0_PCIE1_ADDR] = 0xd8000,
29 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
30 [CBTOP1_PHY_END] = 0x77ffffff,
[all …]
/linux/drivers/interconnect/qcom/
H A Dmilos.c142 .port_offsets = { 0xc000 },
144 .urg_fwd = 0,
159 .port_offsets = { 0xf200 },
161 .urg_fwd = 0,
176 .port_offsets = { 0x10000 },
178 .urg_fwd = 0,
193 .port_offsets = { 0x14000 },
195 .urg_fwd = 0,
210 .port_offsets = { 0x12000 },
212 .urg_fwd = 0,
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-kaanapali.c53 .offset = 0x0,
56 .enable_reg = 0x52020,
57 .enable_mask = BIT(0),
70 { 0x1, 2 },
75 .offset = 0x0,
92 .offset = 0x1000,
95 .enable_reg = 0x52020,
109 .offset = 0x4000,
112 .enable_reg = 0x52020,
126 .offset = 0x7000,
[all …]
H A Dgcc-hawi.c57 .offset = 0x0,
60 .enable_reg = 0x52028,
61 .enable_mask = BIT(0),
74 { 0x1, 2 },
79 .offset = 0x0,
96 .offset = 0x4000,
99 .enable_reg = 0x52028,
113 .offset = 0x5000,
116 .enable_reg = 0x52028,
130 .offset = 0x7000,
[all …]
/linux/drivers/media/pci/bt8xx/
H A Dbttv-cards.c85 static unsigned int card[BTTV_MAX] = { [ 0 ... (BTTV_MAX-1) ] = UNSET };
86 static unsigned int pll[BTTV_MAX] = { [ 0 ... (BTTV_MAX-1) ] = UNSET };
87 static unsigned int tuner[BTTV_MAX] = { [ 0 ... (BTTV_MAX-1) ] = UNSET };
88 static unsigned int svhs[BTTV_MAX] = { [ 0 ... (BTTV_MAX-1) ] = UNSET };
89 static unsigned int remote[BTTV_MAX] = { [ 0 ... (BTTV_MAX-1) ] = UNSET };
92 static struct bttv *master[BTTV_MAX] = { [ 0 ... (BTTV_MAX-1) ] = NULL };
96 static unsigned int audiomux[5] = { [ 0 ... 4 ] = UNSET };
118 MODULE_PARM_DESC(pll, "specify installed crystal (0=none, 28=28 MHz, 35=35 MHz, 14=14 MHz)");
123 "\t\t 0 = autodetect (default)\n"
127 MODULE_PARM_DESC(saa6588, "if 1, then load the saa6588 RDS module, default (0) is to use the card d…
[all …]