1724ba675SRob Herring&l4_wkup { /* 0x44c00000 */ 2724ba675SRob Herring compatible = "ti,am4-l4-wkup", "simple-pm-bus"; 3724ba675SRob Herring power-domains = <&prm_wkup>; 4724ba675SRob Herring clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>; 5724ba675SRob Herring clock-names = "fck"; 6724ba675SRob Herring reg = <0x44c00000 0x800>, 7724ba675SRob Herring <0x44c00800 0x800>, 8724ba675SRob Herring <0x44c01000 0x400>, 9724ba675SRob Herring <0x44c01400 0x400>; 10724ba675SRob Herring reg-names = "ap", "la", "ia0", "ia1"; 11724ba675SRob Herring #address-cells = <1>; 12724ba675SRob Herring #size-cells = <1>; 13724ba675SRob Herring ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ 14724ba675SRob Herring <0x00100000 0x44d00000 0x100000>, /* segment 1 */ 15724ba675SRob Herring <0x00200000 0x44e00000 0x100000>; /* segment 2 */ 16724ba675SRob Herring 17724ba675SRob Herring segment@0 { /* 0x44c00000 */ 18724ba675SRob Herring compatible = "simple-pm-bus"; 19724ba675SRob Herring #address-cells = <1>; 20724ba675SRob Herring #size-cells = <1>; 21724ba675SRob Herring ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 22724ba675SRob Herring <0x00000800 0x00000800 0x000800>, /* ap 1 */ 23724ba675SRob Herring <0x00001000 0x00001000 0x000400>, /* ap 2 */ 24724ba675SRob Herring <0x00001400 0x00001400 0x000400>; /* ap 3 */ 25724ba675SRob Herring }; 26724ba675SRob Herring 27724ba675SRob Herring segment@100000 { /* 0x44d00000 */ 28724ba675SRob Herring compatible = "simple-pm-bus"; 29724ba675SRob Herring #address-cells = <1>; 30724ba675SRob Herring #size-cells = <1>; 31724ba675SRob Herring ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ 32724ba675SRob Herring <0x00004000 0x00104000 0x001000>, /* ap 5 */ 33724ba675SRob Herring <0x00080000 0x00180000 0x002000>, /* ap 6 */ 34724ba675SRob Herring <0x00082000 0x00182000 0x001000>, /* ap 7 */ 35724ba675SRob Herring <0x000f0000 0x001f0000 0x010000>; /* ap 8 */ 36724ba675SRob Herring 37724ba675SRob Herring target-module@0 { /* 0x44d00000, ap 4 28.0 */ 38724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 39724ba675SRob Herring reg = <0x0 0x4>; 40724ba675SRob Herring reg-names = "rev"; 41724ba675SRob Herring clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>; 42724ba675SRob Herring clock-names = "fck"; 43724ba675SRob Herring #address-cells = <1>; 44724ba675SRob Herring #size-cells = <1>; 45724ba675SRob Herring ranges = <0x00000000 0x00000000 0x4000>, 46724ba675SRob Herring <0x00080000 0x00080000 0x2000>; 47724ba675SRob Herring 48724ba675SRob Herring wkup_m3: cpu@0 { 49724ba675SRob Herring compatible = "ti,am4372-wkup-m3"; 50724ba675SRob Herring reg = <0x00000000 0x4000>, 51724ba675SRob Herring <0x00080000 0x2000>; 52724ba675SRob Herring reg-names = "umem", "dmem"; 53724ba675SRob Herring resets = <&prm_wkup 3>; 54724ba675SRob Herring reset-names = "rstctrl"; 55724ba675SRob Herring ti,pm-firmware = "am335x-pm-firmware.elf"; 56724ba675SRob Herring }; 57724ba675SRob Herring }; 58724ba675SRob Herring 59724ba675SRob Herring target-module@f0000 { /* 0x44df0000, ap 8 58.0 */ 60724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 61724ba675SRob Herring reg = <0xf0000 0x4>; 62724ba675SRob Herring reg-names = "rev"; 63724ba675SRob Herring #address-cells = <1>; 64724ba675SRob Herring #size-cells = <1>; 65724ba675SRob Herring ranges = <0x0 0xf0000 0x10000>; 66724ba675SRob Herring 67724ba675SRob Herring prcm: prcm@0 { 68724ba675SRob Herring compatible = "ti,am4-prcm", "simple-bus"; 69724ba675SRob Herring reg = <0x0 0x11000>; 70724ba675SRob Herring interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 71724ba675SRob Herring #address-cells = <1>; 72724ba675SRob Herring #size-cells = <1>; 73724ba675SRob Herring ranges = <0 0 0x11000>; 74724ba675SRob Herring 75724ba675SRob Herring prcm_clocks: clocks { 76724ba675SRob Herring #address-cells = <1>; 77724ba675SRob Herring #size-cells = <0>; 78724ba675SRob Herring }; 79724ba675SRob Herring 80724ba675SRob Herring prcm_clockdomains: clockdomains { 81724ba675SRob Herring }; 82724ba675SRob Herring }; 83724ba675SRob Herring }; 84724ba675SRob Herring }; 85724ba675SRob Herring 86724ba675SRob Herring segment@200000 { /* 0x44e00000 */ 87724ba675SRob Herring compatible = "simple-pm-bus"; 88724ba675SRob Herring #address-cells = <1>; 89724ba675SRob Herring #size-cells = <1>; 90724ba675SRob Herring ranges = <0x00000000 0x00200000 0x001000>, /* ap 9 */ 91724ba675SRob Herring <0x00003000 0x00203000 0x001000>, /* ap 10 */ 92724ba675SRob Herring <0x00004000 0x00204000 0x001000>, /* ap 11 */ 93724ba675SRob Herring <0x00005000 0x00205000 0x001000>, /* ap 12 */ 94724ba675SRob Herring <0x00006000 0x00206000 0x001000>, /* ap 13 */ 95724ba675SRob Herring <0x00007000 0x00207000 0x001000>, /* ap 14 */ 96724ba675SRob Herring <0x00008000 0x00208000 0x001000>, /* ap 15 */ 97724ba675SRob Herring <0x00009000 0x00209000 0x001000>, /* ap 16 */ 98724ba675SRob Herring <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ 99724ba675SRob Herring <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ 100724ba675SRob Herring <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ 101724ba675SRob Herring <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ 102724ba675SRob Herring <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ 103724ba675SRob Herring <0x00010000 0x00210000 0x010000>, /* ap 22 */ 104724ba675SRob Herring <0x00030000 0x00230000 0x001000>, /* ap 23 */ 105724ba675SRob Herring <0x00031000 0x00231000 0x001000>, /* ap 24 */ 106724ba675SRob Herring <0x00032000 0x00232000 0x001000>, /* ap 25 */ 107724ba675SRob Herring <0x00033000 0x00233000 0x001000>, /* ap 26 */ 108724ba675SRob Herring <0x00034000 0x00234000 0x001000>, /* ap 27 */ 109724ba675SRob Herring <0x00035000 0x00235000 0x001000>, /* ap 28 */ 110724ba675SRob Herring <0x00036000 0x00236000 0x001000>, /* ap 29 */ 111724ba675SRob Herring <0x00037000 0x00237000 0x001000>, /* ap 30 */ 112724ba675SRob Herring <0x00038000 0x00238000 0x001000>, /* ap 31 */ 113724ba675SRob Herring <0x00039000 0x00239000 0x001000>, /* ap 32 */ 114724ba675SRob Herring <0x0003a000 0x0023a000 0x001000>, /* ap 33 */ 115724ba675SRob Herring <0x0003e000 0x0023e000 0x001000>, /* ap 34 */ 116724ba675SRob Herring <0x0003f000 0x0023f000 0x001000>, /* ap 35 */ 117724ba675SRob Herring <0x00040000 0x00240000 0x040000>, /* ap 36 */ 118724ba675SRob Herring <0x00080000 0x00280000 0x001000>, /* ap 37 */ 119724ba675SRob Herring <0x00088000 0x00288000 0x008000>, /* ap 38 */ 120724ba675SRob Herring <0x00092000 0x00292000 0x001000>, /* ap 39 */ 121724ba675SRob Herring <0x00086000 0x00286000 0x001000>, /* ap 40 */ 122724ba675SRob Herring <0x00087000 0x00287000 0x001000>, /* ap 41 */ 123724ba675SRob Herring <0x00090000 0x00290000 0x001000>, /* ap 42 */ 124724ba675SRob Herring <0x00091000 0x00291000 0x001000>; /* ap 43 */ 125724ba675SRob Herring 126724ba675SRob Herring target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ 127724ba675SRob Herring compatible = "ti,sysc"; 128724ba675SRob Herring status = "disabled"; 129724ba675SRob Herring #address-cells = <1>; 130724ba675SRob Herring #size-cells = <1>; 131724ba675SRob Herring ranges = <0x0 0x3000 0x1000>; 132724ba675SRob Herring }; 133724ba675SRob Herring 134724ba675SRob Herring target-module@5000 { /* 0x44e05000, ap 12 30.0 */ 135724ba675SRob Herring compatible = "ti,sysc"; 136724ba675SRob Herring status = "disabled"; 137724ba675SRob Herring #address-cells = <1>; 138724ba675SRob Herring #size-cells = <1>; 139724ba675SRob Herring ranges = <0x0 0x5000 0x1000>; 140724ba675SRob Herring }; 141724ba675SRob Herring 142724ba675SRob Herring target-module@7000 { /* 0x44e07000, ap 14 20.0 */ 143724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 144724ba675SRob Herring reg = <0x7000 0x4>, 145724ba675SRob Herring <0x7010 0x4>, 146724ba675SRob Herring <0x7114 0x4>; 147724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 148724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 149724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 150724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 151724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 152724ba675SRob Herring <SYSC_IDLE_NO>, 153724ba675SRob Herring <SYSC_IDLE_SMART>, 154724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 155724ba675SRob Herring ti,syss-mask = <1>; 156724ba675SRob Herring /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 157724ba675SRob Herring clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 0>, 158724ba675SRob Herring <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 8>; 159724ba675SRob Herring clock-names = "fck", "dbclk"; 160724ba675SRob Herring #address-cells = <1>; 161724ba675SRob Herring #size-cells = <1>; 162724ba675SRob Herring ranges = <0x0 0x7000 0x1000>; 163724ba675SRob Herring 164724ba675SRob Herring gpio0: gpio@0 { 165724ba675SRob Herring compatible = "ti,am4372-gpio","ti,omap4-gpio"; 166724ba675SRob Herring reg = <0x0 0x1000>; 167724ba675SRob Herring interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 168724ba675SRob Herring gpio-controller; 169724ba675SRob Herring #gpio-cells = <2>; 170724ba675SRob Herring interrupt-controller; 171724ba675SRob Herring #interrupt-cells = <2>; 172724ba675SRob Herring status = "disabled"; 173724ba675SRob Herring }; 174724ba675SRob Herring }; 175724ba675SRob Herring 176724ba675SRob Herring target-module@9000 { /* 0x44e09000, ap 16 04.0 */ 177724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 178724ba675SRob Herring reg = <0x9050 0x4>, 179724ba675SRob Herring <0x9054 0x4>, 180724ba675SRob Herring <0x9058 0x4>; 181724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 182724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 183724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 184724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 185724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 186724ba675SRob Herring <SYSC_IDLE_NO>, 187724ba675SRob Herring <SYSC_IDLE_SMART>, 188724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 189724ba675SRob Herring /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 190724ba675SRob Herring clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_UART1_CLKCTRL 0>; 191724ba675SRob Herring clock-names = "fck"; 192724ba675SRob Herring #address-cells = <1>; 193724ba675SRob Herring #size-cells = <1>; 194724ba675SRob Herring ranges = <0x0 0x9000 0x1000>; 195724ba675SRob Herring 196724ba675SRob Herring uart0: serial@0 { 197724ba675SRob Herring compatible = "ti,am4372-uart"; 198724ba675SRob Herring reg = <0x0 0x2000>; 199724ba675SRob Herring interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 200724ba675SRob Herring }; 201724ba675SRob Herring }; 202724ba675SRob Herring 203724ba675SRob Herring target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ 204724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 205724ba675SRob Herring reg = <0xb000 0x8>, 206724ba675SRob Herring <0xb010 0x8>, 207724ba675SRob Herring <0xb090 0x8>; 208724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 209724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 210724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 211724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 212724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 213724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 214724ba675SRob Herring <SYSC_IDLE_NO>, 215724ba675SRob Herring <SYSC_IDLE_SMART>, 216724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 217724ba675SRob Herring ti,syss-mask = <1>; 218724ba675SRob Herring /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 219724ba675SRob Herring clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_I2C1_CLKCTRL 0>; 220724ba675SRob Herring clock-names = "fck"; 221724ba675SRob Herring #address-cells = <1>; 222724ba675SRob Herring #size-cells = <1>; 223724ba675SRob Herring ranges = <0x0 0xb000 0x1000>; 224724ba675SRob Herring 225724ba675SRob Herring i2c0: i2c@0 { 226724ba675SRob Herring compatible = "ti,am4372-i2c","ti,omap4-i2c"; 227724ba675SRob Herring reg = <0x0 0x1000>; 228724ba675SRob Herring interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 229724ba675SRob Herring #address-cells = <1>; 230724ba675SRob Herring #size-cells = <0>; 231724ba675SRob Herring status = "disabled"; 232724ba675SRob Herring }; 233724ba675SRob Herring }; 234724ba675SRob Herring 235724ba675SRob Herring target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ 236724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 237724ba675SRob Herring reg = <0xd000 0x4>, 238724ba675SRob Herring <0xd010 0x4>; 239724ba675SRob Herring reg-names = "rev", "sysc"; 240724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 241724ba675SRob Herring <SYSC_IDLE_NO>, 242724ba675SRob Herring <SYSC_IDLE_SMART>, 243724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 244724ba675SRob Herring /* Domains (P, C): wkup_pwrdm, l3s_tsc_clkdm */ 245724ba675SRob Herring clocks = <&l3s_tsc_clkctrl AM4_L3S_TSC_ADC_TSC_CLKCTRL 0>; 246724ba675SRob Herring clock-names = "fck"; 247724ba675SRob Herring #address-cells = <1>; 248724ba675SRob Herring #size-cells = <1>; 249724ba675SRob Herring ranges = <0x0 0xd000 0x1000>; 250724ba675SRob Herring 251724ba675SRob Herring tscadc: tscadc@0 { 252724ba675SRob Herring compatible = "ti,am3359-tscadc"; 253724ba675SRob Herring reg = <0x0 0x1000>; 254724ba675SRob Herring interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 255724ba675SRob Herring clocks = <&adc_tsc_fck>; 256724ba675SRob Herring clock-names = "fck"; 257724ba675SRob Herring status = "disabled"; 258724ba675SRob Herring dmas = <&edma 53 0>, <&edma 57 0>; 259724ba675SRob Herring dma-names = "fifo0", "fifo1"; 260724ba675SRob Herring 261724ba675SRob Herring tsc { 262724ba675SRob Herring compatible = "ti,am3359-tsc"; 263724ba675SRob Herring }; 264724ba675SRob Herring 265724ba675SRob Herring adc { 266724ba675SRob Herring #io-channel-cells = <1>; 267724ba675SRob Herring compatible = "ti,am3359-adc"; 268724ba675SRob Herring }; 269724ba675SRob Herring 270724ba675SRob Herring }; 271724ba675SRob Herring }; 272724ba675SRob Herring 273724ba675SRob Herring target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ 274724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 275724ba675SRob Herring reg = <0x10000 0x4>; 276724ba675SRob Herring reg-names = "rev"; 277724ba675SRob Herring clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_CONTROL_CLKCTRL 0>; 278724ba675SRob Herring clock-names = "fck"; 279724ba675SRob Herring ti,no-idle; 280724ba675SRob Herring #address-cells = <1>; 281724ba675SRob Herring #size-cells = <1>; 282724ba675SRob Herring ranges = <0x0 0x10000 0x10000>; 283724ba675SRob Herring 284724ba675SRob Herring scm: scm@0 { 285724ba675SRob Herring compatible = "ti,am4-scm", "simple-bus"; 286724ba675SRob Herring reg = <0x0 0x4000>; 287724ba675SRob Herring #address-cells = <1>; 288724ba675SRob Herring #size-cells = <1>; 289724ba675SRob Herring ranges = <0 0 0x4000>; 290724ba675SRob Herring 291724ba675SRob Herring am43xx_pinmux: pinmux@800 { 292724ba675SRob Herring compatible = "ti,am437-padconf", 293724ba675SRob Herring "pinctrl-single"; 294724ba675SRob Herring reg = <0x800 0x31c>; 295724ba675SRob Herring #address-cells = <1>; 296724ba675SRob Herring #size-cells = <0>; 297724ba675SRob Herring #pinctrl-cells = <1>; 298724ba675SRob Herring #interrupt-cells = <1>; 299724ba675SRob Herring interrupt-controller; 300724ba675SRob Herring pinctrl-single,register-width = <32>; 301724ba675SRob Herring pinctrl-single,function-mask = <0xffffffff>; 302724ba675SRob Herring }; 303724ba675SRob Herring 304724ba675SRob Herring scm_conf: scm_conf@0 { 305724ba675SRob Herring compatible = "syscon", "simple-bus"; 306724ba675SRob Herring reg = <0x0 0x800>; 307724ba675SRob Herring #address-cells = <1>; 308724ba675SRob Herring #size-cells = <1>; 309724ba675SRob Herring 310724ba675SRob Herring phy_gmii_sel: phy-gmii-sel { 311724ba675SRob Herring compatible = "ti,am43xx-phy-gmii-sel"; 312724ba675SRob Herring reg = <0x650 0x4>; 313724ba675SRob Herring #phy-cells = <2>; 314724ba675SRob Herring }; 315724ba675SRob Herring 316724ba675SRob Herring scm_clocks: clocks { 317724ba675SRob Herring #address-cells = <1>; 318724ba675SRob Herring #size-cells = <0>; 319724ba675SRob Herring }; 320724ba675SRob Herring }; 321724ba675SRob Herring 322724ba675SRob Herring wkup_m3_ipc: wkup_m3_ipc@1324 { 323724ba675SRob Herring compatible = "ti,am4372-wkup-m3-ipc"; 324724ba675SRob Herring reg = <0x1324 0x44>; 325724ba675SRob Herring interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 326724ba675SRob Herring ti,rproc = <&wkup_m3>; 327724ba675SRob Herring mboxes = <&mailbox &mbox_wkupm3>; 328724ba675SRob Herring }; 329724ba675SRob Herring 330724ba675SRob Herring edma_xbar: dma-router@f90 { 331724ba675SRob Herring compatible = "ti,am335x-edma-crossbar"; 332724ba675SRob Herring reg = <0xf90 0x40>; 333724ba675SRob Herring #dma-cells = <3>; 334724ba675SRob Herring dma-requests = <64>; 335724ba675SRob Herring dma-masters = <&edma>; 336724ba675SRob Herring }; 337724ba675SRob Herring 338724ba675SRob Herring scm_clockdomains: clockdomains { 339724ba675SRob Herring }; 340724ba675SRob Herring }; 341724ba675SRob Herring }; 342724ba675SRob Herring 343724ba675SRob Herring timer1_target: target-module@31000 { /* 0x44e31000, ap 24 40.0 */ 344724ba675SRob Herring compatible = "ti,sysc-omap2-timer", "ti,sysc"; 345724ba675SRob Herring reg = <0x31000 0x4>, 346724ba675SRob Herring <0x31010 0x4>, 347724ba675SRob Herring <0x31014 0x4>; 348724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 349724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 350724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 351724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 352724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 353724ba675SRob Herring <SYSC_IDLE_NO>, 354724ba675SRob Herring <SYSC_IDLE_SMART>; 355724ba675SRob Herring ti,syss-mask = <1>; 356724ba675SRob Herring /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 357724ba675SRob Herring clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>; 358724ba675SRob Herring clock-names = "fck"; 359724ba675SRob Herring #address-cells = <1>; 360724ba675SRob Herring #size-cells = <1>; 361724ba675SRob Herring ranges = <0x0 0x31000 0x1000>; 362724ba675SRob Herring 363724ba675SRob Herring timer1: timer@0 { 364724ba675SRob Herring compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms"; 365724ba675SRob Herring reg = <0x0 0x400>; 366724ba675SRob Herring interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 367724ba675SRob Herring ti,timer-alwon; 368724ba675SRob Herring clocks = <&timer1_fck>; 369724ba675SRob Herring clock-names = "fck"; 370724ba675SRob Herring }; 371724ba675SRob Herring }; 372724ba675SRob Herring 373724ba675SRob Herring target-module@33000 { /* 0x44e33000, ap 26 18.0 */ 374724ba675SRob Herring compatible = "ti,sysc"; 375724ba675SRob Herring status = "disabled"; 376724ba675SRob Herring #address-cells = <1>; 377724ba675SRob Herring #size-cells = <1>; 378724ba675SRob Herring ranges = <0x0 0x33000 0x1000>; 379724ba675SRob Herring }; 380724ba675SRob Herring 381724ba675SRob Herring target-module@35000 { /* 0x44e35000, ap 28 50.0 */ 382724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 383724ba675SRob Herring reg = <0x35000 0x4>, 384724ba675SRob Herring <0x35010 0x4>, 385724ba675SRob Herring <0x35014 0x4>; 386724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 387724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | 388724ba675SRob Herring SYSC_OMAP2_SOFTRESET)>; 389724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 390724ba675SRob Herring <SYSC_IDLE_NO>, 391724ba675SRob Herring <SYSC_IDLE_SMART>, 392724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 393724ba675SRob Herring ti,syss-mask = <1>; 394724ba675SRob Herring /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 395724ba675SRob Herring clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_WD_TIMER2_CLKCTRL 0>; 396724ba675SRob Herring clock-names = "fck"; 397724ba675SRob Herring #address-cells = <1>; 398724ba675SRob Herring #size-cells = <1>; 399724ba675SRob Herring ranges = <0x0 0x35000 0x1000>; 400724ba675SRob Herring 401724ba675SRob Herring wdt: wdt@0 { 402724ba675SRob Herring compatible = "ti,am4372-wdt","ti,omap3-wdt"; 403724ba675SRob Herring reg = <0x0 0x1000>; 404724ba675SRob Herring interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 405724ba675SRob Herring }; 406724ba675SRob Herring }; 407724ba675SRob Herring 408724ba675SRob Herring target-module@37000 { /* 0x44e37000, ap 30 08.0 */ 409724ba675SRob Herring compatible = "ti,sysc"; 410724ba675SRob Herring status = "disabled"; 411724ba675SRob Herring #address-cells = <1>; 412724ba675SRob Herring #size-cells = <1>; 413724ba675SRob Herring ranges = <0x0 0x37000 0x1000>; 414724ba675SRob Herring }; 415724ba675SRob Herring 416724ba675SRob Herring target-module@39000 { /* 0x44e39000, ap 32 02.0 */ 417724ba675SRob Herring compatible = "ti,sysc"; 418724ba675SRob Herring status = "disabled"; 419724ba675SRob Herring #address-cells = <1>; 420724ba675SRob Herring #size-cells = <1>; 421724ba675SRob Herring ranges = <0x0 0x39000 0x1000>; 422724ba675SRob Herring }; 423724ba675SRob Herring 424724ba675SRob Herring rtc_target: target-module@3e000 { /* 0x44e3e000, ap 34 60.0 */ 425724ba675SRob Herring compatible = "ti,sysc-omap4-simple", "ti,sysc"; 426724ba675SRob Herring reg = <0x3e074 0x4>, 427724ba675SRob Herring <0x3e078 0x4>; 428724ba675SRob Herring reg-names = "rev", "sysc"; 429724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 430724ba675SRob Herring <SYSC_IDLE_NO>, 431724ba675SRob Herring <SYSC_IDLE_SMART>, 432724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 433724ba675SRob Herring /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ 434724ba675SRob Herring power-domains = <&prm_rtc>; 435724ba675SRob Herring clocks = <&l4_rtc_clkctrl AM4_L4_RTC_RTC_CLKCTRL 0>; 436724ba675SRob Herring clock-names = "fck"; 437724ba675SRob Herring #address-cells = <1>; 438724ba675SRob Herring #size-cells = <1>; 439724ba675SRob Herring ranges = <0x0 0x3e000 0x1000>; 440724ba675SRob Herring 441724ba675SRob Herring rtc: rtc@0 { 442724ba675SRob Herring compatible = "ti,am4372-rtc", "ti,am3352-rtc", 443724ba675SRob Herring "ti,da830-rtc"; 444724ba675SRob Herring reg = <0x0 0x1000>; 445*f274a854SKrzysztof Kozlowski interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 446*f274a854SKrzysztof Kozlowski <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 447724ba675SRob Herring clocks = <&clk_32768_ck>; 448724ba675SRob Herring clock-names = "int-clk"; 449724ba675SRob Herring system-power-controller; 450724ba675SRob Herring status = "disabled"; 451724ba675SRob Herring }; 452724ba675SRob Herring }; 453724ba675SRob Herring 454724ba675SRob Herring target-module@40000 { /* 0x44e40000, ap 36 68.0 */ 455724ba675SRob Herring compatible = "ti,sysc"; 456724ba675SRob Herring status = "disabled"; 457724ba675SRob Herring #address-cells = <1>; 458724ba675SRob Herring #size-cells = <1>; 459724ba675SRob Herring ranges = <0x0 0x40000 0x40000>; 460724ba675SRob Herring }; 461724ba675SRob Herring 462724ba675SRob Herring target-module@86000 { /* 0x44e86000, ap 40 70.0 */ 463724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 464724ba675SRob Herring reg = <0x86000 0x4>, 465724ba675SRob Herring <0x86004 0x4>; 466724ba675SRob Herring reg-names = "rev", "sysc"; 467724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 468724ba675SRob Herring <SYSC_IDLE_NO>; 469724ba675SRob Herring /* Domains (P, C): wkup_pwrdm, l4_wkup_aon_clkdm */ 470724ba675SRob Herring clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL 0>; 471724ba675SRob Herring clock-names = "fck"; 472724ba675SRob Herring #address-cells = <1>; 473724ba675SRob Herring #size-cells = <1>; 474724ba675SRob Herring ranges = <0x0 0x86000 0x1000>; 475724ba675SRob Herring 476724ba675SRob Herring counter32k: counter@0 { 477724ba675SRob Herring compatible = "ti,am4372-counter32k","ti,omap-counter32k"; 478724ba675SRob Herring reg = <0x0 0x40>; 479724ba675SRob Herring }; 480724ba675SRob Herring }; 481724ba675SRob Herring 482724ba675SRob Herring target-module@88000 { /* 0x44e88000, ap 38 12.0 */ 483724ba675SRob Herring compatible = "ti,sysc"; 484724ba675SRob Herring status = "disabled"; 485724ba675SRob Herring #address-cells = <1>; 486724ba675SRob Herring #size-cells = <1>; 487724ba675SRob Herring ranges = <0x00000000 0x00088000 0x00008000>, 488724ba675SRob Herring <0x00008000 0x00090000 0x00001000>, 489724ba675SRob Herring <0x00009000 0x00091000 0x00001000>; 490724ba675SRob Herring }; 491724ba675SRob Herring }; 492724ba675SRob Herring}; 493724ba675SRob Herring 494724ba675SRob Herring&l4_fast { /* 0x4a000000 */ 495724ba675SRob Herring compatible = "ti,am4-l4-fast", "simple-pm-bus"; 496724ba675SRob Herring power-domains = <&prm_per>; 497724ba675SRob Herring clocks = <&l3_clkctrl AM4_L3_L4_HS_CLKCTRL 0>; 498724ba675SRob Herring clock-names = "fck"; 499724ba675SRob Herring reg = <0x4a000000 0x800>, 500724ba675SRob Herring <0x4a000800 0x800>, 501724ba675SRob Herring <0x4a001000 0x400>; 502724ba675SRob Herring reg-names = "ap", "la", "ia0"; 503724ba675SRob Herring #address-cells = <1>; 504724ba675SRob Herring #size-cells = <1>; 505724ba675SRob Herring ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ 506724ba675SRob Herring 507724ba675SRob Herring segment@0 { /* 0x4a000000 */ 508724ba675SRob Herring compatible = "simple-pm-bus"; 509724ba675SRob Herring #address-cells = <1>; 510724ba675SRob Herring #size-cells = <1>; 511724ba675SRob Herring ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 512724ba675SRob Herring <0x00000800 0x00000800 0x000800>, /* ap 1 */ 513724ba675SRob Herring <0x00001000 0x00001000 0x000400>, /* ap 2 */ 514724ba675SRob Herring <0x00100000 0x00100000 0x008000>, /* ap 3 */ 515724ba675SRob Herring <0x00108000 0x00108000 0x001000>, /* ap 4 */ 516724ba675SRob Herring <0x00400000 0x00400000 0x002000>, /* ap 5 */ 517724ba675SRob Herring <0x00402000 0x00402000 0x001000>, /* ap 6 */ 518724ba675SRob Herring <0x00200000 0x00200000 0x080000>, /* ap 7 */ 519724ba675SRob Herring <0x00280000 0x00280000 0x001000>; /* ap 8 */ 520724ba675SRob Herring 521724ba675SRob Herring target-module@100000 { /* 0x4a100000, ap 3 04.0 */ 522724ba675SRob Herring compatible = "ti,sysc-omap4-simple", "ti,sysc"; 523724ba675SRob Herring reg = <0x101200 0x4>, 524724ba675SRob Herring <0x101208 0x4>, 525724ba675SRob Herring <0x101204 0x4>; 526724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 527724ba675SRob Herring ti,sysc-mask = <0>; 528724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 529724ba675SRob Herring <SYSC_IDLE_NO>; 530724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 531724ba675SRob Herring <SYSC_IDLE_NO>; 532724ba675SRob Herring ti,syss-mask = <1>; 533724ba675SRob Herring clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; 534724ba675SRob Herring clock-names = "fck"; 535724ba675SRob Herring #address-cells = <1>; 536724ba675SRob Herring #size-cells = <1>; 537724ba675SRob Herring ranges = <0x0 0x100000 0x8000>; 538724ba675SRob Herring 539724ba675SRob Herring mac_sw: switch@0 { 540724ba675SRob Herring compatible = "ti,am4372-cpsw-switch", "ti,cpsw-switch"; 541724ba675SRob Herring reg = <0x0 0x4000>; 542724ba675SRob Herring ranges = <0 0 0x4000>; 543724ba675SRob Herring clocks = <&cpsw_125mhz_gclk>, <&dpll_clksel_mac_clk>; 544724ba675SRob Herring clock-names = "fck", "50mclk"; 545724ba675SRob Herring assigned-clocks = <&dpll_clksel_mac_clk>; 546724ba675SRob Herring assigned-clock-rates = <50000000>; 547724ba675SRob Herring #address-cells = <1>; 548724ba675SRob Herring #size-cells = <1>; 549724ba675SRob Herring syscon = <&scm_conf>; 550724ba675SRob Herring status = "disabled"; 551724ba675SRob Herring 552*f274a854SKrzysztof Kozlowski interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 553*f274a854SKrzysztof Kozlowski <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 554*f274a854SKrzysztof Kozlowski <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 555*f274a854SKrzysztof Kozlowski <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 556724ba675SRob Herring interrupt-names = "rx_thresh", "rx", "tx", "misc"; 557724ba675SRob Herring 558724ba675SRob Herring ethernet-ports { 559724ba675SRob Herring #address-cells = <1>; 560724ba675SRob Herring #size-cells = <0>; 561724ba675SRob Herring 562724ba675SRob Herring cpsw_port1: port@1 { 563724ba675SRob Herring reg = <1>; 564724ba675SRob Herring label = "port1"; 565724ba675SRob Herring mac-address = [ 00 00 00 00 00 00 ]; 566724ba675SRob Herring phys = <&phy_gmii_sel 1 0>; 567724ba675SRob Herring }; 568724ba675SRob Herring 569724ba675SRob Herring cpsw_port2: port@2 { 570724ba675SRob Herring reg = <2>; 571724ba675SRob Herring label = "port2"; 572724ba675SRob Herring mac-address = [ 00 00 00 00 00 00 ]; 573724ba675SRob Herring phys = <&phy_gmii_sel 2 0>; 574724ba675SRob Herring }; 575724ba675SRob Herring }; 576724ba675SRob Herring 577724ba675SRob Herring davinci_mdio_sw: mdio@1000 { 578724ba675SRob Herring compatible = "ti,am4372-mdio", "ti,cpsw-mdio","ti,davinci_mdio"; 579724ba675SRob Herring clocks = <&cpsw_125mhz_gclk>; 580724ba675SRob Herring clock-names = "fck"; 581724ba675SRob Herring #address-cells = <1>; 582724ba675SRob Herring #size-cells = <0>; 583724ba675SRob Herring bus_freq = <1000000>; 584724ba675SRob Herring reg = <0x1000 0x100>; 585724ba675SRob Herring }; 586724ba675SRob Herring 587724ba675SRob Herring cpts { 588724ba675SRob Herring clocks = <&cpsw_cpts_rft_clk>; 589724ba675SRob Herring clock-names = "cpts"; 590724ba675SRob Herring }; 591724ba675SRob Herring }; 592724ba675SRob Herring }; 593724ba675SRob Herring 594724ba675SRob Herring target-module@200000 { /* 0x4a200000, ap 7 02.0 */ 595724ba675SRob Herring compatible = "ti,sysc"; 596724ba675SRob Herring status = "disabled"; 597724ba675SRob Herring #address-cells = <1>; 598724ba675SRob Herring #size-cells = <1>; 599724ba675SRob Herring ranges = <0x0 0x200000 0x80000>; 600724ba675SRob Herring }; 601724ba675SRob Herring 602724ba675SRob Herring target-module@400000 { /* 0x4a400000, ap 5 08.0 */ 603724ba675SRob Herring compatible = "ti,sysc"; 604724ba675SRob Herring status = "disabled"; 605724ba675SRob Herring #address-cells = <1>; 606724ba675SRob Herring #size-cells = <1>; 607724ba675SRob Herring ranges = <0x0 0x400000 0x2000>; 608724ba675SRob Herring }; 609724ba675SRob Herring }; 610724ba675SRob Herring}; 611724ba675SRob Herring 612724ba675SRob Herring&l4_per { /* 0x48000000 */ 613724ba675SRob Herring compatible = "ti,am4-l4-per", "simple-pm-bus"; 614724ba675SRob Herring power-domains = <&prm_per>; 615724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>; 616724ba675SRob Herring clock-names = "fck"; 617724ba675SRob Herring reg = <0x48000000 0x800>, 618724ba675SRob Herring <0x48000800 0x800>, 619724ba675SRob Herring <0x48001000 0x400>, 620724ba675SRob Herring <0x48001400 0x400>, 621724ba675SRob Herring <0x48001800 0x400>, 622724ba675SRob Herring <0x48001c00 0x400>; 623724ba675SRob Herring reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; 624724ba675SRob Herring #address-cells = <1>; 625724ba675SRob Herring #size-cells = <1>; 626724ba675SRob Herring ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ 627724ba675SRob Herring <0x00100000 0x48100000 0x100000>, /* segment 1 */ 628724ba675SRob Herring <0x00200000 0x48200000 0x100000>, /* segment 2 */ 629724ba675SRob Herring <0x00300000 0x48300000 0x100000>, /* segment 3 */ 630724ba675SRob Herring <0x46000000 0x46000000 0x400000>, /* l3 data port */ 631724ba675SRob Herring <0x46400000 0x46400000 0x400000>; /* l3 data port */ 632724ba675SRob Herring 633724ba675SRob Herring segment@0 { /* 0x48000000 */ 634724ba675SRob Herring compatible = "simple-pm-bus"; 635724ba675SRob Herring #address-cells = <1>; 636724ba675SRob Herring #size-cells = <1>; 637724ba675SRob Herring ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 638724ba675SRob Herring <0x00000800 0x00000800 0x000800>, /* ap 1 */ 639724ba675SRob Herring <0x00001000 0x00001000 0x000400>, /* ap 2 */ 640724ba675SRob Herring <0x00001400 0x00001400 0x000400>, /* ap 3 */ 641724ba675SRob Herring <0x00001800 0x00001800 0x000400>, /* ap 4 */ 642724ba675SRob Herring <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ 643724ba675SRob Herring <0x00008000 0x00008000 0x001000>, /* ap 6 */ 644724ba675SRob Herring <0x00009000 0x00009000 0x001000>, /* ap 7 */ 645724ba675SRob Herring <0x00022000 0x00022000 0x001000>, /* ap 8 */ 646724ba675SRob Herring <0x00023000 0x00023000 0x001000>, /* ap 9 */ 647724ba675SRob Herring <0x00024000 0x00024000 0x001000>, /* ap 10 */ 648724ba675SRob Herring <0x00025000 0x00025000 0x001000>, /* ap 11 */ 649724ba675SRob Herring <0x0002a000 0x0002a000 0x001000>, /* ap 12 */ 650724ba675SRob Herring <0x0002b000 0x0002b000 0x001000>, /* ap 13 */ 651724ba675SRob Herring <0x00038000 0x00038000 0x002000>, /* ap 14 */ 652724ba675SRob Herring <0x0003a000 0x0003a000 0x001000>, /* ap 15 */ 653724ba675SRob Herring <0x0003c000 0x0003c000 0x002000>, /* ap 16 */ 654724ba675SRob Herring <0x0003e000 0x0003e000 0x001000>, /* ap 17 */ 655724ba675SRob Herring <0x00040000 0x00040000 0x001000>, /* ap 18 */ 656724ba675SRob Herring <0x00041000 0x00041000 0x001000>, /* ap 19 */ 657724ba675SRob Herring <0x00042000 0x00042000 0x001000>, /* ap 20 */ 658724ba675SRob Herring <0x00043000 0x00043000 0x001000>, /* ap 21 */ 659724ba675SRob Herring <0x00044000 0x00044000 0x001000>, /* ap 22 */ 660724ba675SRob Herring <0x00045000 0x00045000 0x001000>, /* ap 23 */ 661724ba675SRob Herring <0x00046000 0x00046000 0x001000>, /* ap 24 */ 662724ba675SRob Herring <0x00047000 0x00047000 0x001000>, /* ap 25 */ 663724ba675SRob Herring <0x00048000 0x00048000 0x001000>, /* ap 26 */ 664724ba675SRob Herring <0x00049000 0x00049000 0x001000>, /* ap 27 */ 665724ba675SRob Herring <0x0004c000 0x0004c000 0x001000>, /* ap 28 */ 666724ba675SRob Herring <0x0004d000 0x0004d000 0x001000>, /* ap 29 */ 667724ba675SRob Herring <0x00060000 0x00060000 0x001000>, /* ap 30 */ 668724ba675SRob Herring <0x00061000 0x00061000 0x001000>, /* ap 31 */ 669724ba675SRob Herring <0x00080000 0x00080000 0x010000>, /* ap 32 */ 670724ba675SRob Herring <0x00090000 0x00090000 0x001000>, /* ap 33 */ 671724ba675SRob Herring <0x00030000 0x00030000 0x001000>, /* ap 65 */ 672724ba675SRob Herring <0x00031000 0x00031000 0x001000>, /* ap 66 */ 673724ba675SRob Herring <0x0004a000 0x0004a000 0x001000>, /* ap 71 */ 674724ba675SRob Herring <0x0004b000 0x0004b000 0x001000>, /* ap 72 */ 675724ba675SRob Herring <0x000c8000 0x000c8000 0x001000>, /* ap 73 */ 676724ba675SRob Herring <0x000c9000 0x000c9000 0x001000>, /* ap 74 */ 677724ba675SRob Herring <0x000ca000 0x000ca000 0x001000>, /* ap 77 */ 678724ba675SRob Herring <0x000cb000 0x000cb000 0x001000>, /* ap 78 */ 679724ba675SRob Herring <0x00034000 0x00034000 0x001000>, /* ap 80 */ 680724ba675SRob Herring <0x00035000 0x00035000 0x001000>, /* ap 81 */ 681724ba675SRob Herring <0x00036000 0x00036000 0x001000>, /* ap 84 */ 682724ba675SRob Herring <0x00037000 0x00037000 0x001000>, /* ap 85 */ 683724ba675SRob Herring <0x46000000 0x46000000 0x400000>, /* l3 data port */ 684724ba675SRob Herring <0x46400000 0x46400000 0x400000>; /* l3 data port */ 685724ba675SRob Herring 686724ba675SRob Herring target-module@8000 { /* 0x48008000, ap 6 10.0 */ 687724ba675SRob Herring compatible = "ti,sysc"; 688724ba675SRob Herring status = "disabled"; 689724ba675SRob Herring #address-cells = <1>; 690724ba675SRob Herring #size-cells = <1>; 691724ba675SRob Herring ranges = <0x0 0x8000 0x1000>; 692724ba675SRob Herring }; 693724ba675SRob Herring 694724ba675SRob Herring target-module@22000 { /* 0x48022000, ap 8 0a.0 */ 695724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 696724ba675SRob Herring reg = <0x22050 0x4>, 697724ba675SRob Herring <0x22054 0x4>, 698724ba675SRob Herring <0x22058 0x4>; 699724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 700724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 701724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 702724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 703724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 704724ba675SRob Herring <SYSC_IDLE_NO>, 705724ba675SRob Herring <SYSC_IDLE_SMART>, 706724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 707724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 708724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_UART2_CLKCTRL 0>; 709724ba675SRob Herring clock-names = "fck"; 710724ba675SRob Herring #address-cells = <1>; 711724ba675SRob Herring #size-cells = <1>; 712724ba675SRob Herring ranges = <0x0 0x22000 0x1000>; 713724ba675SRob Herring 714724ba675SRob Herring uart1: serial@0 { 715724ba675SRob Herring compatible = "ti,am4372-uart"; 716724ba675SRob Herring reg = <0x0 0x2000>; 717724ba675SRob Herring interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 718724ba675SRob Herring status = "disabled"; 719724ba675SRob Herring }; 720724ba675SRob Herring }; 721724ba675SRob Herring 722724ba675SRob Herring target-module@24000 { /* 0x48024000, ap 10 1c.0 */ 723724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 724724ba675SRob Herring reg = <0x24050 0x4>, 725724ba675SRob Herring <0x24054 0x4>, 726724ba675SRob Herring <0x24058 0x4>; 727724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 728724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 729724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 730724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 731724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 732724ba675SRob Herring <SYSC_IDLE_NO>, 733724ba675SRob Herring <SYSC_IDLE_SMART>, 734724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 735724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 736724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_UART3_CLKCTRL 0>; 737724ba675SRob Herring clock-names = "fck"; 738724ba675SRob Herring #address-cells = <1>; 739724ba675SRob Herring #size-cells = <1>; 740724ba675SRob Herring ranges = <0x0 0x24000 0x1000>; 741724ba675SRob Herring 742724ba675SRob Herring uart2: serial@0 { 743724ba675SRob Herring compatible = "ti,am4372-uart"; 744724ba675SRob Herring reg = <0x0 0x2000>; 745724ba675SRob Herring interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 746724ba675SRob Herring status = "disabled"; 747724ba675SRob Herring }; 748724ba675SRob Herring }; 749724ba675SRob Herring 750724ba675SRob Herring target-module@2a000 { /* 0x4802a000, ap 12 22.0 */ 751724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 752724ba675SRob Herring reg = <0x2a000 0x8>, 753724ba675SRob Herring <0x2a010 0x8>, 754724ba675SRob Herring <0x2a090 0x8>; 755724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 756724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 757724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 758724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 759724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 760724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 761724ba675SRob Herring <SYSC_IDLE_NO>, 762724ba675SRob Herring <SYSC_IDLE_SMART>, 763724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 764724ba675SRob Herring ti,syss-mask = <1>; 765724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 766724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_I2C2_CLKCTRL 0>; 767724ba675SRob Herring clock-names = "fck"; 768724ba675SRob Herring #address-cells = <1>; 769724ba675SRob Herring #size-cells = <1>; 770724ba675SRob Herring ranges = <0x0 0x2a000 0x1000>; 771724ba675SRob Herring 772724ba675SRob Herring i2c1: i2c@0 { 773724ba675SRob Herring compatible = "ti,am4372-i2c","ti,omap4-i2c"; 774724ba675SRob Herring reg = <0x0 0x1000>; 775724ba675SRob Herring interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 776724ba675SRob Herring #address-cells = <1>; 777724ba675SRob Herring #size-cells = <0>; 778724ba675SRob Herring status = "disabled"; 779724ba675SRob Herring }; 780724ba675SRob Herring }; 781724ba675SRob Herring 782724ba675SRob Herring target-module@30000 { /* 0x48030000, ap 65 08.0 */ 783724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 784724ba675SRob Herring reg = <0x30000 0x4>, 785724ba675SRob Herring <0x30110 0x4>, 786724ba675SRob Herring <0x30114 0x4>; 787724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 788724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 789724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 790724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 791724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 792724ba675SRob Herring <SYSC_IDLE_NO>, 793724ba675SRob Herring <SYSC_IDLE_SMART>; 794724ba675SRob Herring ti,syss-mask = <1>; 795724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 796724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_SPI0_CLKCTRL 0>; 797724ba675SRob Herring clock-names = "fck"; 798724ba675SRob Herring #address-cells = <1>; 799724ba675SRob Herring #size-cells = <1>; 800724ba675SRob Herring ranges = <0x0 0x30000 0x1000>; 801724ba675SRob Herring 802724ba675SRob Herring spi0: spi@0 { 803724ba675SRob Herring compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; 804724ba675SRob Herring reg = <0x0 0x400>; 805724ba675SRob Herring interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 806724ba675SRob Herring #address-cells = <1>; 807724ba675SRob Herring #size-cells = <0>; 808724ba675SRob Herring status = "disabled"; 809724ba675SRob Herring }; 810724ba675SRob Herring }; 811724ba675SRob Herring 812724ba675SRob Herring target-module@34000 { /* 0x48034000, ap 80 56.0 */ 813724ba675SRob Herring compatible = "ti,sysc"; 814724ba675SRob Herring status = "disabled"; 815724ba675SRob Herring #address-cells = <1>; 816724ba675SRob Herring #size-cells = <1>; 817724ba675SRob Herring ranges = <0x0 0x34000 0x1000>; 818724ba675SRob Herring }; 819724ba675SRob Herring 820724ba675SRob Herring target-module@36000 { /* 0x48036000, ap 84 3e.0 */ 821724ba675SRob Herring compatible = "ti,sysc"; 822724ba675SRob Herring status = "disabled"; 823724ba675SRob Herring #address-cells = <1>; 824724ba675SRob Herring #size-cells = <1>; 825724ba675SRob Herring ranges = <0x0 0x36000 0x1000>; 826724ba675SRob Herring }; 827724ba675SRob Herring 828724ba675SRob Herring target-module@38000 { /* 0x48038000, ap 14 04.0 */ 829724ba675SRob Herring compatible = "ti,sysc-omap4-simple", "ti,sysc"; 830724ba675SRob Herring reg = <0x38000 0x4>, 831724ba675SRob Herring <0x38004 0x4>; 832724ba675SRob Herring reg-names = "rev", "sysc"; 833724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 834724ba675SRob Herring <SYSC_IDLE_NO>, 835724ba675SRob Herring <SYSC_IDLE_SMART>; 836724ba675SRob Herring /* Domains (P, C): per_pwrdm, l3s_clkdm */ 837724ba675SRob Herring clocks = <&l3s_clkctrl AM4_L3S_MCASP0_CLKCTRL 0>; 838724ba675SRob Herring clock-names = "fck"; 839724ba675SRob Herring #address-cells = <1>; 840724ba675SRob Herring #size-cells = <1>; 841724ba675SRob Herring ranges = <0x0 0x38000 0x2000>, 842724ba675SRob Herring <0x46000000 0x46000000 0x400000>; 843724ba675SRob Herring 844724ba675SRob Herring mcasp0: mcasp@0 { 845724ba675SRob Herring compatible = "ti,am33xx-mcasp-audio"; 846724ba675SRob Herring reg = <0x0 0x2000>, 847724ba675SRob Herring <0x46000000 0x400000>; 848724ba675SRob Herring reg-names = "mpu", "dat"; 849724ba675SRob Herring interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 850724ba675SRob Herring <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 851724ba675SRob Herring interrupt-names = "tx", "rx"; 852724ba675SRob Herring status = "disabled"; 853724ba675SRob Herring dmas = <&edma 8 2>, 854724ba675SRob Herring <&edma 9 2>; 855724ba675SRob Herring dma-names = "tx", "rx"; 856724ba675SRob Herring }; 857724ba675SRob Herring }; 858724ba675SRob Herring 859724ba675SRob Herring target-module@3c000 { /* 0x4803c000, ap 16 2a.0 */ 860724ba675SRob Herring compatible = "ti,sysc-omap4-simple", "ti,sysc"; 861724ba675SRob Herring reg = <0x3c000 0x4>, 862724ba675SRob Herring <0x3c004 0x4>; 863724ba675SRob Herring reg-names = "rev", "sysc"; 864724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 865724ba675SRob Herring <SYSC_IDLE_NO>, 866724ba675SRob Herring <SYSC_IDLE_SMART>; 867724ba675SRob Herring /* Domains (P, C): per_pwrdm, l3s_clkdm */ 868724ba675SRob Herring clocks = <&l3s_clkctrl AM4_L3S_MCASP1_CLKCTRL 0>; 869724ba675SRob Herring clock-names = "fck"; 870724ba675SRob Herring #address-cells = <1>; 871724ba675SRob Herring #size-cells = <1>; 872724ba675SRob Herring ranges = <0x0 0x3c000 0x2000>, 873724ba675SRob Herring <0x46400000 0x46400000 0x400000>; 874724ba675SRob Herring 875724ba675SRob Herring mcasp1: mcasp@0 { 876724ba675SRob Herring compatible = "ti,am33xx-mcasp-audio"; 877724ba675SRob Herring reg = <0x0 0x2000>, 878724ba675SRob Herring <0x46400000 0x400000>; 879724ba675SRob Herring reg-names = "mpu", "dat"; 880724ba675SRob Herring interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 881724ba675SRob Herring <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 882724ba675SRob Herring interrupt-names = "tx", "rx"; 883724ba675SRob Herring status = "disabled"; 884724ba675SRob Herring dmas = <&edma 10 2>, 885724ba675SRob Herring <&edma 11 2>; 886724ba675SRob Herring dma-names = "tx", "rx"; 887724ba675SRob Herring }; 888724ba675SRob Herring }; 889724ba675SRob Herring 890724ba675SRob Herring timer2_target: target-module@40000 { /* 0x48040000, ap 18 1e.0 */ 891724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc"; 892724ba675SRob Herring reg = <0x40000 0x4>, 893724ba675SRob Herring <0x40010 0x4>, 894724ba675SRob Herring <0x40014 0x4>; 895724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 896724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 897724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 898724ba675SRob Herring <SYSC_IDLE_NO>, 899724ba675SRob Herring <SYSC_IDLE_SMART>, 900724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 901724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 902724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>; 903724ba675SRob Herring clock-names = "fck"; 904724ba675SRob Herring #address-cells = <1>; 905724ba675SRob Herring #size-cells = <1>; 906724ba675SRob Herring ranges = <0x0 0x40000 0x1000>; 907724ba675SRob Herring 908724ba675SRob Herring timer2: timer@0 { 909724ba675SRob Herring compatible = "ti,am4372-timer","ti,am335x-timer"; 910724ba675SRob Herring reg = <0x0 0x400>; 911724ba675SRob Herring interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 912724ba675SRob Herring clocks = <&timer2_fck>; 913724ba675SRob Herring clock-names = "fck"; 914724ba675SRob Herring }; 915724ba675SRob Herring }; 916724ba675SRob Herring 917724ba675SRob Herring target-module@42000 { /* 0x48042000, ap 20 24.0 */ 918724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc"; 919724ba675SRob Herring reg = <0x42000 0x4>, 920724ba675SRob Herring <0x42010 0x4>, 921724ba675SRob Herring <0x42014 0x4>; 922724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 923724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 924724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 925724ba675SRob Herring <SYSC_IDLE_NO>, 926724ba675SRob Herring <SYSC_IDLE_SMART>, 927724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 928724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 929724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_TIMER3_CLKCTRL 0>; 930724ba675SRob Herring clock-names = "fck"; 931724ba675SRob Herring #address-cells = <1>; 932724ba675SRob Herring #size-cells = <1>; 933724ba675SRob Herring ranges = <0x0 0x42000 0x1000>; 934724ba675SRob Herring 935724ba675SRob Herring timer3: timer@0 { 936724ba675SRob Herring compatible = "ti,am4372-timer","ti,am335x-timer"; 937724ba675SRob Herring reg = <0x0 0x400>; 938724ba675SRob Herring interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 939724ba675SRob Herring status = "disabled"; 940724ba675SRob Herring }; 941724ba675SRob Herring }; 942724ba675SRob Herring 943724ba675SRob Herring target-module@44000 { /* 0x48044000, ap 22 26.0 */ 944724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc"; 945724ba675SRob Herring reg = <0x44000 0x4>, 946724ba675SRob Herring <0x44010 0x4>, 947724ba675SRob Herring <0x44014 0x4>; 948724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 949724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 950724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 951724ba675SRob Herring <SYSC_IDLE_NO>, 952724ba675SRob Herring <SYSC_IDLE_SMART>, 953724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 954724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 955724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_TIMER4_CLKCTRL 0>; 956724ba675SRob Herring clock-names = "fck"; 957724ba675SRob Herring #address-cells = <1>; 958724ba675SRob Herring #size-cells = <1>; 959724ba675SRob Herring ranges = <0x0 0x44000 0x1000>; 960724ba675SRob Herring 961724ba675SRob Herring timer4: timer@0 { 962724ba675SRob Herring compatible = "ti,am4372-timer","ti,am335x-timer"; 963724ba675SRob Herring reg = <0x0 0x400>; 964724ba675SRob Herring interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 965724ba675SRob Herring ti,timer-pwm; 966724ba675SRob Herring status = "disabled"; 967724ba675SRob Herring }; 968724ba675SRob Herring }; 969724ba675SRob Herring 970724ba675SRob Herring target-module@46000 { /* 0x48046000, ap 24 28.0 */ 971724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc"; 972724ba675SRob Herring reg = <0x46000 0x4>, 973724ba675SRob Herring <0x46010 0x4>, 974724ba675SRob Herring <0x46014 0x4>; 975724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 976724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 977724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 978724ba675SRob Herring <SYSC_IDLE_NO>, 979724ba675SRob Herring <SYSC_IDLE_SMART>, 980724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 981724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 982724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_TIMER5_CLKCTRL 0>; 983724ba675SRob Herring clock-names = "fck"; 984724ba675SRob Herring #address-cells = <1>; 985724ba675SRob Herring #size-cells = <1>; 986724ba675SRob Herring ranges = <0x0 0x46000 0x1000>; 987724ba675SRob Herring 988724ba675SRob Herring timer5: timer@0 { 989724ba675SRob Herring compatible = "ti,am4372-timer","ti,am335x-timer"; 990724ba675SRob Herring reg = <0x0 0x400>; 991724ba675SRob Herring interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 992724ba675SRob Herring ti,timer-pwm; 993724ba675SRob Herring status = "disabled"; 994724ba675SRob Herring }; 995724ba675SRob Herring }; 996724ba675SRob Herring 997724ba675SRob Herring target-module@48000 { /* 0x48048000, ap 26 1a.0 */ 998724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc"; 999724ba675SRob Herring reg = <0x48000 0x4>, 1000724ba675SRob Herring <0x48010 0x4>, 1001724ba675SRob Herring <0x48014 0x4>; 1002724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1003724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1004724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1005724ba675SRob Herring <SYSC_IDLE_NO>, 1006724ba675SRob Herring <SYSC_IDLE_SMART>, 1007724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1008724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1009724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_TIMER6_CLKCTRL 0>; 1010724ba675SRob Herring clock-names = "fck"; 1011724ba675SRob Herring #address-cells = <1>; 1012724ba675SRob Herring #size-cells = <1>; 1013724ba675SRob Herring ranges = <0x0 0x48000 0x1000>; 1014724ba675SRob Herring 1015724ba675SRob Herring timer6: timer@0 { 1016724ba675SRob Herring compatible = "ti,am4372-timer","ti,am335x-timer"; 1017724ba675SRob Herring reg = <0x0 0x400>; 1018724ba675SRob Herring interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1019724ba675SRob Herring ti,timer-pwm; 1020724ba675SRob Herring status = "disabled"; 1021724ba675SRob Herring }; 1022724ba675SRob Herring }; 1023724ba675SRob Herring 1024724ba675SRob Herring target-module@4a000 { /* 0x4804a000, ap 71 48.0 */ 1025724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1026724ba675SRob Herring reg = <0x4a000 0x4>, 1027724ba675SRob Herring <0x4a010 0x4>, 1028724ba675SRob Herring <0x4a014 0x4>; 1029724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1030724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1031724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1032724ba675SRob Herring <SYSC_IDLE_NO>, 1033724ba675SRob Herring <SYSC_IDLE_SMART>, 1034724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1035724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1036724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_TIMER7_CLKCTRL 0>; 1037724ba675SRob Herring clock-names = "fck"; 1038724ba675SRob Herring #address-cells = <1>; 1039724ba675SRob Herring #size-cells = <1>; 1040724ba675SRob Herring ranges = <0x0 0x4a000 0x1000>; 1041724ba675SRob Herring 1042724ba675SRob Herring timer7: timer@0 { 1043724ba675SRob Herring compatible = "ti,am4372-timer","ti,am335x-timer"; 1044724ba675SRob Herring reg = <0x0 0x400>; 1045724ba675SRob Herring interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1046724ba675SRob Herring ti,timer-pwm; 1047724ba675SRob Herring status = "disabled"; 1048724ba675SRob Herring }; 1049724ba675SRob Herring }; 1050724ba675SRob Herring 1051724ba675SRob Herring target-module@4c000 { /* 0x4804c000, ap 28 36.0 */ 1052724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1053724ba675SRob Herring reg = <0x4c000 0x4>, 1054724ba675SRob Herring <0x4c010 0x4>, 1055724ba675SRob Herring <0x4c114 0x4>; 1056724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1057724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1058724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1059724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1060724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1061724ba675SRob Herring <SYSC_IDLE_NO>, 1062724ba675SRob Herring <SYSC_IDLE_SMART>, 1063724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1064724ba675SRob Herring ti,syss-mask = <1>; 1065724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1066724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 0>, 1067724ba675SRob Herring <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 8>; 1068724ba675SRob Herring clock-names = "fck", "dbclk"; 1069724ba675SRob Herring #address-cells = <1>; 1070724ba675SRob Herring #size-cells = <1>; 1071724ba675SRob Herring ranges = <0x0 0x4c000 0x1000>; 1072724ba675SRob Herring 1073724ba675SRob Herring gpio1: gpio@0 { 1074724ba675SRob Herring compatible = "ti,am4372-gpio","ti,omap4-gpio"; 1075724ba675SRob Herring reg = <0x0 0x1000>; 1076724ba675SRob Herring interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1077724ba675SRob Herring gpio-controller; 1078724ba675SRob Herring #gpio-cells = <2>; 1079724ba675SRob Herring interrupt-controller; 1080724ba675SRob Herring #interrupt-cells = <2>; 1081724ba675SRob Herring status = "disabled"; 1082724ba675SRob Herring }; 1083724ba675SRob Herring }; 1084724ba675SRob Herring 1085724ba675SRob Herring target-module@60000 { /* 0x48060000, ap 30 14.0 */ 1086724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1087724ba675SRob Herring reg = <0x602fc 0x4>, 1088724ba675SRob Herring <0x60110 0x4>, 1089724ba675SRob Herring <0x60114 0x4>; 1090724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1091724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1092724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 1093724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1094724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1095724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1096724ba675SRob Herring <SYSC_IDLE_NO>, 1097724ba675SRob Herring <SYSC_IDLE_SMART>; 1098724ba675SRob Herring ti,syss-mask = <1>; 1099724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1100724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_MMC1_CLKCTRL 0>; 1101724ba675SRob Herring clock-names = "fck"; 1102724ba675SRob Herring #address-cells = <1>; 1103724ba675SRob Herring #size-cells = <1>; 1104724ba675SRob Herring ranges = <0x0 0x60000 0x1000>; 1105724ba675SRob Herring 1106724ba675SRob Herring mmc1: mmc@0 { 1107724ba675SRob Herring compatible = "ti,am437-sdhci"; 1108724ba675SRob Herring reg = <0x0 0x1000>; 1109724ba675SRob Herring ti,needs-special-reset; 1110724ba675SRob Herring dmas = <&edma 24 0>, 1111724ba675SRob Herring <&edma 25 0>; 1112724ba675SRob Herring dma-names = "tx", "rx"; 1113724ba675SRob Herring interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1114724ba675SRob Herring status = "disabled"; 1115724ba675SRob Herring }; 1116724ba675SRob Herring }; 1117724ba675SRob Herring 1118724ba675SRob Herring target-module@80000 { /* 0x48080000, ap 32 18.0 */ 1119724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1120724ba675SRob Herring reg = <0x80000 0x4>, 1121724ba675SRob Herring <0x80010 0x4>, 1122724ba675SRob Herring <0x80014 0x4>; 1123724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1124724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1125724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1126724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1127724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1128724ba675SRob Herring <SYSC_IDLE_NO>, 1129724ba675SRob Herring <SYSC_IDLE_SMART>; 1130724ba675SRob Herring ti,syss-mask = <1>; 1131724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1132724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_ELM_CLKCTRL 0>; 1133724ba675SRob Herring clock-names = "fck"; 1134724ba675SRob Herring #address-cells = <1>; 1135724ba675SRob Herring #size-cells = <1>; 1136724ba675SRob Herring ranges = <0x0 0x80000 0x10000>; 1137724ba675SRob Herring 1138724ba675SRob Herring elm: elm@0 { 1139724ba675SRob Herring compatible = "ti,am3352-elm"; 1140724ba675SRob Herring reg = <0x0 0x2000>; 1141724ba675SRob Herring interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1142724ba675SRob Herring clocks = <&l4ls_gclk>; 1143724ba675SRob Herring clock-names = "fck"; 1144724ba675SRob Herring status = "disabled"; 1145724ba675SRob Herring }; 1146724ba675SRob Herring }; 1147724ba675SRob Herring 1148724ba675SRob Herring target-module@c8000 { /* 0x480c8000, ap 73 06.0 */ 1149724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 1150724ba675SRob Herring reg = <0xc8000 0x4>, 1151724ba675SRob Herring <0xc8010 0x4>; 1152724ba675SRob Herring reg-names = "rev", "sysc"; 1153724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1154724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1155724ba675SRob Herring <SYSC_IDLE_NO>, 1156724ba675SRob Herring <SYSC_IDLE_SMART>; 1157724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1158724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_MAILBOX_CLKCTRL 0>; 1159724ba675SRob Herring clock-names = "fck"; 1160724ba675SRob Herring #address-cells = <1>; 1161724ba675SRob Herring #size-cells = <1>; 1162724ba675SRob Herring ranges = <0x0 0xc8000 0x1000>; 1163724ba675SRob Herring 1164724ba675SRob Herring mailbox: mailbox@0 { 1165724ba675SRob Herring compatible = "ti,omap4-mailbox"; 1166724ba675SRob Herring reg = <0x0 0x200>; 1167724ba675SRob Herring interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1168724ba675SRob Herring #mbox-cells = <1>; 1169724ba675SRob Herring ti,mbox-num-users = <4>; 1170724ba675SRob Herring ti,mbox-num-fifos = <8>; 1171724ba675SRob Herring mbox_wkupm3: mbox-wkup-m3 { 1172724ba675SRob Herring ti,mbox-send-noirq; 1173724ba675SRob Herring ti,mbox-tx = <0 0 0>; 1174724ba675SRob Herring ti,mbox-rx = <0 0 3>; 1175724ba675SRob Herring }; 1176724ba675SRob Herring }; 1177724ba675SRob Herring }; 1178724ba675SRob Herring 1179724ba675SRob Herring target-module@ca000 { /* 0x480ca000, ap 77 38.0 */ 1180724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1181724ba675SRob Herring reg = <0xca000 0x4>, 1182724ba675SRob Herring <0xca010 0x4>, 1183724ba675SRob Herring <0xca014 0x4>; 1184724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1185724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1186724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 1187724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1188724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1189724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1190724ba675SRob Herring <SYSC_IDLE_NO>, 1191724ba675SRob Herring <SYSC_IDLE_SMART>; 1192724ba675SRob Herring ti,syss-mask = <1>; 1193724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1194724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_SPINLOCK_CLKCTRL 0>; 1195724ba675SRob Herring clock-names = "fck"; 1196724ba675SRob Herring #address-cells = <1>; 1197724ba675SRob Herring #size-cells = <1>; 1198724ba675SRob Herring ranges = <0x0 0xca000 0x1000>; 1199724ba675SRob Herring 1200724ba675SRob Herring hwspinlock: spinlock@0 { 1201724ba675SRob Herring compatible = "ti,omap4-hwspinlock"; 1202724ba675SRob Herring reg = <0x0 0x1000>; 1203724ba675SRob Herring #hwlock-cells = <1>; 1204724ba675SRob Herring }; 1205724ba675SRob Herring }; 1206724ba675SRob Herring }; 1207724ba675SRob Herring 1208724ba675SRob Herring segment@100000 { /* 0x48100000 */ 1209724ba675SRob Herring compatible = "simple-pm-bus"; 1210724ba675SRob Herring #address-cells = <1>; 1211724ba675SRob Herring #size-cells = <1>; 1212724ba675SRob Herring ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 34 */ 1213724ba675SRob Herring <0x0008d000 0x0018d000 0x001000>, /* ap 35 */ 1214724ba675SRob Herring <0x0008e000 0x0018e000 0x001000>, /* ap 36 */ 1215724ba675SRob Herring <0x0008f000 0x0018f000 0x001000>, /* ap 37 */ 1216724ba675SRob Herring <0x0009c000 0x0019c000 0x001000>, /* ap 38 */ 1217724ba675SRob Herring <0x0009d000 0x0019d000 0x001000>, /* ap 39 */ 1218724ba675SRob Herring <0x000a6000 0x001a6000 0x001000>, /* ap 40 */ 1219724ba675SRob Herring <0x000a7000 0x001a7000 0x001000>, /* ap 41 */ 1220724ba675SRob Herring <0x000a8000 0x001a8000 0x001000>, /* ap 42 */ 1221724ba675SRob Herring <0x000a9000 0x001a9000 0x001000>, /* ap 43 */ 1222724ba675SRob Herring <0x000aa000 0x001aa000 0x001000>, /* ap 44 */ 1223724ba675SRob Herring <0x000ab000 0x001ab000 0x001000>, /* ap 45 */ 1224724ba675SRob Herring <0x000ac000 0x001ac000 0x001000>, /* ap 46 */ 1225724ba675SRob Herring <0x000ad000 0x001ad000 0x001000>, /* ap 47 */ 1226724ba675SRob Herring <0x000ae000 0x001ae000 0x001000>, /* ap 48 */ 1227724ba675SRob Herring <0x000af000 0x001af000 0x001000>, /* ap 49 */ 1228724ba675SRob Herring <0x000cc000 0x001cc000 0x002000>, /* ap 50 */ 1229724ba675SRob Herring <0x000ce000 0x001ce000 0x002000>, /* ap 51 */ 1230724ba675SRob Herring <0x000d0000 0x001d0000 0x002000>, /* ap 52 */ 1231724ba675SRob Herring <0x000d2000 0x001d2000 0x002000>, /* ap 53 */ 1232724ba675SRob Herring <0x000d8000 0x001d8000 0x001000>, /* ap 54 */ 1233724ba675SRob Herring <0x000d9000 0x001d9000 0x001000>, /* ap 55 */ 1234724ba675SRob Herring <0x000a0000 0x001a0000 0x001000>, /* ap 67 */ 1235724ba675SRob Herring <0x000a1000 0x001a1000 0x001000>, /* ap 68 */ 1236724ba675SRob Herring <0x000a2000 0x001a2000 0x001000>, /* ap 69 */ 1237724ba675SRob Herring <0x000a3000 0x001a3000 0x001000>, /* ap 70 */ 1238724ba675SRob Herring <0x000a4000 0x001a4000 0x001000>, /* ap 92 */ 1239724ba675SRob Herring <0x000a5000 0x001a5000 0x001000>, /* ap 93 */ 1240724ba675SRob Herring <0x000c1000 0x001c1000 0x001000>, /* ap 94 */ 1241724ba675SRob Herring <0x000c2000 0x001c2000 0x001000>; /* ap 95 */ 1242724ba675SRob Herring 1243724ba675SRob Herring target-module@8c000 { /* 0x4818c000, ap 34 0c.0 */ 1244724ba675SRob Herring compatible = "ti,sysc"; 1245724ba675SRob Herring status = "disabled"; 1246724ba675SRob Herring #address-cells = <1>; 1247724ba675SRob Herring #size-cells = <1>; 1248724ba675SRob Herring ranges = <0x0 0x8c000 0x1000>; 1249724ba675SRob Herring }; 1250724ba675SRob Herring 1251724ba675SRob Herring target-module@8e000 { /* 0x4818e000, ap 36 02.0 */ 1252724ba675SRob Herring compatible = "ti,sysc"; 1253724ba675SRob Herring status = "disabled"; 1254724ba675SRob Herring #address-cells = <1>; 1255724ba675SRob Herring #size-cells = <1>; 1256724ba675SRob Herring ranges = <0x0 0x8e000 0x1000>; 1257724ba675SRob Herring }; 1258724ba675SRob Herring 1259724ba675SRob Herring target-module@9c000 { /* 0x4819c000, ap 38 52.0 */ 1260724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1261724ba675SRob Herring reg = <0x9c000 0x8>, 1262724ba675SRob Herring <0x9c010 0x8>, 1263724ba675SRob Herring <0x9c090 0x8>; 1264724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1265724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1266724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 1267724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1268724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1269724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1270724ba675SRob Herring <SYSC_IDLE_NO>, 1271724ba675SRob Herring <SYSC_IDLE_SMART>, 1272724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1273724ba675SRob Herring ti,syss-mask = <1>; 1274724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1275724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_I2C3_CLKCTRL 0>; 1276724ba675SRob Herring clock-names = "fck"; 1277724ba675SRob Herring #address-cells = <1>; 1278724ba675SRob Herring #size-cells = <1>; 1279724ba675SRob Herring ranges = <0x0 0x9c000 0x1000>; 1280724ba675SRob Herring 1281724ba675SRob Herring i2c2: i2c@0 { 1282724ba675SRob Herring compatible = "ti,am4372-i2c","ti,omap4-i2c"; 1283724ba675SRob Herring reg = <0x0 0x1000>; 1284724ba675SRob Herring interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1285724ba675SRob Herring #address-cells = <1>; 1286724ba675SRob Herring #size-cells = <0>; 1287724ba675SRob Herring status = "disabled"; 1288724ba675SRob Herring }; 1289724ba675SRob Herring }; 1290724ba675SRob Herring 1291724ba675SRob Herring target-module@a0000 { /* 0x481a0000, ap 67 2c.0 */ 1292724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1293724ba675SRob Herring reg = <0xa0000 0x4>, 1294724ba675SRob Herring <0xa0110 0x4>, 1295724ba675SRob Herring <0xa0114 0x4>; 1296724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1297724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1298724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1299724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1300724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1301724ba675SRob Herring <SYSC_IDLE_NO>, 1302724ba675SRob Herring <SYSC_IDLE_SMART>; 1303724ba675SRob Herring ti,syss-mask = <1>; 1304724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1305724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_SPI1_CLKCTRL 0>; 1306724ba675SRob Herring clock-names = "fck"; 1307724ba675SRob Herring #address-cells = <1>; 1308724ba675SRob Herring #size-cells = <1>; 1309724ba675SRob Herring ranges = <0x0 0xa0000 0x1000>; 1310724ba675SRob Herring 1311724ba675SRob Herring spi1: spi@0 { 1312724ba675SRob Herring compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; 1313724ba675SRob Herring reg = <0x0 0x400>; 1314724ba675SRob Herring interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1315724ba675SRob Herring #address-cells = <1>; 1316724ba675SRob Herring #size-cells = <0>; 1317724ba675SRob Herring status = "disabled"; 1318724ba675SRob Herring }; 1319724ba675SRob Herring }; 1320724ba675SRob Herring 1321724ba675SRob Herring target-module@a2000 { /* 0x481a2000, ap 69 2e.0 */ 1322724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1323724ba675SRob Herring reg = <0xa2000 0x4>, 1324724ba675SRob Herring <0xa2110 0x4>, 1325724ba675SRob Herring <0xa2114 0x4>; 1326724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1327724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1328724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1329724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1330724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1331724ba675SRob Herring <SYSC_IDLE_NO>, 1332724ba675SRob Herring <SYSC_IDLE_SMART>; 1333724ba675SRob Herring ti,syss-mask = <1>; 1334724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1335724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_SPI2_CLKCTRL 0>; 1336724ba675SRob Herring clock-names = "fck"; 1337724ba675SRob Herring #address-cells = <1>; 1338724ba675SRob Herring #size-cells = <1>; 1339724ba675SRob Herring ranges = <0x0 0xa2000 0x1000>; 1340724ba675SRob Herring 1341724ba675SRob Herring spi2: spi@0 { 1342724ba675SRob Herring compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; 1343724ba675SRob Herring reg = <0x0 0x400>; 1344724ba675SRob Herring interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1345724ba675SRob Herring #address-cells = <1>; 1346724ba675SRob Herring #size-cells = <0>; 1347724ba675SRob Herring status = "disabled"; 1348724ba675SRob Herring }; 1349724ba675SRob Herring }; 1350724ba675SRob Herring 1351724ba675SRob Herring target-module@a4000 { /* 0x481a4000, ap 92 62.0 */ 1352724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1353724ba675SRob Herring reg = <0xa4000 0x4>, 1354724ba675SRob Herring <0xa4110 0x4>, 1355724ba675SRob Herring <0xa4114 0x4>; 1356724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1357724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1358724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1359724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1360724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1361724ba675SRob Herring <SYSC_IDLE_NO>, 1362724ba675SRob Herring <SYSC_IDLE_SMART>; 1363724ba675SRob Herring ti,syss-mask = <1>; 1364724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1365724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_SPI3_CLKCTRL 0>; 1366724ba675SRob Herring clock-names = "fck"; 1367724ba675SRob Herring #address-cells = <1>; 1368724ba675SRob Herring #size-cells = <1>; 1369724ba675SRob Herring ranges = <0x0 0xa4000 0x1000>; 1370724ba675SRob Herring 1371724ba675SRob Herring spi3: spi@0 { 1372724ba675SRob Herring compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; 1373724ba675SRob Herring reg = <0x0 0x400>; 1374724ba675SRob Herring interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1375724ba675SRob Herring #address-cells = <1>; 1376724ba675SRob Herring #size-cells = <0>; 1377724ba675SRob Herring status = "disabled"; 1378724ba675SRob Herring }; 1379724ba675SRob Herring }; 1380724ba675SRob Herring 1381724ba675SRob Herring target-module@a6000 { /* 0x481a6000, ap 40 16.0 */ 1382724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1383724ba675SRob Herring reg = <0xa6050 0x4>, 1384724ba675SRob Herring <0xa6054 0x4>, 1385724ba675SRob Herring <0xa6058 0x4>; 1386724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1387724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1388724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1389724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1390724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1391724ba675SRob Herring <SYSC_IDLE_NO>, 1392724ba675SRob Herring <SYSC_IDLE_SMART>, 1393724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1394724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1395724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_UART4_CLKCTRL 0>; 1396724ba675SRob Herring clock-names = "fck"; 1397724ba675SRob Herring #address-cells = <1>; 1398724ba675SRob Herring #size-cells = <1>; 1399724ba675SRob Herring ranges = <0x0 0xa6000 0x1000>; 1400724ba675SRob Herring 1401724ba675SRob Herring uart3: serial@0 { 1402724ba675SRob Herring compatible = "ti,am4372-uart"; 1403724ba675SRob Herring reg = <0x0 0x2000>; 1404724ba675SRob Herring interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1405724ba675SRob Herring status = "disabled"; 1406724ba675SRob Herring }; 1407724ba675SRob Herring }; 1408724ba675SRob Herring 1409724ba675SRob Herring target-module@a8000 { /* 0x481a8000, ap 42 20.0 */ 1410724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1411724ba675SRob Herring reg = <0xa8050 0x4>, 1412724ba675SRob Herring <0xa8054 0x4>, 1413724ba675SRob Herring <0xa8058 0x4>; 1414724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1415724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1416724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1417724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1418724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1419724ba675SRob Herring <SYSC_IDLE_NO>, 1420724ba675SRob Herring <SYSC_IDLE_SMART>, 1421724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1422724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1423724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_UART5_CLKCTRL 0>; 1424724ba675SRob Herring clock-names = "fck"; 1425724ba675SRob Herring #address-cells = <1>; 1426724ba675SRob Herring #size-cells = <1>; 1427724ba675SRob Herring ranges = <0x0 0xa8000 0x1000>; 1428724ba675SRob Herring 1429724ba675SRob Herring uart4: serial@0 { 1430724ba675SRob Herring compatible = "ti,am4372-uart"; 1431724ba675SRob Herring reg = <0x0 0x2000>; 1432724ba675SRob Herring interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1433724ba675SRob Herring status = "disabled"; 1434724ba675SRob Herring }; 1435724ba675SRob Herring }; 1436724ba675SRob Herring 1437724ba675SRob Herring target-module@aa000 { /* 0x481aa000, ap 44 12.0 */ 1438724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1439724ba675SRob Herring reg = <0xaa050 0x4>, 1440724ba675SRob Herring <0xaa054 0x4>, 1441724ba675SRob Herring <0xaa058 0x4>; 1442724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1443724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1444724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1445724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1446724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1447724ba675SRob Herring <SYSC_IDLE_NO>, 1448724ba675SRob Herring <SYSC_IDLE_SMART>, 1449724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1450724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1451724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_UART6_CLKCTRL 0>; 1452724ba675SRob Herring clock-names = "fck"; 1453724ba675SRob Herring #address-cells = <1>; 1454724ba675SRob Herring #size-cells = <1>; 1455724ba675SRob Herring ranges = <0x0 0xaa000 0x1000>; 1456724ba675SRob Herring 1457724ba675SRob Herring uart5: serial@0 { 1458724ba675SRob Herring compatible = "ti,am4372-uart"; 1459724ba675SRob Herring reg = <0x0 0x2000>; 1460724ba675SRob Herring interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1461724ba675SRob Herring status = "disabled"; 1462724ba675SRob Herring }; 1463724ba675SRob Herring }; 1464724ba675SRob Herring 1465724ba675SRob Herring target-module@ac000 { /* 0x481ac000, ap 46 30.0 */ 1466724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1467724ba675SRob Herring reg = <0xac000 0x4>, 1468724ba675SRob Herring <0xac010 0x4>, 1469724ba675SRob Herring <0xac114 0x4>; 1470724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1471724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1472724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1473724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1474724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1475724ba675SRob Herring <SYSC_IDLE_NO>, 1476724ba675SRob Herring <SYSC_IDLE_SMART>, 1477724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1478724ba675SRob Herring ti,syss-mask = <1>; 1479724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1480724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 0>, 1481724ba675SRob Herring <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 8>; 1482724ba675SRob Herring clock-names = "fck", "dbclk"; 1483724ba675SRob Herring #address-cells = <1>; 1484724ba675SRob Herring #size-cells = <1>; 1485724ba675SRob Herring ranges = <0x0 0xac000 0x1000>; 1486724ba675SRob Herring 1487724ba675SRob Herring gpio2: gpio@0 { 1488724ba675SRob Herring compatible = "ti,am4372-gpio","ti,omap4-gpio"; 1489724ba675SRob Herring reg = <0x0 0x1000>; 1490724ba675SRob Herring interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1491724ba675SRob Herring gpio-controller; 1492724ba675SRob Herring #gpio-cells = <2>; 1493724ba675SRob Herring interrupt-controller; 1494724ba675SRob Herring #interrupt-cells = <2>; 1495724ba675SRob Herring status = "disabled"; 1496724ba675SRob Herring }; 1497724ba675SRob Herring }; 1498724ba675SRob Herring 1499724ba675SRob Herring target-module@ae000 { /* 0x481ae000, ap 48 32.0 */ 1500724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1501724ba675SRob Herring reg = <0xae000 0x4>, 1502724ba675SRob Herring <0xae010 0x4>, 1503724ba675SRob Herring <0xae114 0x4>; 1504724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1505724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1506724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1507724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1508724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1509724ba675SRob Herring <SYSC_IDLE_NO>, 1510724ba675SRob Herring <SYSC_IDLE_SMART>, 1511724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1512724ba675SRob Herring ti,syss-mask = <1>; 1513724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1514724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 0>, 1515724ba675SRob Herring <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 8>; 1516724ba675SRob Herring clock-names = "fck", "dbclk"; 1517724ba675SRob Herring #address-cells = <1>; 1518724ba675SRob Herring #size-cells = <1>; 1519724ba675SRob Herring ranges = <0x0 0xae000 0x1000>; 1520724ba675SRob Herring 1521724ba675SRob Herring gpio3: gpio@0 { 1522724ba675SRob Herring compatible = "ti,am4372-gpio","ti,omap4-gpio"; 1523724ba675SRob Herring reg = <0x0 0x1000>; 1524724ba675SRob Herring interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1525724ba675SRob Herring gpio-controller; 1526724ba675SRob Herring #gpio-cells = <2>; 1527724ba675SRob Herring interrupt-controller; 1528724ba675SRob Herring #interrupt-cells = <2>; 1529724ba675SRob Herring status = "disabled"; 1530724ba675SRob Herring }; 1531724ba675SRob Herring }; 1532724ba675SRob Herring 1533724ba675SRob Herring target-module@c1000 { /* 0x481c1000, ap 94 68.0 */ 1534724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1535724ba675SRob Herring reg = <0xc1000 0x4>, 1536724ba675SRob Herring <0xc1010 0x4>, 1537724ba675SRob Herring <0xc1014 0x4>; 1538724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1539724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1540724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1541724ba675SRob Herring <SYSC_IDLE_NO>, 1542724ba675SRob Herring <SYSC_IDLE_SMART>, 1543724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1544724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1545724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_TIMER8_CLKCTRL 0>; 1546724ba675SRob Herring clock-names = "fck"; 1547724ba675SRob Herring #address-cells = <1>; 1548724ba675SRob Herring #size-cells = <1>; 1549724ba675SRob Herring ranges = <0x0 0xc1000 0x1000>; 1550724ba675SRob Herring 1551724ba675SRob Herring timer8: timer@0 { 1552724ba675SRob Herring compatible = "ti,am4372-timer","ti,am335x-timer"; 1553724ba675SRob Herring reg = <0x0 0x400>; 1554724ba675SRob Herring interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1555724ba675SRob Herring status = "disabled"; 1556724ba675SRob Herring }; 1557724ba675SRob Herring }; 1558724ba675SRob Herring 1559724ba675SRob Herring target-module@cc000 { /* 0x481cc000, ap 50 46.0 */ 1560724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 1561724ba675SRob Herring reg = <0xcc020 0x4>; 1562724ba675SRob Herring reg-names = "rev"; 1563724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1564724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>, 1565724ba675SRob Herring <&dcan0_fck>; 1566724ba675SRob Herring clock-names = "fck", "osc"; 1567724ba675SRob Herring #address-cells = <1>; 1568724ba675SRob Herring #size-cells = <1>; 1569724ba675SRob Herring ranges = <0x0 0xcc000 0x2000>; 1570724ba675SRob Herring 1571724ba675SRob Herring dcan0: can@0 { 1572724ba675SRob Herring compatible = "ti,am4372-d_can", "ti,am3352-d_can"; 1573724ba675SRob Herring reg = <0x0 0x2000>; 1574724ba675SRob Herring clocks = <&dcan0_fck>; 1575724ba675SRob Herring clock-names = "fck"; 1576724ba675SRob Herring syscon-raminit = <&scm_conf 0x644 0>; 1577724ba675SRob Herring interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1578724ba675SRob Herring status = "disabled"; 1579724ba675SRob Herring }; 1580724ba675SRob Herring }; 1581724ba675SRob Herring 1582724ba675SRob Herring target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */ 1583724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 1584724ba675SRob Herring reg = <0xd0020 0x4>; 1585724ba675SRob Herring reg-names = "rev"; 1586724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1587724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>, 1588724ba675SRob Herring <&dcan1_fck>; 1589724ba675SRob Herring clock-names = "fck", "osc"; 1590724ba675SRob Herring #address-cells = <1>; 1591724ba675SRob Herring #size-cells = <1>; 1592724ba675SRob Herring ranges = <0x0 0xd0000 0x2000>; 1593724ba675SRob Herring 1594724ba675SRob Herring dcan1: can@0 { 1595724ba675SRob Herring compatible = "ti,am4372-d_can", "ti,am3352-d_can"; 1596724ba675SRob Herring reg = <0x0 0x2000>; 1597724ba675SRob Herring clocks = <&dcan1_fck>; 1598724ba675SRob Herring clock-names = "fck"; 1599724ba675SRob Herring syscon-raminit = <&scm_conf 0x644 1>; 1600724ba675SRob Herring interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1601724ba675SRob Herring status = "disabled"; 1602724ba675SRob Herring }; 1603724ba675SRob Herring }; 1604724ba675SRob Herring 1605724ba675SRob Herring target-module@d8000 { /* 0x481d8000, ap 54 5e.0 */ 1606724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1607724ba675SRob Herring reg = <0xd82fc 0x4>, 1608724ba675SRob Herring <0xd8110 0x4>, 1609724ba675SRob Herring <0xd8114 0x4>; 1610724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1611724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1612724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 1613724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1614724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1615724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1616724ba675SRob Herring <SYSC_IDLE_NO>, 1617724ba675SRob Herring <SYSC_IDLE_SMART>; 1618724ba675SRob Herring ti,syss-mask = <1>; 1619724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1620724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_MMC2_CLKCTRL 0>; 1621724ba675SRob Herring clock-names = "fck"; 1622724ba675SRob Herring #address-cells = <1>; 1623724ba675SRob Herring #size-cells = <1>; 1624724ba675SRob Herring ranges = <0x0 0xd8000 0x1000>; 1625724ba675SRob Herring 1626724ba675SRob Herring mmc2: mmc@0 { 1627724ba675SRob Herring compatible = "ti,am437-sdhci"; 1628724ba675SRob Herring reg = <0x0 0x1000>; 1629724ba675SRob Herring ti,needs-special-reset; 1630724ba675SRob Herring dmas = <&edma 2 0>, 1631724ba675SRob Herring <&edma 3 0>; 1632724ba675SRob Herring dma-names = "tx", "rx"; 1633724ba675SRob Herring interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1634724ba675SRob Herring status = "disabled"; 1635724ba675SRob Herring }; 1636724ba675SRob Herring }; 1637724ba675SRob Herring }; 1638724ba675SRob Herring 1639724ba675SRob Herring segment@200000 { /* 0x48200000 */ 1640724ba675SRob Herring compatible = "simple-pm-bus"; 1641724ba675SRob Herring #address-cells = <1>; 1642724ba675SRob Herring #size-cells = <1>; 1643724ba675SRob Herring ranges = <0x00000000 0x00200000 0x010000>; 1644724ba675SRob Herring 1645724ba675SRob Herring target-module@0 { 1646724ba675SRob Herring compatible = "ti,sysc-omap4-simple", "ti,sysc"; 1647724ba675SRob Herring power-domains = <&prm_mpu>; 1648724ba675SRob Herring clocks = <&mpu_clkctrl AM4_MPU_MPU_CLKCTRL 0>; 1649724ba675SRob Herring clock-names = "fck"; 1650724ba675SRob Herring ti,no-idle; 1651724ba675SRob Herring #address-cells = <1>; 1652724ba675SRob Herring #size-cells = <1>; 1653724ba675SRob Herring ranges = <0 0 0x10000>; 1654724ba675SRob Herring 1655724ba675SRob Herring mpu@0 { 1656724ba675SRob Herring compatible = "ti,omap4-mpu"; 1657724ba675SRob Herring pm-sram = <&pm_sram_code 1658724ba675SRob Herring &pm_sram_data>; 1659724ba675SRob Herring }; 1660724ba675SRob Herring }; 1661724ba675SRob Herring }; 1662724ba675SRob Herring 1663724ba675SRob Herring segment@300000 { /* 0x48300000 */ 1664724ba675SRob Herring compatible = "simple-pm-bus"; 1665724ba675SRob Herring #address-cells = <1>; 1666724ba675SRob Herring #size-cells = <1>; 1667724ba675SRob Herring ranges = <0x00000000 0x00300000 0x001000>, /* ap 56 */ 1668724ba675SRob Herring <0x00001000 0x00301000 0x001000>, /* ap 57 */ 1669724ba675SRob Herring <0x00002000 0x00302000 0x001000>, /* ap 58 */ 1670724ba675SRob Herring <0x00003000 0x00303000 0x001000>, /* ap 59 */ 1671724ba675SRob Herring <0x00004000 0x00304000 0x001000>, /* ap 60 */ 1672724ba675SRob Herring <0x00005000 0x00305000 0x001000>, /* ap 61 */ 1673724ba675SRob Herring <0x00018000 0x00318000 0x004000>, /* ap 62 */ 1674724ba675SRob Herring <0x0001c000 0x0031c000 0x001000>, /* ap 63 */ 1675724ba675SRob Herring <0x00010000 0x00310000 0x002000>, /* ap 64 */ 1676724ba675SRob Herring <0x00028000 0x00328000 0x001000>, /* ap 75 */ 1677724ba675SRob Herring <0x00029000 0x00329000 0x001000>, /* ap 76 */ 1678724ba675SRob Herring <0x00012000 0x00312000 0x001000>, /* ap 79 */ 1679724ba675SRob Herring <0x00020000 0x00320000 0x001000>, /* ap 82 */ 1680724ba675SRob Herring <0x00021000 0x00321000 0x001000>, /* ap 83 */ 1681724ba675SRob Herring <0x00026000 0x00326000 0x001000>, /* ap 86 */ 1682724ba675SRob Herring <0x00027000 0x00327000 0x001000>, /* ap 87 */ 1683724ba675SRob Herring <0x0002a000 0x0032a000 0x000400>, /* ap 88 */ 1684724ba675SRob Herring <0x0002c000 0x0032c000 0x001000>, /* ap 89 */ 1685724ba675SRob Herring <0x00013000 0x00313000 0x001000>, /* ap 90 */ 1686724ba675SRob Herring <0x00014000 0x00314000 0x001000>, /* ap 91 */ 1687724ba675SRob Herring <0x00006000 0x00306000 0x001000>, /* ap 96 */ 1688724ba675SRob Herring <0x00007000 0x00307000 0x001000>, /* ap 97 */ 1689724ba675SRob Herring <0x00008000 0x00308000 0x001000>, /* ap 98 */ 1690724ba675SRob Herring <0x00009000 0x00309000 0x001000>, /* ap 99 */ 1691724ba675SRob Herring <0x0000a000 0x0030a000 0x001000>, /* ap 100 */ 1692724ba675SRob Herring <0x0000b000 0x0030b000 0x001000>, /* ap 101 */ 1693724ba675SRob Herring <0x0003d000 0x0033d000 0x001000>, /* ap 102 */ 1694724ba675SRob Herring <0x0003e000 0x0033e000 0x001000>, /* ap 103 */ 1695724ba675SRob Herring <0x0003f000 0x0033f000 0x001000>, /* ap 104 */ 1696724ba675SRob Herring <0x00040000 0x00340000 0x001000>, /* ap 105 */ 1697724ba675SRob Herring <0x00041000 0x00341000 0x001000>, /* ap 106 */ 1698724ba675SRob Herring <0x00042000 0x00342000 0x001000>, /* ap 107 */ 1699724ba675SRob Herring <0x00045000 0x00345000 0x001000>, /* ap 108 */ 1700724ba675SRob Herring <0x00046000 0x00346000 0x001000>, /* ap 109 */ 1701724ba675SRob Herring <0x00047000 0x00347000 0x001000>, /* ap 110 */ 1702724ba675SRob Herring <0x00048000 0x00348000 0x001000>, /* ap 111 */ 1703724ba675SRob Herring <0x000f2000 0x003f2000 0x002000>, /* ap 112 */ 1704724ba675SRob Herring <0x000f4000 0x003f4000 0x001000>, /* ap 113 */ 1705724ba675SRob Herring <0x0004c000 0x0034c000 0x002000>, /* ap 114 */ 1706724ba675SRob Herring <0x0004e000 0x0034e000 0x001000>, /* ap 115 */ 1707724ba675SRob Herring <0x00022000 0x00322000 0x001000>, /* ap 116 */ 1708724ba675SRob Herring <0x00023000 0x00323000 0x001000>, /* ap 117 */ 1709724ba675SRob Herring <0x000f0000 0x003f0000 0x001000>, /* ap 118 */ 1710724ba675SRob Herring <0x0002a400 0x0032a400 0x000400>, /* ap 119 */ 1711724ba675SRob Herring <0x0002a800 0x0032a800 0x000400>, /* ap 120 */ 1712724ba675SRob Herring <0x0002ac00 0x0032ac00 0x000400>, /* ap 121 */ 1713724ba675SRob Herring <0x0002b000 0x0032b000 0x001000>, /* ap 122 */ 1714724ba675SRob Herring <0x00080000 0x00380000 0x020000>, /* ap 123 */ 1715724ba675SRob Herring <0x000a0000 0x003a0000 0x001000>, /* ap 124 */ 1716724ba675SRob Herring <0x000a8000 0x003a8000 0x008000>, /* ap 125 */ 1717724ba675SRob Herring <0x000b0000 0x003b0000 0x001000>, /* ap 126 */ 1718724ba675SRob Herring <0x000c0000 0x003c0000 0x020000>, /* ap 127 */ 1719724ba675SRob Herring <0x000e0000 0x003e0000 0x001000>, /* ap 128 */ 1720724ba675SRob Herring <0x000e8000 0x003e8000 0x008000>; /* ap 129 */ 1721724ba675SRob Herring 1722724ba675SRob Herring target-module@0 { /* 0x48300000, ap 56 40.0 */ 1723724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 1724724ba675SRob Herring reg = <0x0 0x4>, 1725724ba675SRob Herring <0x4 0x4>; 1726724ba675SRob Herring reg-names = "rev", "sysc"; 1727724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 1728724ba675SRob Herring <SYSC_IDLE_NO>, 1729724ba675SRob Herring <SYSC_IDLE_SMART>, 1730724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1731724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1732724ba675SRob Herring <SYSC_IDLE_NO>, 1733724ba675SRob Herring <SYSC_IDLE_SMART>, 1734724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1735724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1736724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS0_CLKCTRL 0>; 1737724ba675SRob Herring clock-names = "fck"; 1738724ba675SRob Herring #address-cells = <1>; 1739724ba675SRob Herring #size-cells = <1>; 1740724ba675SRob Herring ranges = <0x0 0x0 0x1000>; 1741724ba675SRob Herring 1742724ba675SRob Herring epwmss0: epwmss@0 { 1743724ba675SRob Herring compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 1744724ba675SRob Herring reg = <0x0 0x10>; 1745724ba675SRob Herring #address-cells = <1>; 1746724ba675SRob Herring #size-cells = <1>; 1747724ba675SRob Herring ranges = <0 0 0x1000>; 1748724ba675SRob Herring status = "disabled"; 1749724ba675SRob Herring 1750724ba675SRob Herring ecap0: pwm@100 { 1751724ba675SRob Herring compatible = "ti,am4372-ecap", 1752724ba675SRob Herring "ti,am3352-ecap"; 1753724ba675SRob Herring #pwm-cells = <3>; 1754724ba675SRob Herring reg = <0x100 0x80>; 1755724ba675SRob Herring clocks = <&l4ls_gclk>; 1756724ba675SRob Herring clock-names = "fck"; 1757724ba675SRob Herring status = "disabled"; 1758724ba675SRob Herring }; 1759724ba675SRob Herring 1760724ba675SRob Herring ehrpwm0: pwm@200 { 1761724ba675SRob Herring compatible = "ti,am4372-ehrpwm", 1762724ba675SRob Herring "ti,am3352-ehrpwm"; 1763724ba675SRob Herring #pwm-cells = <3>; 1764724ba675SRob Herring reg = <0x200 0x80>; 1765724ba675SRob Herring clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; 1766724ba675SRob Herring clock-names = "tbclk", "fck"; 1767724ba675SRob Herring status = "disabled"; 1768724ba675SRob Herring }; 1769724ba675SRob Herring }; 1770724ba675SRob Herring }; 1771724ba675SRob Herring 1772724ba675SRob Herring target-module@2000 { /* 0x48302000, ap 58 4a.0 */ 1773724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 1774724ba675SRob Herring reg = <0x2000 0x4>, 1775724ba675SRob Herring <0x2004 0x4>; 1776724ba675SRob Herring reg-names = "rev", "sysc"; 1777724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 1778724ba675SRob Herring <SYSC_IDLE_NO>, 1779724ba675SRob Herring <SYSC_IDLE_SMART>, 1780724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1781724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1782724ba675SRob Herring <SYSC_IDLE_NO>, 1783724ba675SRob Herring <SYSC_IDLE_SMART>, 1784724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1785724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1786724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS1_CLKCTRL 0>; 1787724ba675SRob Herring clock-names = "fck"; 1788724ba675SRob Herring #address-cells = <1>; 1789724ba675SRob Herring #size-cells = <1>; 1790724ba675SRob Herring ranges = <0x0 0x2000 0x1000>; 1791724ba675SRob Herring 1792724ba675SRob Herring epwmss1: epwmss@0 { 1793724ba675SRob Herring compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 1794724ba675SRob Herring reg = <0x0 0x10>; 1795724ba675SRob Herring #address-cells = <1>; 1796724ba675SRob Herring #size-cells = <1>; 1797724ba675SRob Herring ranges = <0 0 0x1000>; 1798724ba675SRob Herring status = "disabled"; 1799724ba675SRob Herring 1800724ba675SRob Herring ecap1: pwm@100 { 1801724ba675SRob Herring compatible = "ti,am4372-ecap", 1802724ba675SRob Herring "ti,am3352-ecap"; 1803724ba675SRob Herring #pwm-cells = <3>; 1804724ba675SRob Herring reg = <0x100 0x80>; 1805724ba675SRob Herring clocks = <&l4ls_gclk>; 1806724ba675SRob Herring clock-names = "fck"; 1807724ba675SRob Herring status = "disabled"; 1808724ba675SRob Herring }; 1809724ba675SRob Herring 1810724ba675SRob Herring ehrpwm1: pwm@200 { 1811724ba675SRob Herring compatible = "ti,am4372-ehrpwm", 1812724ba675SRob Herring "ti,am3352-ehrpwm"; 1813724ba675SRob Herring #pwm-cells = <3>; 1814724ba675SRob Herring reg = <0x200 0x80>; 1815724ba675SRob Herring clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; 1816724ba675SRob Herring clock-names = "tbclk", "fck"; 1817724ba675SRob Herring status = "disabled"; 1818724ba675SRob Herring }; 1819724ba675SRob Herring }; 1820724ba675SRob Herring }; 1821724ba675SRob Herring 1822724ba675SRob Herring target-module@4000 { /* 0x48304000, ap 60 44.0 */ 1823724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 1824724ba675SRob Herring reg = <0x4000 0x4>, 1825724ba675SRob Herring <0x4004 0x4>; 1826724ba675SRob Herring reg-names = "rev", "sysc"; 1827724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 1828724ba675SRob Herring <SYSC_IDLE_NO>, 1829724ba675SRob Herring <SYSC_IDLE_SMART>, 1830724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1831724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1832724ba675SRob Herring <SYSC_IDLE_NO>, 1833724ba675SRob Herring <SYSC_IDLE_SMART>, 1834724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1835724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1836724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS2_CLKCTRL 0>; 1837724ba675SRob Herring clock-names = "fck"; 1838724ba675SRob Herring #address-cells = <1>; 1839724ba675SRob Herring #size-cells = <1>; 1840724ba675SRob Herring ranges = <0x0 0x4000 0x1000>; 1841724ba675SRob Herring 1842724ba675SRob Herring epwmss2: epwmss@0 { 1843724ba675SRob Herring compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 1844724ba675SRob Herring reg = <0x0 0x10>; 1845724ba675SRob Herring #address-cells = <1>; 1846724ba675SRob Herring #size-cells = <1>; 1847724ba675SRob Herring ranges = <0 0 0x1000>; 1848724ba675SRob Herring status = "disabled"; 1849724ba675SRob Herring 1850724ba675SRob Herring ecap2: pwm@100 { 1851724ba675SRob Herring compatible = "ti,am4372-ecap", 1852724ba675SRob Herring "ti,am3352-ecap"; 1853724ba675SRob Herring #pwm-cells = <3>; 1854724ba675SRob Herring reg = <0x100 0x80>; 1855724ba675SRob Herring clocks = <&l4ls_gclk>; 1856724ba675SRob Herring clock-names = "fck"; 1857724ba675SRob Herring status = "disabled"; 1858724ba675SRob Herring }; 1859724ba675SRob Herring 1860724ba675SRob Herring ehrpwm2: pwm@200 { 1861724ba675SRob Herring compatible = "ti,am4372-ehrpwm", 1862724ba675SRob Herring "ti,am3352-ehrpwm"; 1863724ba675SRob Herring #pwm-cells = <3>; 1864724ba675SRob Herring reg = <0x200 0x80>; 1865724ba675SRob Herring clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; 1866724ba675SRob Herring clock-names = "tbclk", "fck"; 1867724ba675SRob Herring status = "disabled"; 1868724ba675SRob Herring }; 1869724ba675SRob Herring }; 1870724ba675SRob Herring }; 1871724ba675SRob Herring 1872724ba675SRob Herring target-module@6000 { /* 0x48306000, ap 96 58.0 */ 1873724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 1874724ba675SRob Herring reg = <0x6000 0x4>, 1875724ba675SRob Herring <0x6004 0x4>; 1876724ba675SRob Herring reg-names = "rev", "sysc"; 1877724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 1878724ba675SRob Herring <SYSC_IDLE_NO>, 1879724ba675SRob Herring <SYSC_IDLE_SMART>, 1880724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1881724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1882724ba675SRob Herring <SYSC_IDLE_NO>, 1883724ba675SRob Herring <SYSC_IDLE_SMART>, 1884724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1885724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1886724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS3_CLKCTRL 0>; 1887724ba675SRob Herring clock-names = "fck"; 1888724ba675SRob Herring #address-cells = <1>; 1889724ba675SRob Herring #size-cells = <1>; 1890724ba675SRob Herring ranges = <0x0 0x6000 0x1000>; 1891724ba675SRob Herring 1892724ba675SRob Herring epwmss3: epwmss@0 { 1893724ba675SRob Herring compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 1894724ba675SRob Herring reg = <0x0 0x10>; 1895724ba675SRob Herring #address-cells = <1>; 1896724ba675SRob Herring #size-cells = <1>; 1897724ba675SRob Herring ranges = <0 0 0x1000>; 1898724ba675SRob Herring status = "disabled"; 1899724ba675SRob Herring 1900724ba675SRob Herring ehrpwm3: pwm@200 { 1901724ba675SRob Herring compatible = "ti,am4372-ehrpwm", 1902724ba675SRob Herring "ti,am3352-ehrpwm"; 1903724ba675SRob Herring #pwm-cells = <3>; 1904724ba675SRob Herring reg = <0x200 0x80>; 1905724ba675SRob Herring clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>; 1906724ba675SRob Herring clock-names = "tbclk", "fck"; 1907724ba675SRob Herring status = "disabled"; 1908724ba675SRob Herring }; 1909724ba675SRob Herring }; 1910724ba675SRob Herring }; 1911724ba675SRob Herring 1912724ba675SRob Herring target-module@8000 { /* 0x48308000, ap 98 54.0 */ 1913724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 1914724ba675SRob Herring reg = <0x8000 0x4>, 1915724ba675SRob Herring <0x8004 0x4>; 1916724ba675SRob Herring reg-names = "rev", "sysc"; 1917724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 1918724ba675SRob Herring <SYSC_IDLE_NO>, 1919724ba675SRob Herring <SYSC_IDLE_SMART>, 1920724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1921724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1922724ba675SRob Herring <SYSC_IDLE_NO>, 1923724ba675SRob Herring <SYSC_IDLE_SMART>, 1924724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1925724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1926724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS4_CLKCTRL 0>; 1927724ba675SRob Herring clock-names = "fck"; 1928724ba675SRob Herring #address-cells = <1>; 1929724ba675SRob Herring #size-cells = <1>; 1930724ba675SRob Herring ranges = <0x0 0x8000 0x1000>; 1931724ba675SRob Herring 1932724ba675SRob Herring epwmss4: epwmss@0 { 1933724ba675SRob Herring compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 1934724ba675SRob Herring reg = <0x0 0x10>; 1935724ba675SRob Herring #address-cells = <1>; 1936724ba675SRob Herring #size-cells = <1>; 1937724ba675SRob Herring ranges = <0 0 0x1000>; 1938724ba675SRob Herring status = "disabled"; 1939724ba675SRob Herring 1940724ba675SRob Herring ehrpwm4: pwm@48308200 { 1941724ba675SRob Herring compatible = "ti,am4372-ehrpwm", 1942724ba675SRob Herring "ti,am3352-ehrpwm"; 1943724ba675SRob Herring #pwm-cells = <3>; 1944724ba675SRob Herring reg = <0x200 0x80>; 1945724ba675SRob Herring clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>; 1946724ba675SRob Herring clock-names = "tbclk", "fck"; 1947724ba675SRob Herring status = "disabled"; 1948724ba675SRob Herring }; 1949724ba675SRob Herring }; 1950724ba675SRob Herring }; 1951724ba675SRob Herring 1952724ba675SRob Herring target-module@a000 { /* 0x4830a000, ap 100 60.0 */ 1953724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 1954724ba675SRob Herring reg = <0xa000 0x4>, 1955724ba675SRob Herring <0xa004 0x4>; 1956724ba675SRob Herring reg-names = "rev", "sysc"; 1957724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 1958724ba675SRob Herring <SYSC_IDLE_NO>, 1959724ba675SRob Herring <SYSC_IDLE_SMART>, 1960724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1961724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1962724ba675SRob Herring <SYSC_IDLE_NO>, 1963724ba675SRob Herring <SYSC_IDLE_SMART>, 1964724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1965724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1966724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS5_CLKCTRL 0>; 1967724ba675SRob Herring clock-names = "fck"; 1968724ba675SRob Herring #address-cells = <1>; 1969724ba675SRob Herring #size-cells = <1>; 1970724ba675SRob Herring ranges = <0x0 0xa000 0x1000>; 1971724ba675SRob Herring 1972724ba675SRob Herring epwmss5: epwmss@0 { 1973724ba675SRob Herring compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 1974724ba675SRob Herring reg = <0x0 0x10>; 1975724ba675SRob Herring #address-cells = <1>; 1976724ba675SRob Herring #size-cells = <1>; 1977724ba675SRob Herring ranges = <0 0 0x1000>; 1978724ba675SRob Herring status = "disabled"; 1979724ba675SRob Herring 1980724ba675SRob Herring ehrpwm5: pwm@200 { 1981724ba675SRob Herring compatible = "ti,am4372-ehrpwm", 1982724ba675SRob Herring "ti,am3352-ehrpwm"; 1983724ba675SRob Herring #pwm-cells = <3>; 1984724ba675SRob Herring reg = <0x200 0x80>; 1985724ba675SRob Herring clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>; 1986724ba675SRob Herring clock-names = "tbclk", "fck"; 1987724ba675SRob Herring status = "disabled"; 1988724ba675SRob Herring }; 1989724ba675SRob Herring }; 1990724ba675SRob Herring }; 1991724ba675SRob Herring 1992724ba675SRob Herring target-module@10000 { /* 0x48310000, ap 64 4e.1 */ 1993724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1994724ba675SRob Herring reg = <0x11fe0 0x4>, 1995724ba675SRob Herring <0x11fe4 0x4>; 1996724ba675SRob Herring reg-names = "rev", "sysc"; 1997724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>; 1998724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1999724ba675SRob Herring <SYSC_IDLE_NO>; 2000724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2001724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_RNG_CLKCTRL 0>; 2002724ba675SRob Herring clock-names = "fck"; 2003724ba675SRob Herring #address-cells = <1>; 2004724ba675SRob Herring #size-cells = <1>; 2005724ba675SRob Herring ranges = <0x0 0x10000 0x2000>; 2006724ba675SRob Herring 2007724ba675SRob Herring rng: rng@0 { 2008724ba675SRob Herring compatible = "ti,omap4-rng"; 2009724ba675SRob Herring reg = <0x0 0x2000>; 2010724ba675SRob Herring interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 2011724ba675SRob Herring }; 2012724ba675SRob Herring }; 2013724ba675SRob Herring 2014724ba675SRob Herring target-module@13000 { /* 0x48313000, ap 90 50.0 */ 2015724ba675SRob Herring compatible = "ti,sysc"; 2016724ba675SRob Herring status = "disabled"; 2017724ba675SRob Herring #address-cells = <1>; 2018724ba675SRob Herring #size-cells = <1>; 2019724ba675SRob Herring ranges = <0x0 0x13000 0x1000>; 2020724ba675SRob Herring }; 2021724ba675SRob Herring 2022724ba675SRob Herring target-module@18000 { /* 0x48318000, ap 62 4c.0 */ 2023724ba675SRob Herring compatible = "ti,sysc"; 2024724ba675SRob Herring status = "disabled"; 2025724ba675SRob Herring #address-cells = <1>; 2026724ba675SRob Herring #size-cells = <1>; 2027724ba675SRob Herring ranges = <0x0 0x18000 0x4000>; 2028724ba675SRob Herring }; 2029724ba675SRob Herring 2030724ba675SRob Herring target-module@20000 { /* 0x48320000, ap 82 34.0 */ 2031724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 2032724ba675SRob Herring reg = <0x20000 0x4>, 2033724ba675SRob Herring <0x20010 0x4>, 2034724ba675SRob Herring <0x20114 0x4>; 2035724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 2036724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 2037724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 2038724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 2039724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2040724ba675SRob Herring <SYSC_IDLE_NO>, 2041724ba675SRob Herring <SYSC_IDLE_SMART>, 2042724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2043724ba675SRob Herring ti,syss-mask = <1>; 2044724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2045724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 0>, 2046724ba675SRob Herring <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 8>; 2047724ba675SRob Herring clock-names = "fck", "dbclk"; 2048724ba675SRob Herring #address-cells = <1>; 2049724ba675SRob Herring #size-cells = <1>; 2050724ba675SRob Herring ranges = <0x0 0x20000 0x1000>; 2051724ba675SRob Herring 2052724ba675SRob Herring gpio4: gpio@0 { 2053724ba675SRob Herring compatible = "ti,am4372-gpio","ti,omap4-gpio"; 2054724ba675SRob Herring reg = <0x0 0x1000>; 2055724ba675SRob Herring interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2056724ba675SRob Herring gpio-controller; 2057724ba675SRob Herring #gpio-cells = <2>; 2058724ba675SRob Herring interrupt-controller; 2059724ba675SRob Herring #interrupt-cells = <2>; 2060724ba675SRob Herring status = "disabled"; 2061724ba675SRob Herring }; 2062724ba675SRob Herring }; 2063724ba675SRob Herring 2064724ba675SRob Herring gpio5_target: target-module@22000 { /* 0x48322000, ap 116 64.0 */ 2065724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 2066724ba675SRob Herring reg = <0x22000 0x4>, 2067724ba675SRob Herring <0x22010 0x4>, 2068724ba675SRob Herring <0x22114 0x4>; 2069724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 2070724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 2071724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 2072724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 2073724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2074724ba675SRob Herring <SYSC_IDLE_NO>, 2075724ba675SRob Herring <SYSC_IDLE_SMART>, 2076724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2077724ba675SRob Herring ti,syss-mask = <1>; 2078724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2079724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 0>, 2080724ba675SRob Herring <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 8>; 2081724ba675SRob Herring clock-names = "fck", "dbclk"; 2082724ba675SRob Herring #address-cells = <1>; 2083724ba675SRob Herring #size-cells = <1>; 2084724ba675SRob Herring ranges = <0x0 0x22000 0x1000>; 2085724ba675SRob Herring 2086724ba675SRob Herring gpio5: gpio@0 { 2087724ba675SRob Herring compatible = "ti,am4372-gpio","ti,omap4-gpio"; 2088724ba675SRob Herring reg = <0x0 0x1000>; 2089724ba675SRob Herring interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2090724ba675SRob Herring gpio-controller; 2091724ba675SRob Herring #gpio-cells = <2>; 2092724ba675SRob Herring interrupt-controller; 2093724ba675SRob Herring #interrupt-cells = <2>; 2094724ba675SRob Herring status = "disabled"; 2095724ba675SRob Herring }; 2096724ba675SRob Herring }; 2097724ba675SRob Herring 2098724ba675SRob Herring target-module@26000 { /* 0x48326000, ap 86 66.0 */ 2099724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 2100724ba675SRob Herring reg = <0x26000 0x4>, 2101724ba675SRob Herring <0x26104 0x4>; 2102724ba675SRob Herring reg-names = "rev", "sysc"; 2103724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 2104724ba675SRob Herring <SYSC_IDLE_NO>, 2105724ba675SRob Herring <SYSC_IDLE_SMART>; 2106724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2107724ba675SRob Herring <SYSC_IDLE_NO>, 2108724ba675SRob Herring <SYSC_IDLE_SMART>; 2109724ba675SRob Herring /* Domains (P, C): per_pwrdm, l3s_clkdm */ 2110724ba675SRob Herring clocks = <&l3s_clkctrl AM4_L3S_VPFE0_CLKCTRL 0>; 2111724ba675SRob Herring clock-names = "fck"; 2112724ba675SRob Herring #address-cells = <1>; 2113724ba675SRob Herring #size-cells = <1>; 2114724ba675SRob Herring ranges = <0x0 0x26000 0x1000>; 2115724ba675SRob Herring 2116724ba675SRob Herring vpfe0: vpfe@0 { 2117724ba675SRob Herring compatible = "ti,am437x-vpfe"; 2118724ba675SRob Herring reg = <0x0 0x2000>; 2119724ba675SRob Herring interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 2120724ba675SRob Herring status = "disabled"; 2121724ba675SRob Herring }; 2122724ba675SRob Herring }; 2123724ba675SRob Herring 2124724ba675SRob Herring target-module@28000 { /* 0x48328000, ap 75 0e.0 */ 2125724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 2126724ba675SRob Herring reg = <0x28000 0x4>, 2127724ba675SRob Herring <0x28104 0x4>; 2128724ba675SRob Herring reg-names = "rev", "sysc"; 2129724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 2130724ba675SRob Herring <SYSC_IDLE_NO>, 2131724ba675SRob Herring <SYSC_IDLE_SMART>; 2132724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2133724ba675SRob Herring <SYSC_IDLE_NO>, 2134724ba675SRob Herring <SYSC_IDLE_SMART>; 2135724ba675SRob Herring /* Domains (P, C): per_pwrdm, l3s_clkdm */ 2136724ba675SRob Herring clocks = <&l3s_clkctrl AM4_L3S_VPFE1_CLKCTRL 0>; 2137724ba675SRob Herring clock-names = "fck"; 2138724ba675SRob Herring #address-cells = <1>; 2139724ba675SRob Herring #size-cells = <1>; 2140724ba675SRob Herring ranges = <0x0 0x28000 0x1000>; 2141724ba675SRob Herring 2142724ba675SRob Herring vpfe1: vpfe@0 { 2143724ba675SRob Herring compatible = "ti,am437x-vpfe"; 2144724ba675SRob Herring reg = <0x0 0x2000>; 2145724ba675SRob Herring interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 2146724ba675SRob Herring status = "disabled"; 2147724ba675SRob Herring }; 2148724ba675SRob Herring }; 2149724ba675SRob Herring 2150724ba675SRob Herring target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */ 2151724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 2152724ba675SRob Herring reg = <0x2a000 0x4>, 2153724ba675SRob Herring <0x2a010 0x4>, 2154724ba675SRob Herring <0x2a014 0x4>; 2155724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 2156724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 2157724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 2158724ba675SRob Herring ti,syss-mask = <1>; 2159724ba675SRob Herring /* Domains (P, C): per_pwrdm, dss_clkdm */ 2160724ba675SRob Herring clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; 2161724ba675SRob Herring clock-names = "fck"; 2162724ba675SRob Herring #address-cells = <1>; 2163724ba675SRob Herring #size-cells = <1>; 2164724ba675SRob Herring ranges = <0x00000000 0x0002a000 0x00000400>, 2165724ba675SRob Herring <0x00000400 0x0002a400 0x00000400>, 2166724ba675SRob Herring <0x00000800 0x0002a800 0x00000400>, 2167724ba675SRob Herring <0x00000c00 0x0002ac00 0x00000400>, 2168724ba675SRob Herring <0x00001000 0x0002b000 0x00001000>; 2169724ba675SRob Herring 2170724ba675SRob Herring dss: dss@0 { 2171724ba675SRob Herring compatible = "ti,omap3-dss"; 2172724ba675SRob Herring reg = <0 0x200>; 2173724ba675SRob Herring status = "disabled"; 2174724ba675SRob Herring clocks = <&disp_clk>; 2175724ba675SRob Herring clock-names = "fck"; 2176724ba675SRob Herring #address-cells = <1>; 2177724ba675SRob Herring #size-cells = <1>; 2178724ba675SRob Herring ranges = <0x00000000 0x00000000 0x00000400>, 2179724ba675SRob Herring <0x00000400 0x00000400 0x00000400>, 2180724ba675SRob Herring <0x00000800 0x00000800 0x00000400>, 2181724ba675SRob Herring <0x00000c00 0x00000c00 0x00000400>, 2182724ba675SRob Herring <0x00001000 0x00001000 0x00001000>; 2183724ba675SRob Herring 2184724ba675SRob Herring target-module@400 { 2185724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 2186724ba675SRob Herring reg = <0x400 0x4>, 2187724ba675SRob Herring <0x410 0x4>, 2188724ba675SRob Herring <0x414 0x4>; 2189724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 2190724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2191724ba675SRob Herring <SYSC_IDLE_NO>, 2192724ba675SRob Herring <SYSC_IDLE_SMART>; 2193724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 2194724ba675SRob Herring <SYSC_IDLE_NO>, 2195724ba675SRob Herring <SYSC_IDLE_SMART>; 2196724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 2197724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 2198724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 2199724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 2200724ba675SRob Herring ti,syss-mask = <1>; 2201724ba675SRob Herring clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; 2202724ba675SRob Herring clock-names = "fck"; 2203724ba675SRob Herring #address-cells = <1>; 2204724ba675SRob Herring #size-cells = <1>; 2205724ba675SRob Herring ranges = <0 0x400 0x400>; 2206724ba675SRob Herring 2207724ba675SRob Herring dispc: dispc@0 { 2208724ba675SRob Herring compatible = "ti,omap3-dispc"; 2209724ba675SRob Herring reg = <0 0x400>; 2210724ba675SRob Herring interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 2211724ba675SRob Herring clocks = <&disp_clk>; 2212724ba675SRob Herring clock-names = "fck"; 2213724ba675SRob Herring 2214724ba675SRob Herring max-memory-bandwidth = <230000000>; 2215724ba675SRob Herring }; 2216724ba675SRob Herring }; 2217724ba675SRob Herring 2218724ba675SRob Herring target-module@800 { 2219724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 2220724ba675SRob Herring reg = <0x800 0x4>, 2221724ba675SRob Herring <0x810 0x4>, 2222724ba675SRob Herring <0x814 0x4>; 2223724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 2224724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2225724ba675SRob Herring <SYSC_IDLE_NO>, 2226724ba675SRob Herring <SYSC_IDLE_SMART>; 2227724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 2228724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 2229724ba675SRob Herring ti,syss-mask = <1>; 2230724ba675SRob Herring clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; 2231724ba675SRob Herring clock-names = "fck"; 2232724ba675SRob Herring #address-cells = <1>; 2233724ba675SRob Herring #size-cells = <1>; 2234724ba675SRob Herring ranges = <0 0x800 0x400>; 2235724ba675SRob Herring 2236724ba675SRob Herring rfbi: rfbi@0 { 2237724ba675SRob Herring compatible = "ti,omap3-rfbi"; 2238724ba675SRob Herring reg = <0 0x100>; 2239724ba675SRob Herring clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; 2240724ba675SRob Herring clock-names = "fck"; 2241724ba675SRob Herring status = "disabled"; 2242724ba675SRob Herring }; 2243724ba675SRob Herring }; 2244724ba675SRob Herring }; 2245724ba675SRob Herring }; 2246724ba675SRob Herring 2247724ba675SRob Herring target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */ 2248724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc"; 2249724ba675SRob Herring reg = <0x3d000 0x4>, 2250724ba675SRob Herring <0x3d010 0x4>, 2251724ba675SRob Herring <0x3d014 0x4>; 2252724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 2253724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 2254724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2255724ba675SRob Herring <SYSC_IDLE_NO>, 2256724ba675SRob Herring <SYSC_IDLE_SMART>, 2257724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2258724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2259724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_TIMER9_CLKCTRL 0>; 2260724ba675SRob Herring clock-names = "fck"; 2261724ba675SRob Herring #address-cells = <1>; 2262724ba675SRob Herring #size-cells = <1>; 2263724ba675SRob Herring ranges = <0x0 0x3d000 0x1000>; 2264724ba675SRob Herring 2265724ba675SRob Herring timer9: timer@0 { 2266724ba675SRob Herring compatible = "ti,am4372-timer","ti,am335x-timer"; 2267724ba675SRob Herring reg = <0x0 0x400>; 2268724ba675SRob Herring interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 2269724ba675SRob Herring status = "disabled"; 2270724ba675SRob Herring }; 2271724ba675SRob Herring }; 2272724ba675SRob Herring 2273724ba675SRob Herring target-module@3f000 { /* 0x4833f000, ap 104 5c.0 */ 2274724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc"; 2275724ba675SRob Herring reg = <0x3f000 0x4>, 2276724ba675SRob Herring <0x3f010 0x4>, 2277724ba675SRob Herring <0x3f014 0x4>; 2278724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 2279724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 2280724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2281724ba675SRob Herring <SYSC_IDLE_NO>, 2282724ba675SRob Herring <SYSC_IDLE_SMART>, 2283724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2284724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2285724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_TIMER10_CLKCTRL 0>; 2286724ba675SRob Herring clock-names = "fck"; 2287724ba675SRob Herring #address-cells = <1>; 2288724ba675SRob Herring #size-cells = <1>; 2289724ba675SRob Herring ranges = <0x0 0x3f000 0x1000>; 2290724ba675SRob Herring 2291724ba675SRob Herring timer10: timer@0 { 2292724ba675SRob Herring compatible = "ti,am4372-timer","ti,am335x-timer"; 2293724ba675SRob Herring reg = <0x0 0x400>; 2294724ba675SRob Herring interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2295724ba675SRob Herring status = "disabled"; 2296724ba675SRob Herring }; 2297724ba675SRob Herring }; 2298724ba675SRob Herring 2299724ba675SRob Herring target-module@41000 { /* 0x48341000, ap 106 76.0 */ 2300724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc"; 2301724ba675SRob Herring reg = <0x41000 0x4>, 2302724ba675SRob Herring <0x41010 0x4>, 2303724ba675SRob Herring <0x41014 0x4>; 2304724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 2305724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 2306724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2307724ba675SRob Herring <SYSC_IDLE_NO>, 2308724ba675SRob Herring <SYSC_IDLE_SMART>, 2309724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2310724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2311724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_TIMER11_CLKCTRL 0>; 2312724ba675SRob Herring clock-names = "fck"; 2313724ba675SRob Herring #address-cells = <1>; 2314724ba675SRob Herring #size-cells = <1>; 2315724ba675SRob Herring ranges = <0x0 0x41000 0x1000>; 2316724ba675SRob Herring 2317724ba675SRob Herring timer11: timer@0 { 2318724ba675SRob Herring compatible = "ti,am4372-timer","ti,am335x-timer"; 2319724ba675SRob Herring reg = <0x0 0x400>; 2320724ba675SRob Herring interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 2321724ba675SRob Herring status = "disabled"; 2322724ba675SRob Herring }; 2323724ba675SRob Herring }; 2324724ba675SRob Herring 2325724ba675SRob Herring target-module@45000 { /* 0x48345000, ap 108 6a.0 */ 2326724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 2327724ba675SRob Herring reg = <0x45000 0x4>, 2328724ba675SRob Herring <0x45110 0x4>, 2329724ba675SRob Herring <0x45114 0x4>; 2330724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 2331724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 2332724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 2333724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 2334724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2335724ba675SRob Herring <SYSC_IDLE_NO>, 2336724ba675SRob Herring <SYSC_IDLE_SMART>; 2337724ba675SRob Herring ti,syss-mask = <1>; 2338724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2339724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_SPI4_CLKCTRL 0>; 2340724ba675SRob Herring clock-names = "fck"; 2341724ba675SRob Herring #address-cells = <1>; 2342724ba675SRob Herring #size-cells = <1>; 2343724ba675SRob Herring ranges = <0x0 0x45000 0x1000>; 2344724ba675SRob Herring 2345724ba675SRob Herring spi4: spi@0 { 2346724ba675SRob Herring compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; 2347724ba675SRob Herring reg = <0x0 0x400>; 2348724ba675SRob Herring interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 2349724ba675SRob Herring #address-cells = <1>; 2350724ba675SRob Herring #size-cells = <0>; 2351724ba675SRob Herring status = "disabled"; 2352724ba675SRob Herring }; 2353724ba675SRob Herring }; 2354724ba675SRob Herring 2355724ba675SRob Herring target-module@47000 { /* 0x48347000, ap 110 70.0 */ 2356724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 2357724ba675SRob Herring reg = <0x47000 0x4>, 2358724ba675SRob Herring <0x47014 0x4>, 2359724ba675SRob Herring <0x47018 0x4>; 2360724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 2361724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 2362724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 2363724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2364724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_HDQ1W_CLKCTRL 0>; 2365724ba675SRob Herring clock-names = "fck"; 2366724ba675SRob Herring #address-cells = <1>; 2367724ba675SRob Herring #size-cells = <1>; 2368724ba675SRob Herring ranges = <0x0 0x47000 0x1000>; 2369724ba675SRob Herring 2370724ba675SRob Herring hdq: hdq@0 { 2371724ba675SRob Herring compatible = "ti,am4372-hdq"; 2372724ba675SRob Herring reg = <0x0 0x1000>; 2373724ba675SRob Herring interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 2374724ba675SRob Herring clocks = <&func_12m_clk>; 2375724ba675SRob Herring clock-names = "fck"; 2376724ba675SRob Herring status = "disabled"; 2377724ba675SRob Herring }; 2378724ba675SRob Herring }; 2379724ba675SRob Herring 2380724ba675SRob Herring target-module@4c000 { /* 0x4834c000, ap 114 72.0 */ 2381724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 2382724ba675SRob Herring reg = <0x4c000 0x4>, 2383724ba675SRob Herring <0x4c010 0x4>; 2384724ba675SRob Herring reg-names = "rev", "sysc"; 2385724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2386724ba675SRob Herring <SYSC_IDLE_NO>, 2387724ba675SRob Herring <SYSC_IDLE_SMART>; 2388724ba675SRob Herring clocks = <&l3s_clkctrl AM4_L3S_ADC1_CLKCTRL 0>; 2389724ba675SRob Herring clock-names = "fck"; 2390724ba675SRob Herring #address-cells = <1>; 2391724ba675SRob Herring #size-cells = <1>; 2392724ba675SRob Herring ranges = <0x0 0x4c000 0x2000>; 2393724ba675SRob Herring 2394724ba675SRob Herring magadc: magadc@0 { 2395724ba675SRob Herring compatible = "ti,am4372-magadc"; 2396724ba675SRob Herring reg = <0x0 0x2000>; 2397724ba675SRob Herring interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 2398724ba675SRob Herring clocks = <&adc_mag_fck>; 2399724ba675SRob Herring clock-names = "fck"; 2400724ba675SRob Herring dmas = <&edma 54 0>, <&edma 55 0>; 2401724ba675SRob Herring dma-names = "fifo0", "fifo1"; 2402724ba675SRob Herring status = "disabled"; 2403724ba675SRob Herring 2404724ba675SRob Herring mag { 2405724ba675SRob Herring compatible = "ti,am4372-mag"; 2406724ba675SRob Herring }; 2407724ba675SRob Herring 2408724ba675SRob Herring adc { 2409724ba675SRob Herring #io-channel-cells = <1>; 2410724ba675SRob Herring compatible = "ti,am4372-adc"; 2411724ba675SRob Herring }; 2412724ba675SRob Herring }; 2413724ba675SRob Herring }; 2414724ba675SRob Herring 2415724ba675SRob Herring target-module@80000 { /* 0x48380000, ap 123 42.0 */ 2416724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 2417724ba675SRob Herring reg = <0x80000 0x4>, 2418724ba675SRob Herring <0x80010 0x4>; 2419724ba675SRob Herring reg-names = "rev", "sysc"; 2420724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; 2421724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 2422724ba675SRob Herring <SYSC_IDLE_NO>, 2423724ba675SRob Herring <SYSC_IDLE_SMART>, 2424724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2425724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2426724ba675SRob Herring <SYSC_IDLE_NO>, 2427724ba675SRob Herring <SYSC_IDLE_SMART>, 2428724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2429724ba675SRob Herring /* Domains (P, C): per_pwrdm, l3s_clkdm */ 2430724ba675SRob Herring clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 0>; 2431724ba675SRob Herring clock-names = "fck"; 2432724ba675SRob Herring #address-cells = <1>; 2433724ba675SRob Herring #size-cells = <1>; 2434724ba675SRob Herring ranges = <0x0 0x80000 0x20000>; 2435724ba675SRob Herring 2436724ba675SRob Herring dwc3_1: omap_dwc3@0 { 2437724ba675SRob Herring compatible = "ti,am437x-dwc3"; 2438724ba675SRob Herring reg = <0x0 0x10000>; 2439724ba675SRob Herring interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 2440724ba675SRob Herring #address-cells = <1>; 2441724ba675SRob Herring #size-cells = <1>; 2442724ba675SRob Herring utmi-mode = <1>; 2443724ba675SRob Herring ranges = <0 0 0x20000>; 2444724ba675SRob Herring 2445724ba675SRob Herring usb1: usb@10000 { 2446724ba675SRob Herring compatible = "snps,dwc3"; 2447724ba675SRob Herring reg = <0x10000 0x10000>; 2448724ba675SRob Herring interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 2449724ba675SRob Herring <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 2450724ba675SRob Herring <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 2451724ba675SRob Herring interrupt-names = "peripheral", 2452724ba675SRob Herring "host", 2453724ba675SRob Herring "otg"; 2454724ba675SRob Herring phys = <&usb2_phy1>; 2455724ba675SRob Herring phy-names = "usb2-phy"; 2456724ba675SRob Herring maximum-speed = "high-speed"; 2457724ba675SRob Herring dr_mode = "otg"; 2458724ba675SRob Herring status = "disabled"; 2459724ba675SRob Herring snps,dis_u3_susphy_quirk; 2460724ba675SRob Herring snps,dis_u2_susphy_quirk; 2461724ba675SRob Herring }; 2462724ba675SRob Herring }; 2463724ba675SRob Herring }; 2464724ba675SRob Herring 2465724ba675SRob Herring target-module@a8000 { /* 0x483a8000, ap 125 6c.0 */ 2466724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 2467724ba675SRob Herring reg = <0xa8000 0x4>; 2468724ba675SRob Herring reg-names = "rev"; 2469724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2470724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP0_CLKCTRL 0>; 2471724ba675SRob Herring clock-names = "fck"; 2472724ba675SRob Herring #address-cells = <1>; 2473724ba675SRob Herring #size-cells = <1>; 2474724ba675SRob Herring ranges = <0x0 0xa8000 0x8000>; 2475724ba675SRob Herring 2476724ba675SRob Herring ocp2scp0: ocp2scp@0 { 2477724ba675SRob Herring compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; 2478724ba675SRob Herring #address-cells = <1>; 2479724ba675SRob Herring #size-cells = <1>; 2480724ba675SRob Herring ranges = <0 0 0x8000>; 2481724ba675SRob Herring 2482724ba675SRob Herring usb2_phy1: phy@8000 { 2483724ba675SRob Herring compatible = "ti,am437x-usb2"; 2484724ba675SRob Herring reg = <0x0 0x8000>; 2485724ba675SRob Herring syscon-phy-power = <&scm_conf 0x620>; 2486724ba675SRob Herring clocks = <&usb_phy0_always_on_clk32k>, 2487724ba675SRob Herring <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 8>; 2488724ba675SRob Herring clock-names = "wkupclk", "refclk"; 2489724ba675SRob Herring #phy-cells = <0>; 2490724ba675SRob Herring status = "disabled"; 2491724ba675SRob Herring }; 2492724ba675SRob Herring }; 2493724ba675SRob Herring }; 2494724ba675SRob Herring 2495724ba675SRob Herring target-module@c0000 { /* 0x483c0000, ap 127 7a.0 */ 2496724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 2497724ba675SRob Herring reg = <0xc0000 0x4>, 2498724ba675SRob Herring <0xc0010 0x4>; 2499724ba675SRob Herring reg-names = "rev", "sysc"; 2500724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; 2501724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 2502724ba675SRob Herring <SYSC_IDLE_NO>, 2503724ba675SRob Herring <SYSC_IDLE_SMART>, 2504724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2505724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2506724ba675SRob Herring <SYSC_IDLE_NO>, 2507724ba675SRob Herring <SYSC_IDLE_SMART>, 2508724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2509724ba675SRob Herring /* Domains (P, C): per_pwrdm, l3s_clkdm */ 2510724ba675SRob Herring clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 0>; 2511724ba675SRob Herring clock-names = "fck"; 2512724ba675SRob Herring #address-cells = <1>; 2513724ba675SRob Herring #size-cells = <1>; 2514724ba675SRob Herring ranges = <0x0 0xc0000 0x20000>; 2515724ba675SRob Herring 2516724ba675SRob Herring dwc3_2: omap_dwc3@0 { 2517724ba675SRob Herring compatible = "ti,am437x-dwc3"; 2518724ba675SRob Herring reg = <0x0 0x10000>; 2519724ba675SRob Herring interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 2520724ba675SRob Herring #address-cells = <1>; 2521724ba675SRob Herring #size-cells = <1>; 2522724ba675SRob Herring utmi-mode = <1>; 2523724ba675SRob Herring ranges = <0 0 0x20000>; 2524724ba675SRob Herring 2525724ba675SRob Herring usb2: usb@10000 { 2526724ba675SRob Herring compatible = "snps,dwc3"; 2527724ba675SRob Herring reg = <0x10000 0x10000>; 2528724ba675SRob Herring interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 2529724ba675SRob Herring <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 2530724ba675SRob Herring <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 2531724ba675SRob Herring interrupt-names = "peripheral", 2532724ba675SRob Herring "host", 2533724ba675SRob Herring "otg"; 2534724ba675SRob Herring phys = <&usb2_phy2>; 2535724ba675SRob Herring phy-names = "usb2-phy"; 2536724ba675SRob Herring maximum-speed = "high-speed"; 2537724ba675SRob Herring dr_mode = "otg"; 2538724ba675SRob Herring status = "disabled"; 2539724ba675SRob Herring snps,dis_u3_susphy_quirk; 2540724ba675SRob Herring snps,dis_u2_susphy_quirk; 2541724ba675SRob Herring }; 2542724ba675SRob Herring }; 2543724ba675SRob Herring }; 2544724ba675SRob Herring 2545724ba675SRob Herring target-module@e8000 { /* 0x483e8000, ap 129 78.0 */ 2546724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 2547724ba675SRob Herring reg = <0xe8000 0x4>; 2548724ba675SRob Herring reg-names = "rev"; 2549724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2550724ba675SRob Herring clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP1_CLKCTRL 0>; 2551724ba675SRob Herring clock-names = "fck"; 2552724ba675SRob Herring #address-cells = <1>; 2553724ba675SRob Herring #size-cells = <1>; 2554724ba675SRob Herring ranges = <0x0 0xe8000 0x8000>; 2555724ba675SRob Herring 2556724ba675SRob Herring ocp2scp1: ocp2scp@0 { 2557724ba675SRob Herring compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; 2558724ba675SRob Herring #address-cells = <1>; 2559724ba675SRob Herring #size-cells = <1>; 2560724ba675SRob Herring ranges = <0 0 0x8000>; 2561724ba675SRob Herring 2562724ba675SRob Herring usb2_phy2: phy@8000 { 2563724ba675SRob Herring compatible = "ti,am437x-usb2"; 2564724ba675SRob Herring reg = <0x0 0x8000>; 2565724ba675SRob Herring syscon-phy-power = <&scm_conf 0x628>; 2566724ba675SRob Herring clocks = <&usb_phy1_always_on_clk32k>, 2567724ba675SRob Herring <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 8>; 2568724ba675SRob Herring clock-names = "wkupclk", "refclk"; 2569724ba675SRob Herring #phy-cells = <0>; 2570724ba675SRob Herring status = "disabled"; 2571724ba675SRob Herring }; 2572724ba675SRob Herring }; 2573724ba675SRob Herring }; 2574724ba675SRob Herring 2575724ba675SRob Herring target-module@f2000 { /* 0x483f2000, ap 112 5a.0 */ 2576724ba675SRob Herring compatible = "ti,sysc"; 2577724ba675SRob Herring status = "disabled"; 2578724ba675SRob Herring #address-cells = <1>; 2579724ba675SRob Herring #size-cells = <1>; 2580724ba675SRob Herring ranges = <0x0 0xf2000 0x2000>; 2581724ba675SRob Herring }; 2582724ba675SRob Herring }; 2583724ba675SRob Herring}; 2584724ba675SRob Herring 2585