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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dmpc8548cds_32b.dts16 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
20 reg = <0 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0x0 0xff000000 0x01000000
23 0x1 0x0 0x0 0xf8004000 0x00001000>;
28 ranges = <0 0x0 0xe0000000 0x100000>;
32 reg = <0 0xe0008000 0 0x1000>;
33 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
34 0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
39 reg = <0 0xe0009000 0 0x1000>;
40 ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
[all …]
H A Dmpc8548cds_36b.dts16 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
20 reg = <0xf 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0xf 0xff000000 0x01000000
23 0x1 0x0 0xf 0xf8004000 0x00001000>;
28 ranges = <0 0xf 0xe0000000 0x100000>;
32 reg = <0xf 0xe0008000 0 0x1000>;
33 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000
34 0x1000000 0x0 0x00000000 0xf 0xe2000000 0x0 0x800000>;
39 reg = <0xf 0xe0009000 0 0x1000>;
40 ranges = <0x2000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
[all …]
H A Dmpc8541cds.dts29 #size-cells = <0>;
31 PowerPC,8541@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 bus-frequency = <0>; // 166 MHz
40 clock-frequency = <0>; // 825 MHz, from uboot
47 reg = <0x0 0x8000000>; // 128M at 0x0
55 ranges = <0x0 0xe0000000 0x100000>;
[all …]
H A Dmpc8555cds.dts29 #size-cells = <0>;
31 PowerPC,8555@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 bus-frequency = <0>; // 166 MHz
40 clock-frequency = <0>; // 825 MHz, from uboot
47 reg = <0x0 0x8000000>; // 128M at 0x0
55 ranges = <0x0 0xe0000000 0x100000>;
[all …]
H A Dmpc8548cds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x01000000>;
44 partition@0 {
45 reg = <0x0 0x0b00000>;
50 reg = <0x0b00000 0x0400000>;
55 reg = <0x0f00000 0x060000>;
60 reg = <0x0f60000 0x020000>;
66 reg = <0x0f80000 0x080000>;
72 board-control@1,0 {
74 reg = <0x1 0x0 0x1000>;
[all …]
H A Dmpc8540ads.dts29 #size-cells = <0>;
31 PowerPC,8540@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 bus-frequency = <0>; // 166 MHz
40 clock-frequency = <0>; // 825 MHz, from uboot
47 reg = <0x0 0x8000000>; // 128M at 0x0
55 ranges = <0x0 0xe0000000 0x100000>;
[all …]
H A Dmpc8560ads.dts30 #size-cells = <0>;
32 PowerPC,8560@0 {
34 reg = <0x0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
47 reg = <0x0 0x10000000>;
55 ranges = <0x0 0xe0000000 0x100000>;
58 ecm-law@0 {
60 reg = <0x0 0x1000>;
66 reg = <0x1000 0x1000>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dstxssa8555.dts30 #size-cells = <0>;
32 PowerPC,8555@0 {
34 reg = <0x0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot
48 reg = <0x00000000 0x10000000>;
56 ranges = <0x0 0xe0000000 0x100000>;
[all …]
H A Dmpc834x_mds.dts27 #size-cells = <0>;
29 PowerPC,8349@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; // from bootloader
44 reg = <0x00000000 0x10000000>; // 256MB at 0
49 reg = <0xe2400000 0x8000>;
57 ranges = <0x0 0xe0000000 0x00100000>;
58 reg = <0xe0000000 0x00000200>;
[all …]
H A Dmpc5121ads.dts21 nand@0 {
23 reg = <0x00000000 0x40000000>; /* 512MB + 512MB */
28 ranges = <0x0 0x0 0xfc000000 0x04000000
29 0x2 0x0 0x82000000 0x00008000>;
31 flash@0,0 {
33 reg = <0 0x0 0x4000000>;
39 protected@0 {
41 reg = <0x00000000 0x00040000>; // first sector is protected
46 reg = <0x00040000 0x03c00000>; // 60M for filesystem
50 reg = <0x03c40000 0x00280000>; // 2.5M for kernel
[all …]
H A Dmpc8379_mds.dts26 #size-cells = <0>;
28 PowerPC,8379@0 {
30 reg = <0x0>;
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
43 reg = <0x00000000 0x20000000>; // 512MB at 0
50 reg = <0xe0005000 0x1000>;
51 interrupts = <77 0x8>;
55 ranges = <0 0x0 0xfe000000 0x02000000
[all …]
H A Dmpc836x_rdk.dts32 #size-cells = <0>;
34 PowerPC,8360@0 {
36 reg = <0>;
42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
51 reg = <0 0>;
60 ranges = <0 0xe0000000 0x200000>;
61 reg = <0xe0000000 0x200>;
63 bus-frequency = <0>;
[all …]
H A Dmpc8378_mds.dts28 #size-cells = <0>;
30 PowerPC,8378@0 {
32 reg = <0x0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x00000000 0x20000000>; // 512MB at 0
52 reg = <0xe0005000 0x1000>;
53 interrupts = <77 0x8>;
57 ranges = <0 0x0 0xfe000000 0x02000000
[all …]
H A Dmpc832x_mds.dts39 #size-cells = <0>;
41 PowerPC,8323@0 {
43 reg = <0x0>;
48 timebase-frequency = <0>;
49 bus-frequency = <0>;
50 clock-frequency = <0>;
56 reg = <0x00000000 0x08000000>;
61 reg = <0xf8000000 0x8000>;
69 ranges = <0x0 0xe0000000 0x00100000>;
70 reg = <0xe0000000 0x00000200>;
[all …]
H A Dmpc8377_mds.dts28 #size-cells = <0>;
30 PowerPC,8377@0 {
32 reg = <0x0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x00000000 0x20000000>; // 512MB at 0
52 reg = <0xe0005000 0x1000>;
53 interrupts = <77 0x8>;
57 ranges = <0 0x0 0xfe000000 0x02000000
[all …]
H A Dmpc836x_mds.dts31 #size-cells = <0>;
33 PowerPC,8360@0 {
35 reg = <0x0>;
48 reg = <0x00000000 0x10000000>;
56 reg = <0xe0005000 0xd8>;
57 ranges = <0 0 0xfe000000 0x02000000
58 1 0 0xf8000000 0x00008000>;
60 flash@0,0 {
62 reg = <0 0 0x2000000>;
67 bcsr@1,0 {
[all …]
/freebsd/sys/dts/powerpc/
H A Dmpc8555cds.dts80 #size-cells = <0>;
82 PowerPC,8555@0 {
84 reg = <0x0>;
87 d-cache-size = <0x8000>; // L1, 32K
88 i-cache-size = <0x8000>; // L1, 32K
89 timebase-frequency = <0>; // 33 MHz, from uboot
90 bus-frequency = <0>; // 166 MHz
91 clock-frequency = <0>; // 825 MHz, from uboot
98 reg = <0x0 0x10000000>; // 256M at 0x0
105 reg = <0xe0005000 0x1000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dqcom,qmp-usb3-dp-phy.yaml83 "^usb3-phy@[0-9a-f]+$":
113 const: 0
116 const: 0
124 "^dp-phy@[0-9a-f]+$":
143 const: 0
181 reg = <0x088e9000 0x18c>,
182 <0x088e8000 0x10>,
183 <0x088ea000 0x40>;
187 ranges = <0x0 0x088e9000 0x2000>;
203 reg = <0x200 0x128>,
[all …]
H A Dqcom,sc7180-qmp-usb3-dp-phy.yaml92 "^usb3-phy@[0-9a-f]+$":
122 const: 0
125 const: 0
133 "^dp-phy@[0-9a-f]+$":
152 const: 0
237 reg = <0x088e9000 0x18c>,
238 <0x088e8000 0x10>,
239 <0x088ea000 0x40>;
243 ranges = <0x0 0x088e9000 0x2000>;
261 reg = <0x200 0x128>,
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76x02_regs.h9 #define MT_ASIC_VERSION 0x0000
11 #define MT76XX_REV_E3 0x22
12 #define MT76XX_REV_E4 0x33
14 #define MT_CMB_CTRL 0x0020
18 #define MT_EFUSE_CTRL 0x0024
19 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
27 #define MT_EFUSE_DATA_BASE 0x0028
30 #define MT_COEXCFG0 0x0040
31 #define MT_COEXCFG0_COEX_EN BIT(0)
33 #define MT_WLAN_FUN_CTRL 0x0080
[all …]
/freebsd/sys/dev/usb/wlan/
H A Dif_mtwreg.h19 #define MTW_ASIC_VER 0x0000
20 #define MTW_CMB_CTRL 0x0020
21 #define MTW_EFUSE_CTRL 0x0024
22 #define MTW_EFUSE_DATA0 0x0028
23 #define MTW_EFUSE_DATA1 0x002c
24 #define MTW_EFUSE_DATA2 0x0030
25 #define MTW_EFUSE_DATA3 0x0034
26 #define MTW_OSC_CTRL 0x0038
27 #define MTW_COEX_CFG0 0x0040
28 #define MTW_PLL_CTRL 0x0050
[all …]
/freebsd/sys/dev/xl/
H A Dif_xlreg.h35 #define XL_EE_READ 0x0080 /* read, 5 bit address */
36 #define XL_EE_WRITE 0x0040 /* write, 5 bit address */
37 #define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */
38 #define XL_EE_EWEN 0x0030 /* erase, no data needed */
39 #define XL_EE_8BIT_READ 0x0200 /* read, 8 bit address */
40 #define XL_EE_BUSY 0x8000
42 #define XL_EE_EADDR0 0x00 /* station address, first word */
43 #define XL_EE_EADDR1 0x01 /* station address, next word, */
44 #define XL_EE_EADDR2 0x02 /* station address, last word */
45 #define XL_EE_PRODID 0x03 /* product ID code */
[all …]
/freebsd/sys/dev/cxgbe/cudbg/
H A Dcudbg_entity.h42 #define NUM_PCIE_CONFIG_REGS 0x61
51 #define CUDBG_MAX_TCAM_TID 0x800
55 #define SN_REG_ADDR 0x183f
56 #define BN_REG_ADDR 0x1819
57 #define NA_REG_ADDR 0x185a
58 #define MN_REG_ADDR 0x1803
60 #define A_MPS_VF_RPLCT_MAP0 0x1111c
61 #define A_MPS_VF_RPLCT_MAP1 0x11120
62 #define A_MPS_VF_RPLCT_MAP2 0x11124
63 #define A_MPS_VF_RPLCT_MAP3 0x11128
[all …]
/freebsd/sys/arm64/freescale/imx/
H A Dimx8mp_ccm.c350 FIXED(IMX8MP_CLK_DUMMY, "dummy", 0),
359 MUX(IMX8MP_AUDIO_PLL1_REF_SEL, "audio_pll1_ref_sel", pll_ref_p, 0, 0x00, 0, 2),
360 MUX(IMX8MP_AUDIO_PLL2_REF_SEL, "audio_pll2_ref_sel", pll_ref_p, 0, 0x14, 0, 2),
361 MUX(IMX8MP_VIDEO_PLL1_REF_SEL, "video_pll1_ref_sel", pll_ref_p, 0, 0x28, 0, 2),
362 MUX(IMX8MP_DRAM_PLL_REF_SEL, "dram_pll_ref_sel", pll_ref_p, 0, 0x50, 0, 2),
363 MUX(IMX8MP_GPU_PLL_REF_SEL, "gpu_pll_ref_sel", pll_ref_p, 0, 0x64, 0, 2),
364 MUX(IMX8MP_VPU_PLL_REF_SEL, "vpu_pll_ref_sel", pll_ref_p, 0, 0x74, 0, 2),
365 MUX(IMX8MP_ARM_PLL_REF_SEL, "arm_pll_ref_sel", pll_ref_p, 0, 0x84, 0, 2),
366 MUX(IMX8MP_SYS_PLL1_REF_SEL, "sys_pll1_ref_sel", pll_ref_p, 0, 0x94, 0, 2),
367 MUX(IMX8MP_SYS_PLL2_REF_SEL, "sys_pll2_ref_sel", pll_ref_p, 0, 0x104, 0, 2),
[all …]
/freebsd/sys/dev/pci/
H A Dpcireg.h53 #define PCIE_ARI_SLOTMAX 0
59 #define PCI_RID_FUNC_SHIFT 0
74 #define PCIE_ARI_RID2SLOT(rid) (0)
83 #define PCIR_DEVVENDOR 0x00
84 #define PCIR_VENDOR 0x00
85 #define PCIR_DEVICE 0x02
86 #define PCIR_COMMAND 0x04
87 #define PCIM_CMD_PORTEN 0x0001
88 #define PCIM_CMD_MEMEN 0x0002
89 #define PCIM_CMD_BUSMASTEREN 0x0004
[all …]

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