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/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sm6115-dpu.yaml63 reg = <0x05e01000 0x8f000>,
64 <0x05eb0000 0x2008>;
79 interrupts = <0>;
83 #size-cells = <0>;
85 port@0 {
86 reg = <0>;
H A Dqcom,qcm2290-dpu.yaml61 reg = <0x05e01000 0x8f000>,
62 <0x05eb0000 0x2008>;
76 interrupts = <0>;
80 #size-cells = <0>;
82 port@0 {
83 reg = <0>;
H A Dqcom,sdm845-dpu.yaml63 reg = <0x0ae01000 0x8f000>,
64 <0x0aeb0000 0x2008>;
75 interrupts = <0>;
81 #size-cells = <0>;
83 port@0 {
84 reg = <0>;
H A Dqcom,msm8998-dpu.yaml64 reg = <0x0c901000 0x8f000>,
65 <0x0c9a8e00 0xf0>,
66 <0x0c9b0000 0x2008>,
67 <0x0c9b8000 0x1040>;
78 interrupts = <0>;
84 #size-cells = <0>;
86 port@0 {
87 reg = <0>;
H A Dqcom,sc7180-dpu.yaml87 reg = <0x0ae01000 0x8f000>,
88 <0x0aeb0000 0x2008>;
102 interrupts = <0>;
108 #size-cells = <0>;
110 port@0 {
111 reg = <0>;
H A Dqcom,sm6150-dpu.yaml52 reg = <0x0ae01000 0x8f000>,
53 <0x0aeb0000 0x2008>;
69 interrupts = <0>;
73 #size-cells = <0>;
75 port@0 {
76 reg = <0>;
H A Dqcom,sm7150-dpu.yaml62 reg = <0x0ae01000 0x8f000>,
63 <0x0aeb0000 0x2008>;
86 interrupts = <0>;
90 #size-cells = <0>;
92 port@0 {
93 reg = <0>;
H A Dqcom,sc8280xp-mdss.yaml35 "^display-controller@[0-9a-f]+$":
43 "^displayport-controller@[0-9a-f]+$":
65 reg = <0x0ae00000 0x1000>;
83 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
84 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
87 iommus = <&apps_smmu 0x1000 0x402>;
95 reg = <0x0ae01000 0x8f000>,
96 <0x0aeb0000 0x2008>;
119 interrupts = <0>;
123 #size-cells = <0>;
[all …]
H A Dqcom,qcm2290-mdss.yaml49 "^display-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
93 reg = <0x05e00000 0x1000>;
110 iommus = <&apps_smmu 0x420 0x2>,
111 <&apps_smmu 0x421 0x0>;
116 reg = <0x05e01000 0x8f000>,
117 <0x05eb0000 0x2008>;
131 interrupts = <0>;
135 #size-cells = <0>;
[all …]
H A Dqcom,sm6115-mdss.yaml43 "^display-controller@[0-9a-f]+$":
51 "^dsi@[0-9a-f]+$":
65 "^phy@[0-9a-f]+$":
90 reg = <0x05e00000 0x1000>;
101 iommus = <&apps_smmu 0x420 0x2>,
102 <&apps_smmu 0x421 0x0>;
107 reg = <0x05e01000 0x8f000>,
108 <0x05eb0000 0x2008>;
123 interrupts = <0>;
127 #size-cells = <0>;
[all …]
H A Dqcom,sm6350-mdss.yaml48 "^display-controller@[0-9a-f]+$":
56 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
95 reg = <0x0ae00000 0x1000>;
109 iommus = <&apps_smmu 0x800 0x2>;
116 reg = <0x0ae01000 0x8f000>,
117 <0x0aeb0000 0x2008>;
139 interrupts = <0>;
145 #size-cells = <0>;
[all …]
H A Dqcom,sm6150-mdss.yaml47 "^display-controller@[0-9a-f]+$":
54 "^dsi@[0-9a-f]+$":
63 "^phy@[0-9a-f]+$":
84 reg = <0x0ae00000 0x1000>;
103 iommus = <&apps_smmu 0x800 0x0>;
109 reg = <0x0ae01000 0x8f000>,
110 <0x0aeb0000 0x2008>;
126 interrupts = <0>;
130 #size-cells = <0>;
132 port@0 {
[all …]
H A Dqcom,sdm670-mdss.yaml42 "^display-controller@[0-9a-f]+$":
50 "^displayport-controller@[0-9a-f]+$":
58 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
91 reg = <0x0ae00000 0x1000>;
103 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>,
104 <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>;
107 iommus = <&apps_smmu 0x880 0x8>,
108 <&apps_smmu 0xc80 0x8>;
116 reg = <0x0ae01000 0x8f000>,
[all …]
H A Dqcom,msm8998-mdss.yaml39 "^display-controller@[0-9a-f]+$":
47 "^dsi@[0-9a-f]+$":
57 "^phy@[0-9a-f]+$":
79 reg = <0x0c900000 0x1000>;
93 iommus = <&mmss_smmu 0>;
100 reg = <0x0c901000 0x8f000>,
101 <0x0c9a8e00 0xf0>,
102 <0x0c9b0000 0x2008>,
103 <0x0c9b8000 0x1040>;
114 interrupts = <0>;
[all …]
H A Dqcom,sdm845-mdss.yaml43 "^display-controller@[0-9a-f]+$":
51 "^displayport-controller@[0-9a-f]+$":
59 "^dsi@[0-9a-f]+$":
69 "^phy@[0-9a-f]+$":
94 reg = <0x0ae00000 0x1000>;
106 iommus = <&apps_smmu 0x880 0x8>,
107 <&apps_smmu 0xc80 0x8>;
112 reg = <0x0ae01000 0x8f000>,
113 <0x0aeb0000 0x2008>;
124 interrupts = <0>;
[all …]
H A Dqcom,sc7180-mdss.yaml49 "^display-controller@[0-9a-f]+$":
57 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
101 reg = <0xae00000 0x1000>;
118 iommus = <&apps_smmu 0x800 0x2>;
123 reg = <0x0ae01000 0x8f000>,
124 <0x0aeb0000 0x2008>;
138 interrupts = <0>;
144 #size-cells = <0>;
[all …]
H A Dqcom,sm8250-mdss.yaml47 "^display-controller@[0-9a-f]+$":
55 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
99 reg = <0x0ae00000 0x1000>;
118 iommus = <&apps_smmu 0x820 0x402>;
126 reg = <0x0ae01000 0x8f000>,
127 <0x0aeb0000 0x2008>;
143 interrupts = <0>;
147 #size-cells = <0>;
[all …]
H A Dqcom,sm8150-mdss.yaml48 "^display-controller@[0-9a-f]+$":
56 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
96 reg = <0x0ae00000 0x1000>;
115 iommus = <&apps_smmu 0x800 0x420>;
123 reg = <0x0ae01000 0x8f000>,
124 <0x0aeb0000 0x2008>;
140 interrupts = <0>;
144 #size-cells = <0>;
[all …]
H A Dqcom,sm8450-mdss.yaml39 "^display-controller@[0-9a-f]+$":
47 "^displayport-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
91 reg = <0x0ae00000 0x1000>;
115 iommus = <&apps_smmu 0x2800 0x402>;
123 reg = <0x0ae01000 0x8f000>,
124 <0x0aeb0000 0x2008>;
147 interrupts = <0>;
151 #size-cells = <0>;
[all …]
/linux/drivers/soc/tegra/cbb/
H A Dtegra234-cbb.c8 * Error types supported by CBB2.0 are:
27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
28 #define FABRIC_EN_CFG_STATUS_0_0 0x40
29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
30 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
31 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
33 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_INDEX_0_0 0x100
34 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_LOW_0 0x140
35 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_HI_0 0x144
37 #define FABRIC_MN_INITIATOR_ERR_EN_0 0x200
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsdm670.dtsi37 #clock-cells = <0>;
43 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
82 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
104 reg = <0x0 0x200>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm6115.dtsi34 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
69 reg = <0x0 0x1>;
70 clocks = <&cpufreq_hw 0>;
75 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-msm8998.c27 #define GCC_MMSS_MISC 0x0902C
28 #define GCC_GPU_MISC 0x71028
31 { 250000000, 2000000000, 0 },
36 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
55 .offset = 0x0,
68 .offset = 0x0,
81 .offset = 0x0,
94 .offset = 0x0,
[all …]