Home
last modified time | relevance | path

Searched +full:0 +full:x818 (Results 1 – 25 of 83) sorted by relevance

1234

/linux/drivers/staging/rtl8723bs/hal/
H A Dodm_DynamicBBPowerSaving.c19 pDM_PSTable->Rssi_val_min = 0; in odm_DynamicBBPowerSavingInit()
20 pDM_PSTable->initialize = 0; in odm_DynamicBBPowerSavingInit()
35 if (pDM_PSTable->initialize == 0) { in ODM_RF_Saving()
37 pDM_PSTable->Reg874 = (PHY_QueryBBReg(pDM_Odm->Adapter, 0x874, bMaskDWord)&0x1CC000)>>14; in ODM_RF_Saving()
38 pDM_PSTable->RegC70 = (PHY_QueryBBReg(pDM_Odm->Adapter, 0xc70, bMaskDWord)&BIT3)>>3; in ODM_RF_Saving()
39 pDM_PSTable->Reg85C = (PHY_QueryBBReg(pDM_Odm->Adapter, 0x85c, bMaskDWord)&0xFF000000)>>24; in ODM_RF_Saving()
40 pDM_PSTable->RegA74 = (PHY_QueryBBReg(pDM_Odm->Adapter, 0xa74, bMaskDWord)&0xF000)>>12; in ODM_RF_Saving()
41 /* Reg818 = PHY_QueryBBReg(padapter, 0x818, bMaskDWord); */ in ODM_RF_Saving()
46 if (pDM_Odm->RSSI_Min != 0xFF) { in ODM_RF_Saving()
65 PHY_SetBBReg(pDM_Odm->Adapter, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ in ODM_RF_Saving()
[all …]
H A Dodm_reg.h16 #define ODM_BB_RESET 0x002
17 #define ODM_DUMMY 0x4fe
18 #define RF_T_METER_OLD 0x24
19 #define RF_T_METER_NEW 0x42
21 #define ODM_EDCA_VO_PARAM 0x500
22 #define ODM_EDCA_VI_PARAM 0x504
23 #define ODM_EDCA_BE_PARAM 0x508
24 #define ODM_EDCA_BK_PARAM 0x50C
25 #define ODM_TXPAUSE 0x522
28 #define ODM_FPGA_PHY0_PAGE8 0x800
[all …]
H A Dodm_RegDefine11N.h13 #define ODM_REG_RF_MODE_11N 0x00
14 #define ODM_REG_RF_0B_11N 0x0B
15 #define ODM_REG_CHNBW_11N 0x18
16 #define ODM_REG_T_METER_11N 0x24
17 #define ODM_REG_RF_25_11N 0x25
18 #define ODM_REG_RF_26_11N 0x26
19 #define ODM_REG_RF_27_11N 0x27
20 #define ODM_REG_RF_2B_11N 0x2B
21 #define ODM_REG_RF_2C_11N 0x2C
22 #define ODM_REG_RXRF_A3_11N 0x3C
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Deswin,eic7700-usb.yaml80 reg = <0x50480000 0x10000>;
93 eswin,hsp-sp-csr = <&hsp_sp_csr 0x800 0x818>;
/linux/drivers/clk/sophgo/
H A Dclk-cv1800.h14 #define REG_PLL_G2_CTRL 0x800
15 #define REG_PLL_G2_STATUS 0x804
16 #define REG_MIPIMPLL_CSR 0x808
17 #define REG_A0PLL_CSR 0x80C
18 #define REG_DISPPLL_CSR 0x810
19 #define REG_CAM0PLL_CSR 0x814
20 #define REG_CAM1PLL_CSR 0x818
21 #define REG_PLL_G2_SSC_SYN_CTRL 0x840
22 #define REG_A0PLL_SSC_SYN_CTRL 0x850
23 #define REG_A0PLL_SSC_SYN_SET 0x854
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Dbcm4908_enet.h5 #define ENET_CONTROL 0x000
6 #define ENET_MIB_CTRL 0x004
7 #define ENET_MIB_CTRL_CLR_MIB 0x00000001
8 #define ENET_RX_ERR_MASK 0x008
9 #define ENET_MIB_MAX_PKT_SIZE 0x00C
10 #define ENET_MIB_MAX_PKT_SIZE_VAL 0x00003fff
11 #define ENET_DIAG_OUT 0x01c
12 #define ENET_ENABLE_DROP_PKT 0x020
13 #define ENET_IRQ_ENABLE 0x024
14 #define ENET_IRQ_ENABLE_OVFL 0x00000001
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
/linux/arch/arm/mach-s3c/
H A Dregs-syscon-power-s3c64xx.h14 #define S3C64XX_PWR_CFG S3C_SYSREG(0x804)
28 #define S3C64XX_PWRCFG_CFG_WFI_MASK (0x3 << 5)
30 #define S3C64XX_PWRCFG_CFG_WFI_IGNORE (0x0 << 5)
31 #define S3C64XX_PWRCFG_CFG_WFI_IDLE (0x1 << 5)
32 #define S3C64XX_PWRCFG_CFG_WFI_STOP (0x2 << 5)
33 #define S3C64XX_PWRCFG_CFG_WFI_SLEEP (0x3 << 5)
35 #define S3C64XX_PWRCFG_CFG_BATFLT_MASK (0x3 << 3)
37 #define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE (0x0 << 3)
38 #define S3C64XX_PWRCFG_CFG_BATFLT_IRQ (0x1 << 3)
39 #define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP (0x3 << 3)
[all …]
/linux/include/dt-bindings/pinctrl/
H A Dam33xx.h18 #define SLEWCTRL_FAST 0
30 #define PIN_OUTPUT_PULLDOWN 0
43 #define AM335X_PIN_OFFSET_MIN 0x0800U
45 #define AM335X_PIN_GPMC_AD0 0x800
46 #define AM335X_PIN_GPMC_AD1 0x804
47 #define AM335X_PIN_GPMC_AD2 0x808
48 #define AM335X_PIN_GPMC_AD3 0x80c
49 #define AM335X_PIN_GPMC_AD4 0x810
50 #define AM335X_PIN_GPMC_AD5 0x814
51 #define AM335X_PIN_GPMC_AD6 0x818
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Ddm.c21 long rssi_val_min = 0; in rtl8723e_dm_initial_gain_min_pwdb()
25 rtlpriv->link_info.bcn_rx_inperiod == 0) in rtl8723e_dm_initial_gain_min_pwdb()
26 return 0; in rtl8723e_dm_initial_gain_min_pwdb()
30 if (rtlpriv->dm.entry_min_undec_sm_pwdb != 0) in rtl8723e_dm_initial_gain_min_pwdb()
56 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); in rtl8723e_dm_false_alarm_counter_statistics()
59 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff); in rtl8723e_dm_false_alarm_counter_statistics()
60 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); in rtl8723e_dm_false_alarm_counter_statistics()
63 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff); in rtl8723e_dm_false_alarm_counter_statistics()
73 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8; in rtl8723e_dm_false_alarm_counter_statistics()
80 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1); in rtl8723e_dm_false_alarm_counter_statistics()
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dphy-miphy28lp.txt56 reg = <0x9b22000 0xff>,
57 <0x9b09000 0xff>,
58 <0x9b04000 0xff>;
63 st,syscfg = <0x114 0x818 0xe0 0xec>;
71 reg = <0x9b2a000 0xff>,
72 <0x9b19000 0xff>,
73 <0x9b14000 0xff>;
78 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
87 reg = <0x8f95000 0xff>,
88 <0x8f90000 0xff>;
[all …]
/linux/drivers/net/ethernet/ezchip/
H A Dnps_enet.h10 #define NPS_ENET_NAPI_POLL_WEIGHT 0x2
11 #define NPS_ENET_MAX_FRAME_LENGTH 0x3FFF
12 #define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR 0x7
13 #define NPS_ENET_GE_MAC_CFG_0_RX_IFG 0x5
14 #define NPS_ENET_GE_MAC_CFG_0_TX_IFG 0xC
15 #define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN 0x7
16 #define NPS_ENET_GE_MAC_CFG_2_STAT_EN 0x3
17 #define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH 0x14
18 #define NPS_ENET_GE_MAC_CFG_3_MAX_LEN 0x3FFC
20 #define NPS_ENET_DISABLE 0
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Ddm.h11 #define MF_USC_LSC 0
14 #define MAIN_ANT 0
17 #define AUX_ANT_CG_TRX 0
18 #define MAIN_ANT_CGCS_RX 0
22 #define DM_REG_RF_MODE_11N 0x00
23 #define DM_REG_RF_0B_11N 0x0B
24 #define DM_REG_CHNBW_11N 0x18
25 #define DM_REG_T_METER_11N 0x24
26 #define DM_REG_RF_25_11N 0x25
27 #define DM_REG_RF_26_11N 0x26
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
H A Ddm.h7 #define MAIN_ANT 0
10 #define AUX_ANT_CG_TRX 0
11 #define MAIN_ANT_CGCS_RX 0
15 #define DM_REG_RF_MODE_11N 0x00
16 #define DM_REG_RF_0B_11N 0x0B
17 #define DM_REG_CHNBW_11N 0x18
18 #define DM_REG_T_METER_11N 0x24
19 #define DM_REG_RF_25_11N 0x25
20 #define DM_REG_RF_26_11N 0x26
21 #define DM_REG_RF_27_11N 0x27
[all …]
/linux/arch/powerpc/include/asm/
H A Dxive-regs.h29 * store at 0 and some ESBs support doing a trigger via a
32 #define XIVE_ESB_STORE_EOI 0x400 /* Store */
33 #define XIVE_ESB_LOAD_EOI 0x000 /* Load */
34 #define XIVE_ESB_GET 0x800 /* Load */
35 #define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
36 #define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
37 #define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
38 #define XIVE_ESB_SET_PQ_11 0xf00 /* Load */
46 #define XIVE_ESB_LD_ST_MO 0x40 /* Load-after-store ordering */
48 #define XIVE_ESB_VAL_P 0x2
[all …]
H A Dpasemi_dma.h13 /* status register layout in IOB region, at 0xfb800000 */
24 PAS_DMA_CAP_TXCH = 0x44, /* Transmit Channel Info */
25 PAS_DMA_CAP_RXCH = 0x48, /* Transmit Channel Info */
26 PAS_DMA_CAP_IFI = 0x4c, /* Interface Info */
27 PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */
28 PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */
29 PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */
30 PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */
31 PAS_DMA_COM_CFG = 0x114, /* Common config reg */
32 PAS_DMA_TXF_SFLG0 = 0x140, /* Set flags */
[all …]
/linux/drivers/clk/renesas/
H A Dr9a07g043-cpg.c18 #define CPG_PL2SDHI_DSEL (0x218)
21 #define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2)
74 {0, 1},
78 {0, 0},
82 {0, 1},
87 {0, 0},
106 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
151 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
153 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
167 0x514, 0, MSTOP(BUS_REG1, BIT(7))),
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
H A Ddm.h7 #define MAIN_ANT 0
10 #define AUX_ANT_CG_TRX 0
11 #define MAIN_ANT_CGCS_RX 0
17 #define DM_REG_RF_MODE_11N 0x00
18 #define DM_REG_RF_0B_11N 0x0B
19 #define DM_REG_CHNBW_11N 0x18
20 #define DM_REG_T_METER_11N 0x24
21 #define DM_REG_RF_25_11N 0x25
22 #define DM_REG_RF_26_11N 0x26
23 #define DM_REG_RF_27_11N 0x27
[all …]
/linux/drivers/hsi/controllers/
H A Domap_ssi_regs.h15 #define SSI_REVISION_REG 0
16 # define SSI_REV_MAJOR 0xf0
17 # define SSI_REV_MINOR 0xf
18 #define SSI_SYSCONFIG_REG 0x10
19 # define SSI_AUTOIDLE (1 << 0)
21 # define SSI_SIDLEMODE_FORCE 0
24 # define SSI_SIDLEMODE_MASK 0x18
25 # define SSI_MIDLEMODE_FORCE 0
28 # define SSI_MIDLEMODE_MASK 0x3000
29 #define SSI_SYSSTATUS_REG 0x14
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Ddm.h7 #define MAIN_ANT 0
10 #define AUX_ANT_CG_TRX 0
11 #define MAIN_ANT_CGCS_RX 0
17 #define DM_REG_RF_MODE_11N 0x00
18 #define DM_REG_RF_0B_11N 0x0B
19 #define DM_REG_CHNBW_11N 0x18
20 #define DM_REG_T_METER_11N 0x24
21 #define DM_REG_RF_25_11N 0x25
22 #define DM_REG_RF_26_11N 0x26
23 #define DM_REG_RF_27_11N 0x27
[all …]
/linux/drivers/phy/ralink/
H A Dphy-ralink-usb.c22 #define RT_SYSC_REG_SYSCFG1 0x014
23 #define RT_SYSC_REG_CLKCFG1 0x030
24 #define RT_SYSC_REG_USB_PHY_CFG 0x05c
26 #define OFS_U2_PHY_AC0 0x800
27 #define OFS_U2_PHY_AC1 0x804
28 #define OFS_U2_PHY_AC2 0x808
29 #define OFS_U2_PHY_ACR0 0x810
30 #define OFS_U2_PHY_ACR1 0x814
31 #define OFS_U2_PHY_ACR2 0x818
32 #define OFS_U2_PHY_ACR3 0x81C
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam437x-gp-evm.dts57 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
58 brightness-levels = <0 51 53 56 62 75 101 152 255>;
68 pinctrl-0 = <&matrix_keypad_default>;
80 linux,keymap = <0x00000201 /* P1 */
81 0x00010202 /* P2 */
82 0x01000067 /* UP */
83 0x0101006a /* RIGHT */
84 0x02000069 /* LEFT */
85 0x0201006c>; /* DOWN */
103 #clock-cells = <0>;
[all …]
/linux/arch/mips/include/asm/
H A Dgt64120.h21 #define GT_CPU_OFS 0x000
23 #define GT_MULTI_OFS 0x120
26 #define GT_SCS10LD_OFS 0x008
27 #define GT_SCS10HD_OFS 0x010
28 #define GT_SCS32LD_OFS 0x018
29 #define GT_SCS32HD_OFS 0x020
30 #define GT_CS20LD_OFS 0x028
31 #define GT_CS20HD_OFS 0x030
32 #define GT_CS3BOOTLD_OFS 0x038
33 #define GT_CS3BOOTHD_OFS 0x040
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dsumod.h30 #define RCU_FW_VERSION 0x30c
32 #define RCU_PWR_GATING_SEQ0 0x408
33 #define RCU_PWR_GATING_SEQ1 0x40c
34 #define RCU_PWR_GATING_CNTL 0x410
35 # define PWR_GATING_EN (1 << 0)
36 # define RSVD_MASK (0x3 << 1)
38 # define PCV_MASK (0x1f << 3)
41 # define PCP_MASK (0xf << 8)
44 # define RPW_MASK (0xf << 16)
47 # define ID_MASK (0xf << 24)
[all …]

1234