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/linux/drivers/staging/rtl8723bs/hal/
H A Dodm_reg.h16 #define ODM_BB_RESET 0x002
17 #define ODM_DUMMY 0x4fe
18 #define RF_T_METER_OLD 0x24
19 #define RF_T_METER_NEW 0x42
21 #define ODM_EDCA_VO_PARAM 0x500
22 #define ODM_EDCA_VI_PARAM 0x504
23 #define ODM_EDCA_BE_PARAM 0x508
24 #define ODM_EDCA_BK_PARAM 0x50C
25 #define ODM_TXPAUSE 0x522
28 #define ODM_FPGA_PHY0_PAGE8 0x800
[all …]
H A Dodm_RegDefine11N.h13 #define ODM_REG_RF_MODE_11N 0x00
14 #define ODM_REG_RF_0B_11N 0x0B
15 #define ODM_REG_CHNBW_11N 0x18
16 #define ODM_REG_T_METER_11N 0x24
17 #define ODM_REG_RF_25_11N 0x25
18 #define ODM_REG_RF_26_11N 0x26
19 #define ODM_REG_RF_27_11N 0x27
20 #define ODM_REG_RF_2B_11N 0x2B
21 #define ODM_REG_RF_2C_11N 0x2C
22 #define ODM_REG_RXRF_A3_11N 0x3C
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/linux/arch/powerpc/include/asm/
H A Dxive-regs.h29 * store at 0 and some ESBs support doing a trigger via a
32 #define XIVE_ESB_STORE_EOI 0x400 /* Store */
33 #define XIVE_ESB_LOAD_EOI 0x000 /* Load */
34 #define XIVE_ESB_GET 0x800 /* Load */
35 #define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
36 #define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
37 #define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
38 #define XIVE_ESB_SET_PQ_11 0xf00 /* Load */
46 #define XIVE_ESB_LD_ST_MO 0x40 /* Load-after-store ordering */
48 #define XIVE_ESB_VAL_P 0x2
[all …]
/linux/drivers/hsi/controllers/
H A Domap_ssi_regs.h15 #define SSI_REVISION_REG 0
16 # define SSI_REV_MAJOR 0xf0
17 # define SSI_REV_MINOR 0xf
18 #define SSI_SYSCONFIG_REG 0x10
19 # define SSI_AUTOIDLE (1 << 0)
21 # define SSI_SIDLEMODE_FORCE 0
24 # define SSI_SIDLEMODE_MASK 0x18
25 # define SSI_MIDLEMODE_FORCE 0
28 # define SSI_MIDLEMODE_MASK 0x3000
29 #define SSI_SYSSTATUS_REG 0x14
[all …]
/linux/drivers/clk/sophgo/
H A Dclk-cv1800.h14 #define REG_PLL_G2_CTRL 0x800
15 #define REG_PLL_G2_STATUS 0x804
16 #define REG_MIPIMPLL_CSR 0x808
17 #define REG_A0PLL_CSR 0x80C
18 #define REG_DISPPLL_CSR 0x810
19 #define REG_CAM0PLL_CSR 0x814
20 #define REG_CAM1PLL_CSR 0x818
21 #define REG_PLL_G2_SSC_SYN_CTRL 0x840
22 #define REG_A0PLL_SSC_SYN_CTRL 0x850
23 #define REG_A0PLL_SSC_SYN_SET 0x854
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Dbcm4908_enet.h5 #define ENET_CONTROL 0x000
6 #define ENET_MIB_CTRL 0x004
7 #define ENET_MIB_CTRL_CLR_MIB 0x00000001
8 #define ENET_RX_ERR_MASK 0x008
9 #define ENET_MIB_MAX_PKT_SIZE 0x00C
10 #define ENET_MIB_MAX_PKT_SIZE_VAL 0x00003fff
11 #define ENET_DIAG_OUT 0x01c
12 #define ENET_ENABLE_DROP_PKT 0x020
13 #define ENET_IRQ_ENABLE 0x024
14 #define ENET_IRQ_ENABLE_OVFL 0x00000001
[all …]
/linux/arch/arm/mach-s3c/
H A Dregs-syscon-power-s3c64xx.h14 #define S3C64XX_PWR_CFG S3C_SYSREG(0x804)
28 #define S3C64XX_PWRCFG_CFG_WFI_MASK (0x3 << 5)
30 #define S3C64XX_PWRCFG_CFG_WFI_IGNORE (0x0 << 5)
31 #define S3C64XX_PWRCFG_CFG_WFI_IDLE (0x1 << 5)
32 #define S3C64XX_PWRCFG_CFG_WFI_STOP (0x2 << 5)
33 #define S3C64XX_PWRCFG_CFG_WFI_SLEEP (0x3 << 5)
35 #define S3C64XX_PWRCFG_CFG_BATFLT_MASK (0x3 << 3)
37 #define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE (0x0 << 3)
38 #define S3C64XX_PWRCFG_CFG_BATFLT_IRQ (0x1 << 3)
39 #define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP (0x3 << 3)
[all …]
/linux/include/dt-bindings/pinctrl/
H A Dam33xx.h18 #define SLEWCTRL_FAST 0
30 #define PIN_OUTPUT_PULLDOWN 0
43 #define AM335X_PIN_OFFSET_MIN 0x0800U
45 #define AM335X_PIN_GPMC_AD0 0x800
46 #define AM335X_PIN_GPMC_AD1 0x804
47 #define AM335X_PIN_GPMC_AD2 0x808
48 #define AM335X_PIN_GPMC_AD3 0x80c
49 #define AM335X_PIN_GPMC_AD4 0x810
50 #define AM335X_PIN_GPMC_AD5 0x814
51 #define AM335X_PIN_GPMC_AD6 0x818
[all …]
/linux/drivers/net/ethernet/ezchip/
H A Dnps_enet.h10 #define NPS_ENET_NAPI_POLL_WEIGHT 0x2
11 #define NPS_ENET_MAX_FRAME_LENGTH 0x3FFF
12 #define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR 0x7
13 #define NPS_ENET_GE_MAC_CFG_0_RX_IFG 0x5
14 #define NPS_ENET_GE_MAC_CFG_0_TX_IFG 0xC
15 #define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN 0x7
16 #define NPS_ENET_GE_MAC_CFG_2_STAT_EN 0x3
17 #define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH 0x14
18 #define NPS_ENET_GE_MAC_CFG_3_MAX_LEN 0x3FFC
20 #define NPS_ENET_DISABLE 0
[all …]
/linux/arch/m68k/kernel/
H A Drelocate_kernel.S27 2: addl #0x00000000,%a4 /* virt_to_phys() */
50 5: addl #0x00000000,%a4 /* virt_to_phys() */
57 andl #0xff000000,%d0
58 orw #0xe020,%d0 /* Map 16 MiB, enable, cacheable */
66 moveq #0,%d0
94 btst #0,%d0 /* entry & IND_DESTINATION? */
128 orw #0x808,%d0
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Ddm.h11 #define MF_USC_LSC 0
14 #define MAIN_ANT 0
17 #define AUX_ANT_CG_TRX 0
18 #define MAIN_ANT_CGCS_RX 0
22 #define DM_REG_RF_MODE_11N 0x00
23 #define DM_REG_RF_0B_11N 0x0B
24 #define DM_REG_CHNBW_11N 0x18
25 #define DM_REG_T_METER_11N 0x24
26 #define DM_REG_RF_25_11N 0x25
27 #define DM_REG_RF_26_11N 0x26
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
H A Ddm.h7 #define MAIN_ANT 0
10 #define AUX_ANT_CG_TRX 0
11 #define MAIN_ANT_CGCS_RX 0
15 #define DM_REG_RF_MODE_11N 0x00
16 #define DM_REG_RF_0B_11N 0x0B
17 #define DM_REG_CHNBW_11N 0x18
18 #define DM_REG_T_METER_11N 0x24
19 #define DM_REG_RF_25_11N 0x25
20 #define DM_REG_RF_26_11N 0x26
21 #define DM_REG_RF_27_11N 0x27
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
H A Ddm.h7 #define MAIN_ANT 0
10 #define AUX_ANT_CG_TRX 0
11 #define MAIN_ANT_CGCS_RX 0
17 #define DM_REG_RF_MODE_11N 0x00
18 #define DM_REG_RF_0B_11N 0x0B
19 #define DM_REG_CHNBW_11N 0x18
20 #define DM_REG_T_METER_11N 0x24
21 #define DM_REG_RF_25_11N 0x25
22 #define DM_REG_RF_26_11N 0x26
23 #define DM_REG_RF_27_11N 0x27
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dge_imp3a.dts22 reg = <0 0xfef05000 0 0x1000>;
24 ranges = <0x0 0x0 0x0 0xff000000 0x01000000
25 0x1 0x0 0x0 0xe0000000 0x08000000
26 0x2 0x0 0x0 0xe8000000 0x08000000
27 0x3 0x0 0x0 0xfc100000 0x00020000
28 0x4 0x0 0x0 0xfc000000 0x00008000
29 0x5 0x0 0x0 0xfc008000 0x00008000
30 0x6 0x0 0x0 0xfee00000 0x00040000
31 0x7 0x0 0x0 0xfee80000 0x00040000>;
33 /* nor@0,0 is a mirror of part of the memory in nor@1,0
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Ddm.h7 #define MAIN_ANT 0
10 #define AUX_ANT_CG_TRX 0
11 #define MAIN_ANT_CGCS_RX 0
17 #define DM_REG_RF_MODE_11N 0x00
18 #define DM_REG_RF_0B_11N 0x0B
19 #define DM_REG_CHNBW_11N 0x18
20 #define DM_REG_T_METER_11N 0x24
21 #define DM_REG_RF_25_11N 0x25
22 #define DM_REG_RF_26_11N 0x26
23 #define DM_REG_RF_27_11N 0x27
[all …]
H A Dreg.h7 #define TXPKT_BUF_SELECT 0x69
8 #define RXPKT_BUF_SELECT 0xA5
9 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
11 #define REG_SYS_ISO_CTRL 0x0000
12 #define REG_SYS_FUNC_EN 0x0002
13 #define REG_APS_FSMCO 0x0004
14 #define REG_SYS_CLKR 0x0008
15 #define REG_9346CR 0x000A
16 #define REG_EE_VPD 0x000C
17 #define REG_AFE_MISC 0x0010
[all …]
/linux/drivers/dma/
H A Dst_fdma.h63 #define FDMA_NODE_CTRL_REQ_MAP_MASK GENMASK(4, 0)
64 #define FDMA_NODE_CTRL_REQ_MAP_FREE_RUN 0x0
150 #define FDMA_CMD_STA_OFST 0xFC0
151 #define FDMA_CMD_SET_OFST 0xFC4
152 #define FDMA_CMD_CLR_OFST 0xFC8
153 #define FDMA_CMD_MASK_OFST 0xFCC
154 #define FDMA_CMD_START(ch) (0x1 << (ch << 1))
155 #define FDMA_CMD_PAUSE(ch) (0x2 << (ch << 1))
156 #define FDMA_CMD_FLUSH(ch) (0x3 << (ch << 1))
158 #define FDMA_INT_STA_OFST 0xFD0
[all …]
/linux/drivers/phy/ralink/
H A Dphy-ralink-usb.c22 #define RT_SYSC_REG_SYSCFG1 0x014
23 #define RT_SYSC_REG_CLKCFG1 0x030
24 #define RT_SYSC_REG_USB_PHY_CFG 0x05c
26 #define OFS_U2_PHY_AC0 0x800
27 #define OFS_U2_PHY_AC1 0x804
28 #define OFS_U2_PHY_AC2 0x808
29 #define OFS_U2_PHY_ACR0 0x810
30 #define OFS_U2_PHY_ACR1 0x814
31 #define OFS_U2_PHY_ACR2 0x818
32 #define OFS_U2_PHY_ACR3 0x81C
[all …]
/linux/drivers/pmdomain/sunxi/
H A Dsun55i-pck600.c32 #define PPU_PWPR 0x0
33 #define PPU_PWSR 0x8
34 #define PPU_DCDR0 0x170
35 #define PPU_DCDR1 0x174
38 #define PPU_PWR_STATUS GENMASK(3, 0)
39 #define PPU_POWER_MODE_ON 0x8
40 #define PPU_POWER_MODE_OFF 0x0
42 #define PPU_REG_SIZE 0x1000
89 0, 10000); in sunxi_pck600_pd_set_power()
150 base = devm_platform_ioremap_resource(pdev, 0); in sunxi_pck600_probe()
[all …]
/linux/drivers/net/dsa/
H A Drzn1_a5psw.h18 #define A5PSW_REVISION 0x0
19 #define A5PSW_PORT_OFFSET(port) (0x400 * (port))
21 #define A5PSW_PORT_ENA 0x8
26 #define A5PSW_UCAST_DEF_MASK 0xC
28 #define A5PSW_VLAN_VERIFY 0x10
29 #define A5PSW_VLAN_VERI_SHIFT 0
32 #define A5PSW_BCAST_DEF_MASK 0x14
33 #define A5PSW_MCAST_DEF_MASK 0x18
35 #define A5PSW_INPUT_LEARN 0x1C
39 #define A5PSW_MGMT_CFG 0x20
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_backend.h20 #define SUN4I_BACKEND_MODCTL_REG 0x800
24 #define SUN4I_BACKEND_MODCTL_OUT_LCD0 (0 << 20)
34 #define SUN4I_BACKEND_MODCTL_DEBE_EN BIT(0)
36 #define SUN4I_BACKEND_BACKCOLOR_REG 0x804
39 #define SUN4I_BACKEND_DISSIZE_REG 0x808
40 #define SUN4I_BACKEND_DISSIZE(w, h) (((((h) - 1) & 0xffff) << 16) | \
41 (((w) - 1) & 0xffff))
43 #define SUN4I_BACKEND_LAYSIZE_REG(l) (0x810 + (0x4 * (l)))
44 #define SUN4I_BACKEND_LAYSIZE(w, h) (((((h) - 1) & 0x1fff) << 16) | \
45 (((w) - 1) & 0x1fff))
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam437x-gp-evm.dts57 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
58 brightness-levels = <0 51 53 56 62 75 101 152 255>;
68 pinctrl-0 = <&matrix_keypad_default>;
80 linux,keymap = <0x00000201 /* P1 */
81 0x00010202 /* P2 */
82 0x01000067 /* UP */
83 0x0101006a /* RIGHT */
84 0x02000069 /* LEFT */
85 0x0201006c>; /* DOWN */
103 #clock-cells = <0>;
[all …]
/linux/include/linux/bcma/
H A Dbcma_driver_pci.h10 #define BCMA_CORE_PCI_CTL 0x0000 /* PCI Control */
11 #define BCMA_CORE_PCI_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */
12 #define BCMA_CORE_PCI_CTL_RST 0x00000002 /* PCI_RESET driven out to pin */
13 #define BCMA_CORE_PCI_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */
14 #define BCMA_CORE_PCI_CTL_CLK 0x00000008 /* Gate for clock driven out to pin */
15 #define BCMA_CORE_PCI_ARBCTL 0x0010 /* PCI Arbiter Control */
16 #define BCMA_CORE_PCI_ARBCTL_INTERN 0x00000001 /* Use internal arbiter */
17 #define BCMA_CORE_PCI_ARBCTL_EXTERN 0x00000002 /* Use external arbiter */
18 #define BCMA_CORE_PCI_ARBCTL_PARKID 0x00000006 /* Mask, selects which agent is parked on an idle …
19 #define BCMA_CORE_PCI_ARBCTL_PARKID_LAST 0x00000000 /* Last requestor */
[all …]
/linux/drivers/perf/hisilicon/
H A Dhisi_uncore_mn_pmu.c21 #define HISI_MN_DYNAMIC_CTRL_REG 0x400
22 #define HISI_MN_DYNAMIC_CTRL_EN BIT(0)
23 #define HISI_MN_PERF_CTRL_REG 0x408
25 #define HISI_MN_INT_MASK_REG 0x800
26 #define HISI_MN_INT_STATUS_REG 0x808
27 #define HISI_MN_INT_CLEAR_REG 0x80C
28 #define HISI_MN_EVENT_CTRL_REG 0x1C00
29 #define HISI_MN_VERSION_REG 0x1C04
30 #define HISI_MN_EVTYPE0_REG 0x1d00
31 #define HISI_MN_EVTYPE_MASK GENMASK(7, 0)
[all …]

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