Home
last modified time | relevance | path

Searched +full:0 +full:x78000000 (Results 1 – 25 of 62) sorted by relevance

123

/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62.dtsi77 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
78 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
79 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
80 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
81 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
82 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
83 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
84 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
85 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
86 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-am62a.dtsi81 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
82 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
83 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
84 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
85 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
86 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
87 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
88 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
89 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
90 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-am64.dtsi54 ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
58 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
59 <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
61 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
63 <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dmicrochip,pcie-host.yaml47 0-3
51 pattern: '^fic[0-3]$'
72 reg = <0x0 0x70000000 0x0 0x08000000>,
73 <0x0 0x43008000 0x0 0x00002000>,
74 <0x0 0x4300a000 0x0 0x00002000>;
81 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
82 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
83 <0 0 0 2 &pcie_intc0 1>,
84 <0 0 0 3 &pcie_intc0 2>,
85 <0 0 0 4 &pcie_intc0 3>;
[all …]
/linux/drivers/net/ethernet/dec/tulip/
H A Dpnic.c23 u32 phy_reg = ioread32(ioaddr + 0xB8); in pnic_do_nway()
26 if (phy_reg & 0x78000000) { /* Ignore baseT4 */ in pnic_do_nway()
27 if (phy_reg & 0x20000000) dev->if_port = 5; in pnic_do_nway()
28 else if (phy_reg & 0x40000000) dev->if_port = 3; in pnic_do_nway()
29 else if (phy_reg & 0x10000000) dev->if_port = 4; in pnic_do_nway()
30 else if (phy_reg & 0x08000000) dev->if_port = 0; in pnic_do_nway()
32 new_csr6 = (dev->if_port & 1) ? 0x01860000 : 0x00420000; in pnic_do_nway()
33 iowrite32(0x32 | (dev->if_port & 1), ioaddr + CSR12); in pnic_do_nway()
35 iowrite32(0x1F868, ioaddr + 0xB8); in pnic_do_nway()
36 if (phy_reg & 0x30000000) { in pnic_do_nway()
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a774a1-hihope-rzg2m.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x6 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.2",
36 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a774e1-hihope-rzg2h.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x5 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.3",
36 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a774a1-hihope-rzg2m-rev2.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x6 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.2",
36 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a779m5-salvator-xs.dts23 reg = <0x0 0x48000000 0x0 0x78000000>;
34 clock-names = "du.0", "du.1", "du.3",
35 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a774b1-hihope-rzg2n.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x4 0x80000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.3",
36 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a774b1-hihope-rzg2n-rev2.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x4 0x80000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.3",
36 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a779m3-salvator-xs.dts23 reg = <0x0 0x48000000 0x0 0x78000000>;
28 reg = <0x4 0x80000000 0x0 0x80000000>;
33 reg = <0x6 0x00000000 0x1 0x00000000>;
44 clock-names = "du.0", "du.1", "du.2",
45 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a779m3-ulcb.dts22 reg = <0x0 0x48000000 0x0 0x78000000>;
27 reg = <0x4 0x80000000 0x0 0x80000000>;
32 reg = <0x6 0x00000000 0x1 0x00000000>;
43 clock-names = "du.0", "du.1", "du.2",
44 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a779f0-spider-cpu.dtsi54 reg = <0x0 0x48000000 0x0 0x78000000>;
59 reg = <0x4 0x80000000 0x0 0x80000000>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
102 pinctrl-0 = <&hscif0_pins>;
111 pinctrl-0 = <&i2c0_pins>;
119 reg = <0x20>;
132 pinctrl-0 = <&i2c4_pins>;
141 reg = <0x50>;
151 pinctrl-0 = <&mmc_pins>;
[all …]
H A Dr8a779a0-falcon-cpu.dtsi36 pinctrl-0 = <&keys_pins>;
90 reg = <0x0 0x48000000 0x0 0x78000000>;
95 reg = <0x5 0x00000000 0x0 0x80000000>;
100 reg = <0x6 0x00000000 0x0 0x80000000>;
105 reg = <0x7 0x00000000 0x0 0x80000000>;
149 #clock-cells = <0>;
180 pinctrl-0 = <&i2c0_pins>;
189 reg = <0x50>;
195 pinctrl-0 = <&i2c1_pins>;
202 pinctrl-0 = <&irq0_pins>;
[all …]
H A Dr8a774c0-cat874.dts67 reg = <0x0 0x48000000 0x0 0x78000000>;
72 regulator-name = "D12.0V";
115 states = <3300000 1>, <1800000 0>;
131 #clock-cells = <0>;
142 #size-cells = <0>;
143 port@0 {
144 reg = <0>;
164 pinctrl-0 = <&du_pins>;
171 clock-names = "du.0", "du.1", "dclkin.0";
174 port@0 {
[all …]
/linux/arch/sparc/include/asm/
H A Dpcr.h19 #define PCR_PIC_PRIV 0x00000001 /* PIC access is privileged */
20 #define PCR_STRACE 0x00000002 /* Trace supervisor events */
21 #define PCR_UTRACE 0x00000004 /* Trace user events */
22 #define PCR_N2_HTRACE 0x00000008 /* Trace hypervisor events */
23 #define PCR_N2_TOE_OV0 0x00000010 /* Trap if PIC 0 overflows */
24 #define PCR_N2_TOE_OV1 0x00000020 /* Trap if PIC 1 overflows */
25 #define PCR_N2_MASK0 0x00003fc0
27 #define PCR_N2_SL0 0x0003c000
29 #define PCR_N2_OV0 0x00040000
30 #define PCR_N2_MASK1 0x07f80000
[all …]
/linux/arch/arm/mach-footbridge/include/mach/
H A Dhardware.h13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
24 #define XBUS_SIZE 0x00100000
[all …]
/linux/drivers/net/wireless/silabs/wfx/
H A Dhwio.h33 #define CFG_ERR_SPI_FRAME 0x00000001 /* only with SPI */
34 #define CFG_ERR_SDIO_BUF_MISMATCH 0x00000001 /* only with SDIO */
35 #define CFG_ERR_BUF_UNDERRUN 0x00000002
36 #define CFG_ERR_DATA_IN_TOO_LARGE 0x00000004
37 #define CFG_ERR_HOST_NO_OUT_QUEUE 0x00000008
38 #define CFG_ERR_BUF_OVERRUN 0x00000010
39 #define CFG_ERR_DATA_OUT_TOO_LARGE 0x00000020
40 #define CFG_ERR_HOST_NO_IN_QUEUE 0x00000040
41 #define CFG_ERR_HOST_CRC_MISS 0x00000080 /* only with SDIO */
42 #define CFG_SPI_IGNORE_CS 0x00000080 /* only with SPI */
[all …]
/linux/arch/powerpc/include/asm/
H A Ddisassemble.h21 return (inst >> 1) & 0x3ff; in get_xop()
26 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); in get_sprn()
31 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); in get_dcrn()
36 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); in get_tmrn()
41 return (inst >> 21) & 0x1f; in get_rt()
46 return (inst >> 21) & 0x1f; in get_rs()
51 return (inst >> 16) & 0x1f; in get_ra()
56 return (inst >> 11) & 0x1f; in get_rb()
61 return inst & 0x1; in get_rc()
66 return (inst >> 11) & 0x1f; in get_ws()
[all …]
H A Dkeylargo.h10 /* "Pangea" chipset has keylargo device-id 0x25 while core99
11 * has device-id 0x22. The rev. of the pangea one is 0, so we
12 * fake an artificial rev. in keylargo_rev by oring 0x100
14 #define KL_PANGEA_REV 0x100
17 #define KEYLARGO_MBCR 0x34 /* KL Only, Media bay control/status */
18 #define KEYLARGO_FCR0 0x38
19 #define KEYLARGO_FCR1 0x3c
20 #define KEYLARGO_FCR2 0x40
21 #define KEYLARGO_FCR3 0x44
22 #define KEYLARGO_FCR4 0x48
[all …]
/linux/arch/arm/include/asm/hardware/
H A Ddec21285.h9 #define DC21285_PCI_IACK 0x79000000
10 #define DC21285_ARMCSR_BASE 0x42000000
11 #define DC21285_PCI_TYPE_0_CONFIG 0x7b000000
12 #define DC21285_PCI_TYPE_1_CONFIG 0x7a000000
13 #define DC21285_OUTBOUND_WRITE_FLUSH 0x78000000
14 #define DC21285_FLASH 0x41000000
15 #define DC21285_PCI_IO 0x7c000000
16 #define DC21285_PCI_MEM 0x80000000
26 * The footbridge is programmed to expose the system RAM at 0xe0000000.
27 * The requirement is that the RAM isn't placed at bus address 0, which
[all …]
/linux/drivers/gpu/drm/etnaviv/
H A Dcmdstream.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
42 #define FE_OPCODE_LOAD_STATE 0x00000001
43 #define FE_OPCODE_END 0x00000002
44 #define FE_OPCODE_NOP 0x00000003
45 #define FE_OPCODE_DRAW_2D 0x00000004
46 #define FE_OPCODE_DRAW_PRIMITIVES 0x00000005
47 #define FE_OPCODE_DRAW_INDEXED_PRIMITIVES 0x00000006
48 #define FE_OPCODE_WAIT 0x00000007
49 #define FE_OPCODE_LINK 0x00000008
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Dmorello.dtsi16 #clock-cells = <0>;
23 #clock-cells = <0>;
30 #size-cells = <0>;
32 cpu0: cpu@0 {
34 reg = <0x0 0x0>;
38 i-cache-size = <0x10000>;
41 d-cache-size = <0x10000>;
45 clocks = <&scmi_dvfs 0>;
51 cache-size = <0x100000>;
61 reg = <0x0 0x100>;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mq-tqma8mq.dtsi15 reg = <0x00000000 0x40000000 0 0x40000000>;
36 pinctrl-0 = <&pinctrl_dvfs>;
43 states = <900000 0x1 1000000 0x0>;
56 size = <0 0x28000000>;
58 alloc-ranges = <0 0x40000000 0 0x78000000>;
95 pinctrl-0 = <&pinctrl_i2c1>;
104 reg = <0x8>;
199 reg = <0x1b>;
204 reg = <0x51>;
206 pinctrl-0 = <&pinctrl_rtc>;
[all …]

123