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/linux/kernel/bpf/preload/iterators/
H A Diterators.lskel-big-endian.h27 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_map__attach()
29 if (fd > 0) in iterators_bpf__dump_bpf_map__attach()
38 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_prog__attach()
40 if (fd > 0) in iterators_bpf__dump_bpf_prog__attach()
48 int ret = 0; in iterators_bpf__attach()
50 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_map__attach(skel); in iterators_bpf__attach()
51 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_prog__attach(skel); in iterators_bpf__attach()
52 return ret < 0 ? ret : 0; in iterators_bpf__attach()
96 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load()
97 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load()
[all …]
H A Diterators.lskel-little-endian.h27 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_map__attach()
29 if (fd > 0) in iterators_bpf__dump_bpf_map__attach()
38 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_prog__attach()
40 if (fd > 0) in iterators_bpf__dump_bpf_prog__attach()
48 int ret = 0; in iterators_bpf__attach()
50 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_map__attach(skel); in iterators_bpf__attach()
51 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_prog__attach(skel); in iterators_bpf__attach()
52 return ret < 0 ? ret : 0; in iterators_bpf__attach()
96 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load()
97 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load()
[all …]
/linux/crypto/
H A Dtestmgr.h33 * @ksize: Length of @key in bytes (0 if no key)
103 * @crypt_error: When @novrfy=0, the expected error from encrypt(). When
222 "\x63\x1c\xcd\x7b\xe1\x7e\xe4\xde\xc9\xa8\x89\xa1\x74\xcb\x3c\x63"
235 "\xF7\x36\x8D\x07\xEE\xD4\x10\x43\xA4\x40\xD6\xB6\xF0\x74\x54\xF5"
239 "\x84\xEE\x6A\x64\x9D\x06\x09\x53\x74\x88\x34\xB2\x45\x45\x98\x39"
247 "\xB2\x94\x10\xB3\xC7\x99\x8D\x6B\xC4\x65\x74\x5E\x5C\x39\x26\x69"
251 "\x93\x99\x26\xED\x4F\x74\xA1\x3E\xDD\xFB\xE1\xA1\xCE\xCC\x48\x94"
269 "\xD9\x49\x09\x75\xEA\xB7\x74\x14\xFF\x59\xC1\xF7\x69\x2E\x9A\x2E"
270 "\x20\x2B\x38\xFC\x91\x0A\x47\x41\x74\xAD\xC9\x3C\x1F\x67\xC9\x81"
285 "\x74\x1b\x55\xac\x47\xb5\x08\x0a\x6e\x2b\x2d\xf7\x94\xb8\x8a\x95"
[all …]
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dgoya_blocks.h16 #define mmPCI_NRTR_BASE 0x7FFC000000ull
17 #define PCI_NRTR_MAX_OFFSET 0x608
18 #define PCI_NRTR_SECTION 0x4000
19 #define mmPCI_RD_REGULATOR_BASE 0x7FFC004000ull
20 #define PCI_RD_REGULATOR_MAX_OFFSET 0x74
21 #define PCI_RD_REGULATOR_SECTION 0x1000
22 #define mmPCI_WR_REGULATOR_BASE 0x7FFC005000ull
23 #define PCI_WR_REGULATOR_MAX_OFFSET 0x74
24 #define PCI_WR_REGULATOR_SECTION 0x3B000
25 #define mmMME1_RTR_BASE 0x7FFC040000ull
[all …]
/linux/drivers/staging/media/meson/vdec/
H A Dcodec_h264.c15 #define SIZE_WORKSPACE 0x1ee000
22 #define WORKSPACE_BUF_OFFSET 0x1000000
25 #define CMD_MASK GENMASK(7, 0)
43 #define PIC_STRUCT_MASK GENMASK(2, 0)
44 #define BUF_IDX_MASK GENMASK(4, 0)
47 #define OFFSET_MASK GENMASK(15, 0)
51 #define MB_TOTAL_MASK GENMASK(15, 0)
52 #define MB_WIDTH_MASK GENMASK(7, 0)
54 #define MAX_REF_MASK GENMASK(6, 0)
56 #define AR_IDC_MASK GENMASK(7, 0)
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7d-flex-concentrator.dts23 reg = <0x80000000 0x40000000>;
52 pinctrl-0 = <&pinctrl_leds>;
54 led-0 {
91 pinctrl-0 = <&pinctrl_restart>;
109 pinctrl-0 = <&pinctrl_ecspi2>;
113 pcf2127: rtc@0 {
115 reg = <0>;
123 pinctrl-0 = <&pinctrl_ecspi4>;
133 st33htph: tpm@0 {
135 reg = <0>;
[all …]
H A Dimx7-mba7.dtsi27 gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>;
43 button-0 {
86 io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>,
87 <&adc2 0>, <&adc2 1>, <&adc2 2>, <&adc2 3>;
226 pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_ss0>;
227 cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>,
234 pinctrl-0 = <&pinctrl_ecspi2>;
240 pinctrl-0 = <&pinctrl_enet1>;
249 #size-cells = <0>;
251 ethphy1_0: ethernet-phy@0 {
[all …]
H A Dimx7-colibri.dtsi15 brightness-levels = <0 45 63 88 119 158 203 255>;
20 pinctrl-0 = <&pinctrl_gpio_bl_on>;
22 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
34 pinctrl-0 = <&pinctrl_usbc_det>;
40 pinctrl-0 = <&pinctrl_gpiokeys>;
111 pinctrl-0 = <&pinctrl_usbh_reg>;
151 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
157 assigned-clock-rates = <0>, <100000000>;
170 pinctrl-0 = <&pinctrl_enet1>;
175 #size-cells = <0>;
[all …]
/linux/lib/crypto/
H A Dchacha20poly1305-selftest.c31 0x49, 0x6e, 0x74, 0x65, 0x72, 0x6e, 0x65, 0x74,
32 0x2d, 0x44, 0x72, 0x61, 0x66, 0x74, 0x73, 0x20,
33 0x61, 0x72, 0x65, 0x20, 0x64, 0x72, 0x61, 0x66,
34 0x74, 0x20, 0x64, 0x6f, 0x63, 0x75, 0x6d, 0x65,
35 0x6e, 0x74, 0x73, 0x20, 0x76, 0x61, 0x6c, 0x69,
36 0x64, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x61, 0x20,
37 0x6d, 0x61, 0x78, 0x69, 0x6d, 0x75, 0x6d, 0x20,
38 0x6f, 0x66, 0x20, 0x73, 0x69, 0x78, 0x20, 0x6d,
39 0x6f, 0x6e, 0x74, 0x68, 0x73, 0x20, 0x61, 0x6e,
40 0x64, 0x20, 0x6d, 0x61, 0x79, 0x20, 0x62, 0x65,
[all …]
H A Daesgcm.c43 * Returns: 0 on success, or -EINVAL if @keysize or @authsize contain values
60 return 0; in aesgcm_expandkey()
67 while (len > 0) { in aesgcm_ghash()
114 while (len > 0) { in aesgcm_crypt()
231 "\x42\x83\x1e\xc2\x21\x77\x74\x24"
253 "\x42\x83\x1e\xc2\x21\x77\x74\x24"
377 "\xcf\x59\x74\x1f\xb2\x85\xb4\x07"
381 "\x59\xa9\x97\xab\xbb\x0e\x74\x5c"
429 "\x86\x5c\x74\x3a\xeb\x24\x26\xc7"
462 "\xa4\x78\xdb\x74\x3d\x8b\xb5";
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx6ul.c76 { .val = 0, .div = 20, },
86 { .val = 0, .div = 4, },
91 { .val = 0, .div = 1, },
100 IMX6UL_GPR1_ENET1_CLK_SEL, 0,
106 IMX6UL_GPR1_ENET2_CLK_SEL, 0,
141 hws[IMX6UL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6ul_clocks_init()
151 base = of_iomap(np, 0); in imx6ul_clocks_init()
155 …hws[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
156 …hws[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
157 …hws[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
[all …]
H A Dclk-imx6sll.c19 #define CCM_ANALOG_PLL_BYPASS (0x1 << 16)
20 #define xPLL_CLR(offset) (offset + 0x8)
62 { .val = 0, .div = 4, },
67 { .val = 0, .div = 1, },
92 hws[IMX6SLL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6sll_clocks_init()
102 base = of_iomap(np, 0); in imx6sll_clocks_init()
107 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x0)); in imx6sll_clocks_init()
108 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x10)); in imx6sll_clocks_init()
109 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x20)); in imx6sll_clocks_init()
110 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x30)); in imx6sll_clocks_init()
[all …]
H A Dclk-imx6q.c97 { .val = 0, .div = 20, },
107 { .val = 0, .div = 4, },
112 { .val = 0, .div = 1, },
155 return 0; in ldb_di_sel_by_clock_id()
179 for (index = 0; index < num_parents; index++) { in of_assigned_ldb_sels()
182 if (rc < 0) { in of_assigned_ldb_sels()
189 if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) { in of_assigned_ldb_sels()
193 parent = clkspec.args[0]; in of_assigned_ldb_sels()
197 if (rc < 0) in of_assigned_ldb_sels()
199 if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) { in of_assigned_ldb_sels()
[all …]
H A Dclk-imx6sx.c89 { .val = 0, .div = 20, },
99 { .val = 0, .div = 4, },
104 { .val = 0, .div = 1, },
134 hws[IMX6SX_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6sx_clocks_init()
148 base = of_iomap(np, 0); in imx6sx_clocks_init()
152 …hws[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
153 …hws[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
154 …hws[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
155 …hws[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
156 …hws[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
[all …]
/linux/drivers/gpu/drm/panel/
H A Dpanel-himax-hx8394.c30 #define HX8394_CMD_SETSEQUENCE 0xb0
31 #define HX8394_CMD_SETPOWER 0xb1
32 #define HX8394_CMD_SETDISP 0xb2
33 #define HX8394_CMD_SETCYC 0xb4
34 #define HX8394_CMD_SETVCOM 0xb6
35 #define HX8394_CMD_SETTE 0xb7
36 #define HX8394_CMD_SETSENSOR 0xb8
37 #define HX8394_CMD_SETEXTC 0xb9
38 #define HX8394_CMD_SETMIPI 0xba
39 #define HX8394_CMD_SETOTP 0xbb
[all …]
/linux/drivers/soc/tegra/
H A Dpmc.c63 #define PMC_CNTRL 0x0
74 #define PMC_WAKE_MASK 0x0c
75 #define PMC_WAKE_LEVEL 0x10
76 #define PMC_WAKE_STATUS 0x14
77 #define PMC_SW_WAKE_STATUS 0x18
78 #define PMC_DPD_PADS_ORIDE 0x1c
81 #define DPD_SAMPLE 0x020
82 #define DPD_SAMPLE_ENABLE BIT(0)
83 #define DPD_SAMPLE_DISABLE (0 << 0)
85 #define PWRGATE_TOGGLE 0x30
[all …]
/linux/drivers/media/usb/gspca/
H A Dnw80x.c159 * - 3rd byte: data length (=0 for end of sequence)
162 #define I2C0 0xff
165 0x04, 0x05, 0x01, 0x61,
166 0x04, 0x04, 0x01, 0x01,
167 0x04, 0x06, 0x01, 0x04,
168 0x04, 0x04, 0x03, 0x00, 0x00, 0x00,
169 0x05, 0x05, 0x01, 0x00,
170 0, 0, 0
173 0x04, 0x06, 0x01, 0xc0,
174 0x00, 0x00, 0x40, 0x10, 0x43, 0x00, 0xb4, 0x01, 0x10, 0x00, 0x4f,
[all …]
/linux/drivers/gpu/drm/i915/gt/uc/abi/
H A Dguc_errors_abi.h10 INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0,
11 INTEL_GUC_RESPONSE_NOT_SUPPORTED = 0x20,
12 INTEL_GUC_RESPONSE_NO_ATTRIBUTE_TABLE = 0x201,
13 INTEL_GUC_RESPONSE_NO_DECRYPTION_KEY = 0x202,
14 INTEL_GUC_RESPONSE_DECRYPTION_FAILED = 0x204,
15 INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000,
19 INTEL_GUC_LOAD_STATUS_DEFAULT = 0x00,
20 INTEL_GUC_LOAD_STATUS_START = 0x01,
21 INTEL_GUC_LOAD_STATUS_ERROR_DEVID_BUILD_MISMATCH = 0x02,
22 INTEL_GUC_LOAD_STATUS_GUC_PREPROD_BUILD_MISMATCH = 0x03,
[all …]
/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A Dpipeline.json4 "Counter": "0,1,2,3",
5 "EventCode": "0xc4",
13 "Counter": "0,1,2,3",
14 "EventCode": "0xc4",
18 "UMask": "0xf9"
22 "Counter": "0,1,2,3",
23 "EventCode": "0xc4",
27 "UMask": "0xbf"
31 "Counter": "0,1,2,3",
32 "EventCode": "0xc4",
[all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Dpipeline.json4 "Counter": "0,1,2,3",
5 "EventCode": "0xc4",
13 "Counter": "0,1,2,3",
14 "EventCode": "0xc4",
18 "UMask": "0xf9"
22 "Counter": "0,1,2,3",
23 "EventCode": "0xc4",
27 "UMask": "0xbf"
31 "Counter": "0,1,2,3",
32 "EventCode": "0xc4",
[all …]
/linux/Documentation/devicetree/bindings/iio/light/
H A Dams,as73211.yaml26 I2C address of the device (0x74...0x77).
46 #size-cells = <0>;
50 reg = <0x74>;
52 pinctrl-0 = <&pinctrl_color_sensor>;
/linux/drivers/gpu/drm/xe/abi/
H A Dguc_errors_abi.h10 XE_GUC_RESPONSE_STATUS_SUCCESS = 0x0,
11 XE_GUC_RESPONSE_ERROR_PROTOCOL = 0x04,
12 XE_GUC_RESPONSE_INVALID_STATE = 0x0A,
13 XE_GUC_RESPONSE_UNSUPPORTED_VERSION = 0x0B,
14 XE_GUC_RESPONSE_INVALID_VFID = 0x0C,
15 XE_GUC_RESPONSE_UNPROVISIONED_VF = 0x0D,
16 XE_GUC_RESPONSE_INVALID_EVENT = 0x0E,
17 XE_GUC_RESPONSE_NOT_SUPPORTED = 0x20,
18 XE_GUC_RESPONSE_UNKNOWN_ACTION = 0x30,
19 XE_GUC_RESPONSE_ACTION_ABORTED = 0x31,
[all …]
/linux/arch/arm/include/asm/hardware/
H A Dioc.h24 #define IOC_CONTROL (0x00)
25 #define IOC_KARTTX (0x04)
26 #define IOC_KARTRX (0x04)
28 #define IOC_IRQSTATA (0x10)
29 #define IOC_IRQREQA (0x14)
30 #define IOC_IRQCLRA (0x14)
31 #define IOC_IRQMASKA (0x18)
33 #define IOC_IRQSTATB (0x20)
34 #define IOC_IRQREQB (0x24)
35 #define IOC_IRQMASKB (0x28)
[all …]
/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A Dpipeline.json4 "Counter": "0,1,2,3,4,5,6,7",
6 "EventCode": "0xcd",
9 "UMask": "0x3"
13 "Counter": "0,1,2,3,4,5,6,7",
14 "EventCode": "0xc4",
21 "Counter": "0,1,2,3,4,5,6,7",
22 "EventCode": "0xc4",
25 "UMask": "0x7e"
29 "Counter": "0,1,2,3,4,5,6,7",
30 "EventCode": "0xc4",
[all …]
/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A Dpipeline.json4 "Counter": "0,1,2,3,4,5,6,7",
6 "EventCode": "0xcd",
9 "UMask": "0x3"
13 "Counter": "0,1,2,3,4,5,6,7",
14 "EventCode": "0xc4",
21 "Counter": "0,1,2,3,4,5,6,7",
22 "EventCode": "0xc4",
25 "UMask": "0x7e"
29 "Counter": "0,1,2,3,4,5,6,7",
30 "EventCode": "0xc4",
[all …]

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