/freebsd/sys/contrib/device-tree/Bindings/spi/ |
H A D | spi-bcm63xx.txt | 10 - #size-cells: <0>, also as required by generic SPI binding. 22 reg = <0x10000800 0x70c>; 32 #size-cells = <0>;
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/freebsd/sys/contrib/device-tree/src/c6x/ |
H A D | tms320c6472.dtsi | 9 #size-cells = <0>; 11 cpu@0 { 13 reg = <0>; 60 reg = <0x1800000 0x1000>; 66 reg = <0x01840000 0x8400>; 71 ti,core-mask = < 0x01 >; 72 reg = <0x25e0000 0x40>; 77 ti,core-mask = < 0x02 >; 78 reg = <0x25f0000 0x40>; 83 ti,core-mask = < 0x04 >; [all …]
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/freebsd/sys/contrib/device-tree/src/mips/brcm/ |
H A D | bcm6358.dtsi | 13 #size-cells = <0>; 17 cpu@0 { 20 reg = <0>; 33 #clock-cells = <0>; 47 #address-cells = <0>; 63 reg = <0xfffe0004 0x4>; 69 reg = <0xfffe0008 0x4>; 74 offset = <0x0>; 75 mask = <0x1>; 81 reg = <0xfffe000c 0x8>, [all …]
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H A D | bcm6362.dtsi | 14 #size-cells = <0>; 18 cpu@0 { 21 reg = <0>; 34 #clock-cells = <0>; 42 #clock-cells = <0>; 58 #address-cells = <0>; 74 reg = <0x10000004 0x4>; 80 reg = <0x10000008 0x4>; 85 offset = <0x0>; 86 mask = <0x1>; [all …]
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H A D | bcm6368.dtsi | 13 #size-cells = <0>; 17 cpu@0 { 20 reg = <0>; 33 #clock-cells = <0>; 48 #address-cells = <0>; 64 reg = <0x10000004 0x4>; 70 reg = <0x10000008 0x4>; 75 offset = <0x0>; 76 mask = <0x1>; 82 reg = <0x10000010 0x4>; [all …]
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H A D | bcm63268.dtsi | 14 #size-cells = <0>; 18 cpu@0 { 21 reg = <0>; 34 #clock-cells = <0>; 42 #clock-cells = <0>; 58 #address-cells = <0>; 74 reg = <0x10000004 0x4>; 80 reg = <0x10000008 0x4>; 85 offset = <0x0>; 86 mask = <0x1>; [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/ |
H A D | hikey970-pinctrl.dtsi | 16 reg = <0x0 0xe896c000 0x0 0x72c>; 18 #gpio-range-cells = <0x3>; 19 pinctrl-single,register-width = <0x20>; 20 pinctrl-single,function-mask = <0x7>; 22 pinctrl-single,gpio-range = <&range 0 82 0>; 26 0x054 MUX_M2 /* UART0_RXD */ 27 0x058 MUX_M2 /* UART0_TXD */ 33 0x700 MUX_M2 /* UART2_CTS_N */ 34 0x704 MUX_M2 /* UART2_RTS_N */ 35 0x708 MUX_M2 /* UART2_RXD */ [all …]
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
H A D | imx35-pinfunc.h | 13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0 14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0 15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0 16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0 17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0 18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0 19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0 20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0 21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0 22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0 [all …]
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H A D | imx6dl-pinfunc.h | 13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0 14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0 15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0 16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0 17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0 18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0 19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0 20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0 21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0 22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0 [all …]
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H A D | imx6sl-pinfunc.h | 13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 [all …]
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H A D | imx6q-pinfunc.h | 13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 [all …]
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H A D | imx51-pinfunc.h | 13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0 14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0 15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0 16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0 17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0 18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0 19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0 20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0 21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0 22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0 [all …]
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H A D | imx50-pinfunc.h | 13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0 14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0 15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0 16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0 17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0 18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0 19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0 20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0 21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0 22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0 [all …]
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H A D | imxrt1170-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0 18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0 19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0 26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0 [all …]
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/freebsd/sys/dev/dwc/ |
H A D | dwc1000_reg.h | 37 #define MAC_CONFIGURATION 0x0 47 #define MAC_FRAME_FILTER 0x4 53 #define FRAME_FILTER_PR (1 << 0) /* All Incoming Frames */ 54 #define GMAC_MAC_HTHIGH 0x08 55 #define GMAC_MAC_HTLOW 0x0c 56 #define GMII_ADDRESS 0x10 57 #define GMII_ADDRESS_PA_MASK 0x1f /* Phy device */ 59 #define GMII_ADDRESS_GR_MASK 0x1f /* Phy register */ 61 #define GMII_ADDRESS_CR_MASK 0xf 64 #define GMII_ADDRESS_GB (1 << 0) /* Busy */ [all …]
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/freebsd/sys/arm64/nvidia/tegra210/ |
H A D | tegra210_car.h | 39 #define RST_SOURCE 0x000 40 #define RST_DEVICES_L 0x004 41 #define RST_DEVICES_H 0x008 42 #define RST_DEVICES_U 0x00C 43 #define CLK_OUT_ENB_L 0x010 44 #define CLK_OUT_ENB_H 0x014 45 #define CLK_OUT_ENB_U 0x018 46 #define SUPER_CCLK_DIVIDER 0x024 47 #define SCLK_BURST_POLICY 0x028 48 #define SUPER_SCLK_DIVIDER 0x02c [all …]
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/freebsd/sys/dev/ath/ath_hal/ar9002/ |
H A D | ar9285_attach.c | 85 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ in ar9285AniSetup() 92 .maxFirstepLevel = 2, /* levels 0..2 */ in ar9285AniSetup() 93 .firstep = { 0, 4, 8 }, in ar9285AniSetup() 122 ar9285_lna_conf[(pModal->antdiv_ctl2 >> 2) & 0x3]); in ar9285_eeprom_print_diversity_settings() 124 ar9285_lna_conf[pModal->antdiv_ctl2 & 0x3]); in ar9285_eeprom_print_diversity_settings() 126 ((pModal->antdiv_ctl1 & 0x1) ? "enabled" : "disabled"), in ar9285_eeprom_print_diversity_settings() 127 ((pModal->antdiv_ctl1 & 0x8) ? "enabled" : "disabled")); in ar9285_eeprom_print_diversity_settings() 217 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", in ar9285Attach() 224 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; in ar9285Attach() 270 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); in ar9285Attach() [all …]
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/freebsd/sys/dev/tsec/ |
H A D | if_tsecreg.h | 29 #define TSEC_REG_ID 0x000 /* Controller ID register #1. */ 30 #define TSEC_REG_ID2 0x004 /* Controller ID register #2. */ 33 #define TSEC_REG_IEVENT 0x010 /* Interrupt event register */ 34 #define TSEC_REG_IMASK 0x014 /* Interrupt mask register */ 35 #define TSEC_REG_EDIS 0x018 /* Error disabled register */ 36 #define TSEC_REG_ECNTRL 0x020 /* Ethernet control register */ 37 #define TSEC_REG_MINFLR 0x024 /* Minimum frame length register */ 38 #define TSEC_REG_PTV 0x028 /* Pause time value register */ 39 #define TSEC_REG_DMACTRL 0x02c /* DMA control register */ 40 #define TSEC_REG_TBIPA 0x030 /* TBI PHY address register */ [all …]
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/freebsd/sys/dev/clk/allwinner/ |
H A D | ccu_d1.c | 56 CCU_RESET(RST_MBUS, 0x540, 30) 57 CCU_RESET(RST_BUS_DE, 0x60C, 16) 58 CCU_RESET(RST_BUS_DI, 0x62C, 16) 59 CCU_RESET(RST_BUS_G2D, 0x63C, 16) 60 CCU_RESET(RST_BUS_CE, 0x68C, 16) 61 CCU_RESET(RST_BUS_VE, 0x69C, 16) 62 CCU_RESET(RST_BUS_DMA, 0x70C, 16) 63 CCU_RESET(RST_BUS_MSGBOX0, 0x71C, 16) 64 CCU_RESET(RST_BUS_MSGBOX1, 0x71C, 17) 65 CCU_RESET(RST_BUS_MSGBOX2, 0x71C, 18) [all …]
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/freebsd/sys/dev/qlxgb/ |
H A D | qla_misc.c | 54 #define Q8_ADDR_UNDEFINED 0xFFFFFFFF 61 Q8_ADDR_UNDEFINED, /* 0x00 */ 62 0x77300000, /* 0x01 */ 63 0x29500000, /* 0x02 */ 64 0x2A500000, /* 0x03 */ 65 Q8_ADDR_UNDEFINED, /* 0x04 */ 66 0x0D000000, /* 0x05 */ 67 0x1B100000, /* 0x06 */ 68 0x0E600000, /* 0x07 */ 69 0x0E000000, /* 0x08 */ [all …]
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/freebsd/sys/dev/sound/pci/hda/ |
H A D | hda_reg.h | 37 #define HDA_CMD_VERB_MASK 0x000fffff 38 #define HDA_CMD_VERB_SHIFT 0 39 #define HDA_CMD_NID_MASK 0x0ff00000 41 #define HDA_CMD_CAD_MASK 0xf0000000 62 #define HDA_CMD_VERB_GET_PARAMETER 0xf00 69 #define HDA_CMD_VERB_GET_CONN_SELECT_CONTROL 0xf01 70 #define HDA_CMD_VERB_SET_CONN_SELECT_CONTROL 0x701 74 HDA_CMD_VERB_GET_CONN_SELECT_CONTROL, 0x0)) 80 #define HDA_CMD_VERB_GET_CONN_LIST_ENTRY 0xf02 90 #define HDA_CMD_VERB_GET_PROCESSING_STATE 0xf03 [all …]
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/freebsd/usr.sbin/bhyve/ |
H A D | hda_reg.h | 37 #define HDA_CMD_VERB_MASK 0x000fffff 38 #define HDA_CMD_VERB_SHIFT 0 39 #define HDA_CMD_NID_MASK 0x0ff00000 41 #define HDA_CMD_CAD_MASK 0xf0000000 62 #define HDA_CMD_VERB_GET_PARAMETER 0xf00 69 #define HDA_CMD_VERB_GET_CONN_SELECT_CONTROL 0xf01 70 #define HDA_CMD_VERB_SET_CONN_SELECT_CONTROL 0x701 74 HDA_CMD_VERB_GET_CONN_SELECT_CONTROL, 0x0)) 80 #define HDA_CMD_VERB_GET_CONN_LIST_ENTRY 0xf02 90 #define HDA_CMD_VERB_GET_PROCESSING_STATE 0xf03 [all …]
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/freebsd/contrib/ofed/opensm/opensm/ |
H A D | osm_torus.c | 64 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 119 enum endpt_type { UNKNOWN = 0, SRCSINK, PASSTHRU }; 189 * used as follows, assuming 0 <= d < N: 195 * traversing a link from link.end[0] to link.end[1] is always in the positive 267 * A torus dimension has coordinate values 0, 1, ..., radix - 1. 270 * radix - 1 and 0. The following specify the dateline location 273 * E.g. if the shared switch is at 0,0,0, the following are all 316 #define X_MESH (1U << 0) 347 for (s = 0; s < f->switch_cnt; s++) { in teardown_fabric() 352 for (p = 0; p < sw->port_cnt; p++) { in teardown_fabric() [all …]
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/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
H A D | osprey_reg_map.h | 86 volatile char pad__0[0x8]; /* 0x0 - 0x8 */ 87 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */ 88 volatile char pad__1[0x8]; /* 0xc - 0x14 */ 89 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */ 90 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */ 91 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */ 92 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */ 93 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */ 94 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */ 95 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */ [all …]
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/freebsd/tools/tools/cxgbtool/ |
H A D | reg_defs_t3.c | 8 { "SG_CONTROL", 0x0, 0 }, 22 { "GlobalEnable", 0, 1 }, 23 { "SG_KDOORBELL", 0x4, 0 }, 25 { "EgrCntx", 0, 16 }, 26 { "SG_GTS", 0x8, 0 }, 29 { "NewIndex", 0, 16 }, 30 { "SG_CONTEXT_CMD", 0xc, 0 }, 38 { "Context", 0, 16 }, 39 { "SG_CONTEXT_DATA0", 0x10, 0 }, 40 { "SG_CONTEXT_DATA1", 0x14, 0 }, [all …]
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