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/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_machdep.c50 #define PMC_PHYSBASE 0x7000e400
51 #define PMC_SIZE 0x400
52 #define PMC_CONTROL_REG 0x0
53 #define PMC_SCRATCH0 0x50
70 return (0); in tegra124_attach()
87 devmap_add_entry(0x70000000, 0x01000000); in tegra124_devmap_init()
88 return (0); in tegra124_devmap_init()
98 bus_space_map(fdtbus_bs_tag, PMC_PHYSBASE, PMC_SIZE, 0, &pmc); in tegra124_cpu_reset()
109 bus_space_write_4(fdtbus_bs_tag, pmc, PMC_CONTROL_REG, reg | 0x10); in tegra124_cpu_reset()
118 * option SOCDEV_PA=0x70000000
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H A Dtegra124_mp.c46 #define PMC_PHYSBASE 0x7000e400
47 #define PMC_SIZE 0x400
48 #define PMC_CONTROL_REG 0x0
49 #define PMC_PWRGATE_TOGGLE 0x30
51 #define PMC_PWRGATE_STATUS 0x38
53 #define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000 /* exception vectors */
55 #define TEGRA_EXCEPTION_VECTOR_ENTRY 0x100
63 if (mp_ncpus != 0) in tegra124_mp_setmaxid()
83 if (bus_space_map(fdtbus_bs_tag, PMC_PHYSBASE, PMC_SIZE, 0, &pmc) != 0) in tegra124_mp_start_ap()
86 TEGRA_EXCEPTION_VECTORS_SIZE, 0, &exvec) != 0) in tegra124_mp_start_ap()
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/freebsd/sys/contrib/device-tree/Bindings/arm/tegra/
H A Dnvidia,tegra20-pmc.yaml88 enum: [0, 1, 2]
91 Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
145 const: 0
184 Defaults to 0. Valid values are described in section 12.5.2
212 3d0 3D Graphics 0 Tegra30
260 const: 0
261 description: Must be 0.
357 reg = <0x7000e400 0x400>;
364 nvidia,suspend-mode = <0>;
365 nvidia,cpu-pwr-good-time = <0>;
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/freebsd/sys/contrib/device-tree/Bindings/soc/tegra/
H A Dnvidia,tegra20-pmc.yaml81 const: 0
137 const: 0
170 Defaults to 0. Valid values are described in section 12.5.2 "Pinmux
200 3d0 3D Graphics 0 Tegra30
239 const: 0
240 description: Must be 0.
380 reg = <0x7000e400 0x400>;
387 nvidia,suspend-mode = <0>;
388 nvidia,cpu-pwr-good-time = <0>;
389 nvidia,cpu-pwr-off-time = <0>;
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/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra114.dtsi17 reg = <0x80000000 0x0>;
22 reg = <0x40000000 0x40000>;
25 ranges = <0 0x40000000 0x40000>;
28 reg = <0x400 0x3fc00>;
35 reg = <0x5000000
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H A Dtegra20.dtsi17 memory@0 {
19 reg = <0 0>;
24 reg = <0x40000000 0x40000>;
27 ranges = <0 0x40000000 0x40000>;
30 reg = <0x400 0x3fc0
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H A Dtegra124.dtsi21 reg = <0x0 0x80000000 0x0 0x0>;
27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
28 <0x0 0x0100380
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H A Dtegra30.dtsi20 reg = <0x80000000 0x0>;
26 reg = <0x00003000 0x00000800>, /* PADS registers */
27 <0x00003800 0x00000200>, /* AFI registers */
28 <0x10000000 0x10000000>; /* configuration space */
35 interrupt-map-mask = <0 0
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/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra132.dtsi22 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
23 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
24 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
31 interrupt-map-mask = <0 0 0 0>;
32 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
34 bus-range = <0x00 0xff>;
38 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
39 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
40 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
41 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
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H A Dtegra210.dtsi21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
33 bus-range = <0x00 0xff>;
37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
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