xref: /freebsd/sys/arm/nvidia/tegra124/tegra124_machdep.c (revision fdafd315ad0d0f28a11b9fb4476a9ab059c62b92)
1ef2ee5d0SMichal Meloun /*-
2ef2ee5d0SMichal Meloun  * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3ef2ee5d0SMichal Meloun  * All rights reserved.
4ef2ee5d0SMichal Meloun  *
5ef2ee5d0SMichal Meloun  * Redistribution and use in source and binary forms, with or without
6ef2ee5d0SMichal Meloun  * modification, are permitted provided that the following conditions
7ef2ee5d0SMichal Meloun  * are met:
8ef2ee5d0SMichal Meloun  * 1. Redistributions of source code must retain the above copyright
9ef2ee5d0SMichal Meloun  *    notice, this list of conditions and the following disclaimer.
10ef2ee5d0SMichal Meloun  * 2. Redistributions in binary form must reproduce the above copyright
11ef2ee5d0SMichal Meloun  *    notice, this list of conditions and the following disclaimer in the
12ef2ee5d0SMichal Meloun  *    documentation and/or other materials provided with the distribution.
13ef2ee5d0SMichal Meloun  *
14ef2ee5d0SMichal Meloun  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15ef2ee5d0SMichal Meloun  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16ef2ee5d0SMichal Meloun  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17ef2ee5d0SMichal Meloun  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18ef2ee5d0SMichal Meloun  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19ef2ee5d0SMichal Meloun  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20ef2ee5d0SMichal Meloun  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21ef2ee5d0SMichal Meloun  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22ef2ee5d0SMichal Meloun  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23ef2ee5d0SMichal Meloun  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24ef2ee5d0SMichal Meloun  * SUCH DAMAGE.
25ef2ee5d0SMichal Meloun  */
26ef2ee5d0SMichal Meloun 
27ef2ee5d0SMichal Meloun #include "opt_platform.h"
28ef2ee5d0SMichal Meloun 
29ef2ee5d0SMichal Meloun #include <sys/param.h>
30ef2ee5d0SMichal Meloun #include <sys/bus.h>
3130b72b68SRuslan Bukin #include <sys/devmap.h>
32*e2e050c8SConrad Meyer #include <sys/lock.h>
33*e2e050c8SConrad Meyer #include <sys/reboot.h>
34*e2e050c8SConrad Meyer #include <sys/systm.h>
35ef2ee5d0SMichal Meloun 
36ef2ee5d0SMichal Meloun #include <vm/vm.h>
37ef2ee5d0SMichal Meloun 
38ef2ee5d0SMichal Meloun #include <machine/bus.h>
39ef2ee5d0SMichal Meloun #include <machine/fdt.h>
40ef2ee5d0SMichal Meloun #include <machine/intr.h>
41ef2ee5d0SMichal Meloun #include <machine/machdep.h>
42ef2ee5d0SMichal Meloun #include <machine/platformvar.h>
43ef2ee5d0SMichal Meloun 
44ef2ee5d0SMichal Meloun #include <dev/ofw/openfirm.h>
45ef2ee5d0SMichal Meloun 
46ef2ee5d0SMichal Meloun #include <arm/nvidia/tegra124/tegra124_mp.h>
47ef2ee5d0SMichal Meloun 
48ef2ee5d0SMichal Meloun #include "platform_if.h"
49ef2ee5d0SMichal Meloun 
50ef2ee5d0SMichal Meloun #define	PMC_PHYSBASE		0x7000e400
51ef2ee5d0SMichal Meloun #define	PMC_SIZE		0x400
52ef2ee5d0SMichal Meloun #define	PMC_CONTROL_REG		0x0
53ef2ee5d0SMichal Meloun #define	PMC_SCRATCH0		0x50
54ef2ee5d0SMichal Meloun #define	 PMC_SCRATCH0_MODE_RECOVERY	(1 << 31)
55ef2ee5d0SMichal Meloun #define	 PMC_SCRATCH0_MODE_BOOTLOADER	(1 << 30)
56ef2ee5d0SMichal Meloun #define	 PMC_SCRATCH0_MODE_RCM		(1 << 1)
57ef2ee5d0SMichal Meloun #define	 PMC_SCRATCH0_MODE_MASK		(PMC_SCRATCH0_MODE_RECOVERY | \
58ef2ee5d0SMichal Meloun 					PMC_SCRATCH0_MODE_BOOTLOADER | \
59ef2ee5d0SMichal Meloun 					PMC_SCRATCH0_MODE_RCM)
60ef2ee5d0SMichal Meloun 
61ba9f40caSAndrew Turner static platform_attach_t tegra124_attach;
62ba9f40caSAndrew Turner static platform_devmap_init_t tegra124_devmap_init;
63ba9f40caSAndrew Turner static platform_late_init_t tegra124_late_init;
64ba9f40caSAndrew Turner static platform_cpu_reset_t tegra124_cpu_reset;
65ba9f40caSAndrew Turner 
66ef2ee5d0SMichal Meloun static int
tegra124_attach(platform_t plat)67ef2ee5d0SMichal Meloun tegra124_attach(platform_t plat)
68ef2ee5d0SMichal Meloun {
69ef2ee5d0SMichal Meloun 
70ef2ee5d0SMichal Meloun 	return (0);
71ef2ee5d0SMichal Meloun }
72ef2ee5d0SMichal Meloun 
73ef2ee5d0SMichal Meloun static void
tegra124_late_init(platform_t plat)74ef2ee5d0SMichal Meloun tegra124_late_init(platform_t plat)
75ef2ee5d0SMichal Meloun {
76ef2ee5d0SMichal Meloun 
77ef2ee5d0SMichal Meloun }
78ef2ee5d0SMichal Meloun 
79ef2ee5d0SMichal Meloun /*
80ef2ee5d0SMichal Meloun  * Set up static device mappings.
81ef2ee5d0SMichal Meloun  *
82ef2ee5d0SMichal Meloun  */
83ef2ee5d0SMichal Meloun static int
tegra124_devmap_init(platform_t plat)84ef2ee5d0SMichal Meloun tegra124_devmap_init(platform_t plat)
85ef2ee5d0SMichal Meloun {
86ef2ee5d0SMichal Meloun 
8730b72b68SRuslan Bukin 	devmap_add_entry(0x70000000, 0x01000000);
88ef2ee5d0SMichal Meloun 	return (0);
89ef2ee5d0SMichal Meloun }
90ef2ee5d0SMichal Meloun 
910dbb8873SAndrew Turner static void
tegra124_cpu_reset(platform_t plat)920dbb8873SAndrew Turner tegra124_cpu_reset(platform_t plat)
93ef2ee5d0SMichal Meloun {
94ef2ee5d0SMichal Meloun 	bus_space_handle_t pmc;
95ef2ee5d0SMichal Meloun 	uint32_t reg;
96ef2ee5d0SMichal Meloun 
97ef2ee5d0SMichal Meloun 	printf("Resetting...\n");
98ef2ee5d0SMichal Meloun 	bus_space_map(fdtbus_bs_tag, PMC_PHYSBASE, PMC_SIZE, 0, &pmc);
99ef2ee5d0SMichal Meloun 
100ef2ee5d0SMichal Meloun 	reg = bus_space_read_4(fdtbus_bs_tag, pmc, PMC_SCRATCH0);
101ef2ee5d0SMichal Meloun 	reg &= PMC_SCRATCH0_MODE_MASK;
102ef2ee5d0SMichal Meloun 	bus_space_write_4(fdtbus_bs_tag, pmc, PMC_SCRATCH0,
103ef2ee5d0SMichal Meloun 	   reg | PMC_SCRATCH0_MODE_BOOTLOADER); 	/* boot to bootloader */
104ef2ee5d0SMichal Meloun 	bus_space_read_4(fdtbus_bs_tag, pmc, PMC_SCRATCH0);
105ef2ee5d0SMichal Meloun 
106ef2ee5d0SMichal Meloun 	reg = bus_space_read_4(fdtbus_bs_tag, pmc, PMC_CONTROL_REG);
107ef2ee5d0SMichal Meloun 	spinlock_enter();
108ef2ee5d0SMichal Meloun 	dsb();
109ef2ee5d0SMichal Meloun 	bus_space_write_4(fdtbus_bs_tag, pmc, PMC_CONTROL_REG, reg | 0x10);
110ef2ee5d0SMichal Meloun 	bus_space_read_4(fdtbus_bs_tag, pmc, PMC_CONTROL_REG);
111ef2ee5d0SMichal Meloun 	while(1)
112ef2ee5d0SMichal Meloun 		;
113ef2ee5d0SMichal Meloun 
114ef2ee5d0SMichal Meloun }
115ef2ee5d0SMichal Meloun 
116ef2ee5d0SMichal Meloun /*
117ef2ee5d0SMichal Meloun  * Early putc routine for EARLY_PRINTF support.  To use, add to kernel config:
11869c48a28SMichal Meloun  *   option SOCDEV_PA=0x70000000
11969c48a28SMichal Meloun  *   option SOCDEV_VA=0x70000000
120ef2ee5d0SMichal Meloun  *   option EARLY_PRINTF
121ef2ee5d0SMichal Meloun  */
12259c4192cSEmmanuel Vadot #if 0
12369c48a28SMichal Meloun #ifdef EARLY_PRINTF
124ef2ee5d0SMichal Meloun static void
125ef2ee5d0SMichal Meloun tegra124_early_putc(int c)
126ef2ee5d0SMichal Meloun {
127ef2ee5d0SMichal Meloun 
12869c48a28SMichal Meloun 	volatile uint32_t * UART_STAT_REG = (uint32_t *)(0x70006314);
12969c48a28SMichal Meloun 	volatile uint32_t * UART_TX_REG   = (uint32_t *)(0x70006300);
13069c48a28SMichal Meloun 	const uint32_t      UART_TXRDY    = (1 << 6);
131ef2ee5d0SMichal Meloun 	while ((*UART_STAT_REG & UART_TXRDY) == 0)
132ef2ee5d0SMichal Meloun 		continue;
133ef2ee5d0SMichal Meloun 	*UART_TX_REG = c;
134ef2ee5d0SMichal Meloun }
135ef2ee5d0SMichal Meloun early_putc_t *early_putc = tegra124_early_putc;
136ef2ee5d0SMichal Meloun #endif
13759c4192cSEmmanuel Vadot #endif
138ef2ee5d0SMichal Meloun 
139ef2ee5d0SMichal Meloun static platform_method_t tegra124_methods[] = {
140ef2ee5d0SMichal Meloun 	PLATFORMMETHOD(platform_attach,		tegra124_attach),
141ef2ee5d0SMichal Meloun 	PLATFORMMETHOD(platform_devmap_init,	tegra124_devmap_init),
142ef2ee5d0SMichal Meloun 	PLATFORMMETHOD(platform_late_init,	tegra124_late_init),
1430dbb8873SAndrew Turner 	PLATFORMMETHOD(platform_cpu_reset,	tegra124_cpu_reset),
1440dbb8873SAndrew Turner 
145ef2ee5d0SMichal Meloun #ifdef SMP
146ef2ee5d0SMichal Meloun 	PLATFORMMETHOD(platform_mp_start_ap,	tegra124_mp_start_ap),
147ef2ee5d0SMichal Meloun 	PLATFORMMETHOD(platform_mp_setmaxid,	tegra124_mp_setmaxid),
148ef2ee5d0SMichal Meloun #endif
149ef2ee5d0SMichal Meloun 	PLATFORMMETHOD_END,
150ef2ee5d0SMichal Meloun };
151ef2ee5d0SMichal Meloun 
15292fa5c23SMichal Meloun FDT_PLATFORM_DEF(tegra124, "Nvidia Jetson-TK1", 0, "nvidia,jetson-tk1", 120);
153